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git01.mediatek.com / filogic / uboot / ac858d116db7f78fba75fa643c362ceae92b0f24 / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 2927c5e Disable unused chip-select for DDR controller interleaving by York Sun · Mon Oct 18 13:46:50 2010 -0700
  2. 5207e77 Fix parameters to support RDIMM for P2020DS by York Sun · Fri Aug 27 16:25:56 2010 -0500
  3. 1714e49 powerpc/8xxx: Improvement to DDR parameters by york · Fri Jul 02 22:25:56 2010 +0000
  4. de87932 powerpc/8xxx: Enable DDR3 RDIMM support by york · Fri Jul 02 22:25:55 2010 +0000
  5. 4260372 powerpc/8xxx: Enabled address hashing for 85xx by york · Fri Jul 02 22:25:54 2010 +0000
  6. f4f93c6 powerpc/8xxx: Enable quad-rank DIMMs. by york · Fri Jul 02 22:25:53 2010 +0000
  7. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  8. 8107926 fsl-ddr: Add extra cycle to turnaround times by Dave Liu · Tue Dec 08 11:56:48 2009 +0800
  9. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  10. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/ctrl_regs.c]
  11. 3525e1a fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 by Dave Liu · Fri Mar 05 12:22:00 2010 +0800
  12. 625b268 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · Wed Dec 16 10:24:39 2009 -0600
  13. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · Wed Dec 16 10:24:38 2009 -0600
  14. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · Wed Dec 16 10:24:37 2009 -0600
  15. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · Wed Dec 16 10:24:36 2009 -0600
  16. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · Thu Sep 10 14:54:55 2009 -0500
  17. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  18. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  19. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  20. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · Sat Mar 14 12:48:19 2009 +0800
  21. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  22. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  23. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · Fri Nov 21 16:31:22 2008 +0800
  24. d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
  25. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  26. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  27. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500