Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 9626f5acbb5b0bc8874ead46e5836a4abd3dcb36 / drivers / ddr
  1. d3e6816 Revert "drivers/ddr/fsl: Dual-license DDR driver" by Tom Rini · Wed Feb 14 21:34:05 2018 -0500
  2. 6d49eda drivers/ddr/fsl: Dual-license DDR driver by York Sun · Wed Feb 07 11:47:22 2018 -0800
  3. 74588bb drivers/ddr/fsl: Cleanup unused variable by York Sun · Mon Jan 29 09:44:38 2018 -0800
  4. 194c2f4 drivers/ddr/fsl: Modify binding registers to save time on data init by York Sun · Mon Jan 29 09:44:37 2018 -0800
  5. bc2f32a drivers/ddr/fsl: Add calculation of register control words by York Sun · Mon Jan 29 10:24:08 2018 -0800
  6. 6db4fdd drivers/ddr/fsl: Add 3DS RDIMM support by York Sun · Mon Jan 29 09:44:35 2018 -0800
  7. 2a4859e drivers/ddr/fsl: Fix workaround for A009803 by York Sun · Mon Jan 29 09:44:34 2018 -0800
  8. d9f7fa0 drivers/ddr/fsl: Fix DDR4 RDIMM support by York Sun · Mon Jan 29 09:44:33 2018 -0800
  9. c00a369 Merge git://git.denx.de/u-boot-socfpga by Tom Rini · Sat Jan 27 14:48:41 2018 -0500
  10. 60649bb Merge git://git.denx.de/u-boot-spi by Tom Rini · Fri Jan 26 07:46:34 2018 -0500
  11. a4af914 ddr: altera: silence PHY calibration unless in debug mode by Goldschmidt Simon · Thu Jan 25 06:04:44 2018 +0000
  12. 918de03 wait_bit: use wait_for_bit_le32 and remove wait_for_bit by Álvaro Fernández Rojas · Tue Jan 23 17:14:55 2018 +0100
  13. 661bc24 ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs by Rajesh Bhagat · Wed Jan 17 16:13:06 2018 +0530
  14. 5450f0c ddr: marvell: update ddr controller init and freq by Chris Packham · Thu Jan 18 17:16:10 2018 +1300
  15. d5c581c ddr: marvell: update additional ODT setting by Chris Packham · Thu Jan 18 17:16:09 2018 +1300
  16. 1324fab ddr: marvell: use correct TREFI value by Chris Packham · Thu Jan 18 17:16:08 2018 +1300
  17. ae80614 ddr: marvell: only assert M_ODT[0] on write for a single CS by Chris Packham · Thu Jan 18 17:16:07 2018 +1300
  18. b25faa2 armv8: ls1088a: Add NXP LS1088A SoC support by Ashish Kumar · Thu Aug 31 16:12:53 2017 +0530
  19. 64b723f env: Rename getenv/_f() to env_get() by Simon Glass · Thu Aug 03 12:22:12 2017 -0600
  20. 273d3f7 arm: mvebu: ddr3_debug: remove self assignments by xypron.glpk@gmx.de · Sun Jul 30 21:54:56 2017 +0200
  21. 94e8daa arm: mvebu: remove self assignment by xypron.glpk@gmx.de · Sun Jul 30 21:51:05 2017 +0200
  22. f8bf75f driver/ddr: Add support for setting timing in hws_topology_map by Marek Behún · Fri Jun 09 19:28:40 2017 +0200
  23. 622b7b3 treewide: remove unneeded semicolons by Masahiro Yamada · Tue Jun 13 15:17:28 2017 +0900
  24. f43278e driver: ddr: fsl: Fix compiling error for DDR2 by York Sun · Thu May 25 17:03:23 2017 -0700
  25. 89e0a3a common: arm: freescale: layerscape: Move header files out of common.h by Simon Glass · Wed May 17 08:23:10 2017 -0600
  26. 243182c common: freescale: Move arch-specific declarations by Simon Glass · Wed May 17 08:23:06 2017 -0600
  27. cffa503 Merge git://git.denx.de/u-boot-fsl-qoriq by Tom Rini · Tue Apr 18 11:36:06 2017 -0400
  28. 5fecf83 ddr: fsl: incorrect logical constraint in populate_memctl_options by xypron.glpk@gmx.de · Sat Apr 15 15:23:49 2017 +0200
  29. 7d2e8e4 drivers: ddr: fsl: fix unused-const-variable warnings by Thomas Schaefer · Tue Mar 28 11:29:56 2017 -0700
  30. 03017c5 Merge branch 'master' of git://git.denx.de/u-boot-socfpga by Tom Rini · Fri Apr 14 09:05:57 2017 -0400
  31. 016539e arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig by Ley Foon Tan · Wed Apr 05 17:32:51 2017 +0800
  32. d35f338 board_f: Rename initdram() to dram_init() by Simon Glass · Thu Apr 06 12:47:05 2017 -0600
  33. 39f90ba board_f: Drop return value from initdram() by Simon Glass · Fri Mar 31 08:40:25 2017 -0600
  34. fe84507 ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS by York Sun · Wed Dec 28 08:43:45 2016 -0800
  35. dcd28c0 ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig by York Sun · Wed Dec 28 08:43:44 2016 -0800
  36. be73553 powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig by York Sun · Wed Dec 28 08:43:43 2016 -0800
  37. 1dc61ca arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig by York Sun · Wed Dec 28 08:43:41 2016 -0800
  38. d297d39 fsl_ddr: Move DDR config options to driver Kconfig by York Sun · Wed Dec 28 08:43:40 2016 -0800
  39. 15875a5 fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum by Shengzhou Liu · Mon Nov 21 11:36:48 2016 +0800
  40. 7566ac1 fsl/ddr: Fix compiling warning by Shengzhou Liu · Mon Nov 21 11:36:47 2016 +0800
  41. 32be34d powerpc: MPC8555: Remove macro CONFIG_MPC8555 by York Sun · Wed Nov 16 11:23:23 2016 -0800
  42. bf820c0 powerpc: mpc8541: Remove macro CONFIG_MPC8541 by York Sun · Wed Nov 16 11:18:31 2016 -0800
  43. 3ea5951 ddr: altera: Configuring SDRAM extra cycles timing parameters by Chin Liang See · Wed Sep 21 10:25:56 2016 +0800
  44. c5b1e5d Various, accumulated typos collected from around the tree. by Robert P. J. Day · Wed Sep 07 14:27:59 2016 -0400
  45. 71c10a4 Merge git://git.denx.de/u-boot-fsl-qoriq by Tom Rini · Mon Sep 26 13:24:46 2016 -0400
  46. c1e979b driver: ddr: fsl_mmdc: Pass board parameters through data structure by York Sun · Mon Sep 26 08:09:25 2016 -0700
  47. 30fe357 drivers: squash lines for immediate return by Masahiro Yamada · Tue Sep 06 22:17:39 2016 +0900
  48. 3350e37 ddr: fsl: fix a compile issue by Shaohui Xie · Wed Sep 07 17:56:06 2016 +0800
  49. cb7fb12 driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a by Shengzhou Liu · Fri Aug 26 18:30:39 2016 +0800
  50. 36af3d3 driver/ddr/fsl: Revise workaround A008511 for A009803 by York Sun · Mon Aug 29 17:04:13 2016 +0800
  51. 7c72578 driver/ddr/fsl: Add more debug registers by York Sun · Mon Aug 29 17:04:12 2016 +0800
  52. e3cef9f driver/ddr/fsl: Fix timing_cfg_2 by York Sun · Fri Jul 29 09:02:29 2016 -0700
  53. 8d56db9 Various, unrelated tree-wide typo fixes. by Robert P. J. Day · Fri Jul 15 13:44:45 2016 -0400
  54. 4be68d0 driver/ddr/fsl: Check condition for erratum A-009803 by Shengzhou Liu · Wed May 25 16:15:00 2016 +0800
  55. 2a77a12 drivers/ddr/fsl: Disabling data init if ECC is not enabled by York Sun · Thu May 26 12:19:03 2016 -0700
  56. 3abd16b drivers/ddr/fsl: Fix timing_cfg_2 register by York Sun · Wed May 18 21:11:19 2016 -0700
  57. 3b33dd2 drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl by Shengzhou Liu · Wed May 04 10:20:21 2016 +0800
  58. c4a11bc Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq by Tom Rini · Tue May 24 13:42:03 2016 -0400
  59. 31fdba2 arm: mvebu: a38x: Weed out floating point use by Marek Vasut · Sat Apr 30 14:45:42 2016 +0200
  60. c72d12e driver/ddr/fsl: Add workaround for erratum A-010165 by Shengzhou Liu · Tue May 10 16:03:47 2016 +0800
  61. 9c3cdc2 driver/ddr/fsl: Add workaround for erratum A-009801 by Shengzhou Liu · Wed Mar 16 13:50:23 2016 +0800
  62. b2dee26 drivers/ddr/fsl: update workaround for erratum A-008511 by Shengzhou Liu · Wed Mar 16 13:50:22 2016 +0800
  63. edfdb99 Fix spelling of "occurred". by Vagrant Cascadian · Sat Apr 30 19:18:00 2016 -0700
  64. 66acabc ddr: altera: Repair DQ window centering code by Marek Vasut · Tue Apr 05 23:17:35 2016 +0200
  65. a4b9fa1 ddr: altera: Staticize global variables by Marek Vasut · Tue Apr 05 11:18:38 2016 +0200
  66. 4df2d7b ddr: altera: Make DLEVEL behavior inclusive by Marek Vasut · Mon Apr 04 21:21:05 2016 +0200
  67. f4d3862 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() by Marek Vasut · Mon Apr 04 21:16:18 2016 +0200
  68. 2bf2ee5 ddr: altera: Remove unnecessary ODT mode config by Marek Vasut · Mon Apr 04 19:10:12 2016 +0200
  69. acee8fd ddr: altera: Remove unnecessary update of the SCC by Marek Vasut · Mon Apr 04 18:41:53 2016 +0200
  70. 12361a2 ddr: altera: Fix DRAM end value in protection rule by Marek Vasut · Mon Apr 04 17:52:21 2016 +0200
  71. 45ce296 ddr: altera: Fix scc_mgr_set() argument order by Marek Vasut · Mon Apr 04 17:28:16 2016 +0200
  72. 6946989 ddr: altera: Tweak DQS tracking enable handling by Marek Vasut · Tue Apr 05 23:41:56 2016 +0200
  73. 2654bc9 ddr: altera: Replace ad-hoc constant with macro by Marek Vasut · Mon Apr 04 16:07:11 2016 +0200
  74. 0137e60 Fix typo choosen in comments and printf logs by Alexander Merkle · Thu Mar 17 15:44:47 2016 +0100
  75. 5b2c16a arm: mvebu: Fix ddr3_init() cpu config by Dirk Eibach · Wed Oct 28 16:44:15 2015 +0100
  76. b03e1b1 driver/ddr/fsl: Add workaround for erratum A-009803 by Shengzhou Liu · Thu Mar 10 17:36:57 2016 +0800
  77. 5219944 driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete by Shengzhou Liu · Thu Mar 10 17:36:56 2016 +0800
  78. 7557405 Use correct spelling of "U-Boot" by Bin Meng · Fri Feb 05 19:30:11 2016 -0800
  79. e80d11f drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32. by Purna Chandra Mandal · Thu Jan 28 15:30:15 2016 +0530
  80. 7ae7a0e drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers by Ed Swarthout · Thu Jan 14 12:28:04 2016 -0600
  81. bdda96c driver/ddr/fsl: Add workaround for A009663 by Shengzhou Liu · Wed Dec 16 16:45:41 2015 +0800
  82. fa2e2fb fsl/ddr: Add workaround for ERRATUM_A009942 by Shengzhou Liu · Wed Jan 06 11:26:51 2016 +0800
  83. e237880 Add more SPDX-License-Identifier tags by Tom Rini · Thu Jan 14 22:05:13 2016 -0500
  84. 42aa46d ddr: altera: Init the rule ID in debug code by Marek Vasut · Tue Dec 29 09:38:52 2015 +0100
  85. d911168 mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT by Phil Sutter · Fri Dec 25 14:41:23 2015 +0100
  86. 33aa8de axp: Fix debugging support in DDR3 write leveling by Phil Sutter · Fri Dec 25 14:41:19 2015 +0100
  87. ff7ad17 arm: mvebu: Make ECC support configurable on Armada XP by Stefan Roese · Thu Dec 10 15:02:38 2015 +0100
  88. 3c6b6fc arm: mvebu: ddr: Fix compilation warning by Stefan Roese · Thu Nov 19 13:50:10 2015 +0100
  89. fae8805 move erratum a008336 and a008514 to soc specific file by Yao Yuan · Sat Dec 05 14:59:14 2015 +0800
  90. 5a46e43 fsl/ddr: updated ddr errata-A008378 for arm and power SoCs by Shengzhou Liu · Fri Nov 20 15:52:04 2015 +0800
  91. 77594b3 driver/ddr/fsl: Update timing config for heavy load by York Sun · Wed Nov 04 10:03:21 2015 -0800
  92. 780ae3d driver/ddr/fsl: Update workaround for A008511 for vref range by York Sun · Wed Nov 04 10:03:20 2015 -0800
  93. d192126 driver/ddr/fsl: Update MR5 RTT park by York Sun · Wed Nov 04 10:03:19 2015 -0800
  94. d4d97ef driver/ddr/fsl: Update DDR4 MR6 for Vref range by York Sun · Wed Nov 04 10:03:18 2015 -0800
  95. 5cb12f6 driver/ddr/fsl: Update DDR4 RTT values by York Sun · Wed Nov 04 10:03:17 2015 -0800
  96. 68c19d7 drivers/ddr/fsl: Fix typo in BIST test for DDR4 by York Sun · Fri Nov 06 09:58:46 2015 -0800
  97. d957a67 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 by York Sun · Wed Nov 04 09:53:10 2015 -0800
  98. 77f7ded armv8: ls2085a: Add support of LS2085A SoC by Prabhakar Kushwaha · Mon Nov 09 16:42:20 2015 +0530
  99. 122bcfd armv8: LS2080A: Rename LS2085A to reflect LS2080A by Prabhakar Kushwaha · Mon Nov 09 16:42:07 2015 +0530
  100. dea4e33 arm: mvebu: Fix SAR1_CPU_CORE_MASK by Dirk Eibach · Wed Oct 28 16:44:14 2015 +0100