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git01.mediatek.com / filogic / uboot / 85741a2088a704199baa7c81797f646cbb784d8c / arch / riscv / cpu
  1. 26190b8 riscv: cpu: fu740: clear feature disable CSR by Green Wan · 3 years, 6 months ago
  2. ecefa5f drivers: clk: add fu740 support by Green Wan · 3 years, 6 months ago
  3. 7f33743 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · 3 years, 6 months ago
  4. 4bebdd3 treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · 3 years, 6 months ago
  5. 1255ab8 riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · 3 years, 7 months ago
  6. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · 3 years, 7 months ago
  7. b1b3bc0 Revert "riscv: cpu: fu740: clear feature disable CSR" by Bin Meng · 3 years, 7 months ago
  8. 968a13f riscv: cpu: fu740: clear feature disable CSR by Green Wan · 3 years, 7 months ago
  9. 2612080 riscv: cpu: Add callback to init each core by Green Wan · 3 years, 7 months ago
  10. 2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · 3 years, 9 months ago
  11. b1db71b Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · 3 years, 10 months ago
  12. 489b25a riscv: Adjust board_get_usable_ram_top() for 32-bit by Bin Meng · 3 years, 10 months ago
  13. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · 4 years, 1 month ago
  14. 4b96c88 riscv: fix the wrong swap value register by Brad Kim · 4 years ago
  15. 4f1b444 riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · 4 years ago
  16. 5a23865 timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · 4 years, 1 month ago
  17. 5bdad9f riscv: Add some comments to start.S by Sean Anderson · 4 years, 2 months ago
  18. 2c4c7d1 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · 4 years, 2 months ago
  19. 934b24a riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · 4 years, 2 months ago
  20. dd1cd70 riscv: Clear pending IPIs on initialization by Sean Anderson · 4 years, 2 months ago
  21. e8de08b Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · 4 years, 2 months ago
  22. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · 4 years, 2 months ago
  23. 54bcf26 riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · 4 years, 3 months ago
  24. 03de50e riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · 4 years, 4 months ago
  25. 6b15551 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · 4 years, 4 months ago
  26. 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · 4 years, 4 months ago
  27. 4e3ba2a riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · 4 years, 5 months ago
  28. e70ef90 env: Enable SPI flash env for SiFive FU540 by Jagan Teki · 4 years, 5 months ago
  29. 257875d riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · 4 years, 4 months ago
  30. 90fa4e9 Merge branch 'next' by Tom Rini · 4 years, 5 months ago
  31. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · 4 years, 6 months ago
  32. 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · 4 years, 5 months ago
  33. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · 4 years, 5 months ago
  34. 84df2e1 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · 4 years, 5 months ago
  35. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · 4 years, 6 months ago
  36. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · 4 years, 6 months ago
  37. 45b4ad9d riscv: Add _image_binary_end for SPL by Pragnesh Patel · 4 years, 6 months ago
  38. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · 4 years, 7 months ago
  39. 9758973 common: Drop init.h from common header by Simon Glass · 4 years, 7 months ago
  40. 274e0b0 common: Drop net.h from common header by Simon Glass · 4 years, 7 months ago
  41. 111b804 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · 4 years, 7 months ago
  42. b161f90 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · 4 years, 8 months ago
  43. 88fc2a5 riscv: Merge unnecessary SMP ifdefs in start.S by Bin Meng · 4 years, 8 months ago
  44. 6c1e6dd riscv: qemu: Remove the simple-bus driver for the SoC node by Bin Meng · 4 years, 8 months ago
  45. d12b55b riscv: ax25: cache: Remove SPL_RISCV_MMODE config check by Pragnesh Patel · 4 years, 9 months ago
  46. 750fee5 riscv: Remove unnecessary instruction by Sean Anderson · 4 years, 10 months ago
  47. e8b46a1 riscv: Add option to print registers on exception by Sean Anderson · 5 years ago
  48. 5e75a27 riscv: Fix breakage caused by linker relaxation by Sean Anderson · 5 years ago
  49. 284f71b common: Move relocate_code() to init.h by Simon Glass · 5 years ago
  50. c308e01 riscv: add option to wait for ack from secondary harts in smp functions by Lukas Auer · 5 years ago
  51. 55bc1bd riscv: Fix clear bss loop in the start-up code by Rick Chen · 5 years ago
  52. 883275d riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL by Rick Chen · 5 years ago
  53. 276292a riscv: ax25: add SPL support by Rick Chen · 5 years ago
  54. 6980b6b common: Move board_get_usable_ram_top() out of common.h by Simon Glass · 5 years ago
  55. 8f3f761 common: Move enable/disable_interrupts out of common.h by Simon Glass · 5 years ago
  56. 6333448 common: Move ARM cache operations out of common.h by Simon Glass · 5 years ago
  57. 1d91ba7 common: Move some cache and MMU functions out of common.h by Simon Glass · 5 years ago
  58. 49cb706 riscv: cache: use CCTL to flush d-cache by Rick Chen · 5 years ago
  59. 05a684e riscv: cache: Flush L2 cache before jump to linux by Rick Chen · 5 years ago
  60. 19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · 5 years ago
  61. b9ad45d riscv: update fix_rela_dyn by Marcus Comstedt · 5 years ago
  62. 2a2a925 riscv: support SPL stack and global data relocation by Lukas Auer · 5 years ago
  63. 396f0bd riscv: add SPL support by Lukas Auer · 5 years ago
  64. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
  65. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · 5 years ago
  66. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · 6 years ago
  67. 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · 6 years ago
  68. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · 6 years ago
  69. f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · 6 years ago
  70. 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · 6 years ago
  71. cddde09 riscv: hang if relocation of secondary harts fails by Lukas Auer · 6 years ago
  72. 9ebf294 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · 6 years ago
  73. a359665 riscv: add support for multi-hart systems by Lukas Auer · 6 years ago
  74. 8de4b3e riscv: save hart ID in register tp instead of s0 by Lukas Auer · 6 years ago
  75. 01558e2 riscv: delay initialization of caches and debug UART by Lukas Auer · 6 years ago
  76. 0bbe9cf riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems by Anup Patel · 6 years ago
  77. 1240cd6 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · 6 years ago
  78. 6280e32 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · 6 years ago
  79. 89681a7 riscv: Save boot hart id to the global data by Bin Meng · 6 years ago
  80. 1f46f6d riscv: Return to previous privilege level after trap handling by Bin Meng · 6 years ago
  81. ea95452 riscv: Fix context restore before returning from trap handler by Bin Meng · 6 years ago
  82. 2e128a7 riscv: Move trap handler codes to mtrap.S by Bin Meng · 6 years ago
  83. a7544ed riscv: Do some basic architecture level cpu initialization by Bin Meng · 6 years ago
  84. edfe9a9 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · 6 years ago
  85. 2caa1ee riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · 6 years ago
  86. 7a3bbfb riscv: Probe cpus during boot by Bin Meng · 6 years ago
  87. 8fa4478 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · 6 years ago
  88. 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · 6 years ago
  89. 66c6935 riscv: qemu: Create a simple-bus driver for the soc node by Bin Meng · 6 years ago
  90. 2a21815 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · 6 years ago
  91. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · 6 years ago
  92. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · 6 years ago
  93. 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · 6 years ago
  94. 8598e6b riscv: do not blindly modify the mstatus CSR by Lukas Auer · 6 years ago
  95. 230ab8a riscv: remove unused labels in start.S by Lukas Auer · 6 years ago
  96. ccd035a Drop CONFIG_INIT_CRITICAL by Bin Meng · 6 years ago
  97. af51285 riscv: align mtvec on a 4-byte boundary by Lukas Auer · 6 years ago
  98. 7cf4368 riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · 6 years ago
  99. de8d80e riscv: Move do_reset() to a common place by Bin Meng · 6 years ago
  100. 8a8694d riscv: Add QEMU virt board support by Bin Meng · 6 years ago