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git01.mediatek.com / filogic / uboot / 6cdd8d8fe8b1932b506379dd42685f37258e17b8 / arch / arm / mach-socfpga / include / mach
  1. cfd0c54 arm: socfpga: Add misc support for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:43 2017 +0800
  2. 9ea8c5b arm: socfpga: Add pinmux for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:42 2017 +0800
  3. d33c203 arm: socfpga: Add sdram header file for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:41 2017 +0800
  4. c3b4963 arm: socfpga: Add system manager for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:40 2017 +0800
  5. ca40f29 arm: socfpga: Add clock driver for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:39 2017 +0800
  6. 778ed2c arm: socfpga: Add reset driver support for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:38 2017 +0800
  7. 05e8629 arm: socfpga: Add A10 macros by Ley Foon Tan · Wed Apr 26 02:44:37 2017 +0800
  8. b149f2b arm: socfpga: Restructure misc driver by Ley Foon Tan · Wed Apr 26 02:44:36 2017 +0800
  9. d5c5e3b arm: socfpga: Restructure system manager by Ley Foon Tan · Wed Apr 26 02:44:35 2017 +0800
  10. dd5d12d arm: socfpga: Restructure reset manager driver by Ley Foon Tan · Wed Apr 26 02:44:34 2017 +0800
  11. ec6f882 arm: socfpga: Restructure clock manager driver by Ley Foon Tan · Wed Apr 26 02:44:33 2017 +0800
  12. 19869ea ARM: socfpga: boot0 hook: remove macro from boot0 header file by Chee, Tien Fong · Wed Mar 29 11:49:16 2017 +0800
  13. 2492b9f arm: socfpga: set the mpuclk divider in the Altera group register by Dinh Nguyen · Tue Jan 31 12:33:08 2017 -0600
  14. bcd861b ARM: socfpga: Add boot0 hook to prevent SPL corruption by Marek Vasut · Wed Nov 16 17:20:23 2016 +0100
  15. 3ea5951 ddr: altera: Configuring SDRAM extra cycles timing parameters by Chin Liang See · Wed Sep 21 10:25:56 2016 +0800
  16. 734c066 arm: socfpga: Nuke useless include by Marek Vasut · Sat Mar 19 18:59:11 2016 +0100
  17. 8dcb5c5 arm: socfpga: Define NAND reset bit by Marek Vasut · Sun Dec 20 04:00:41 2015 +0100
  18. c4b66c4 arm: socfpga: fix up a questionable macro for SDMMC by Dinh Nguyen · Wed Dec 02 13:31:33 2015 -0600
  19. eca8b5c ARM: socfpga: rename the cyclone5 and arria5 base address file by Dinh Nguyen · Mon Nov 23 17:27:17 2015 -0600
  20. b1f95d6 ARM: socfpga: arria10: add base address map for Arria10 by Dinh Nguyen · Mon Nov 23 17:27:16 2015 -0600
  21. e3f7a45 arm: socfpga: reset: FIX address of tstscratch register by Philipp Rosenberger · Thu Nov 12 18:23:10 2015 +0100
  22. 200f0c5 arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines by Dinh Nguyen · Mon Nov 02 17:11:21 2015 -0600
  23. 1749723 mmc: dw_mmc: Probe the MMC from OF by Marek Vasut · Sat Jul 25 10:48:14 2015 +0200
  24. 7b64873 arm: socfpga: Make the pinmux table const u8 by Marek Vasut · Mon Aug 10 22:17:46 2015 +0200
  25. b640cae arm: socfpga: scan: Add code to get FPGA ID by Dinh Nguyen · Fri Jul 31 11:06:50 2015 -0500
  26. 65371c8 arm: socfpga: scan: Clean up horrible macros by Marek Vasut · Sat Aug 01 03:18:50 2015 +0200
  27. 24d12ec arm: socfpga: scan: Clean up scan_chain_engine_is_idle() by Marek Vasut · Sat Aug 01 02:48:03 2015 +0200
  28. f00a6ea ddr: altera: sequencer: Wrap misc remaining macros by Marek Vasut · Sun Aug 02 19:18:47 2015 +0200
  29. 3bf9204 ddr: altera: sequencer: Wrap IO_* macros by Marek Vasut · Sun Aug 02 19:00:23 2015 +0200
  30. 39b620e ddr: altera: sequencer: Wrap RW_MGR_* macros by Marek Vasut · Sun Aug 02 18:12:08 2015 +0200
  31. 3384e74 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init by Marek Vasut · Sun Aug 02 17:15:19 2015 +0200
  32. 14c5d9a ddr: altera: sequencer: Clean up mach/sdram.h by Marek Vasut · Sun Aug 02 17:02:11 2015 +0200
  33. 32ada57 ddr: altera: sdram: Introduce socfpga_sdram_get_config() by Marek Vasut · Sat Aug 01 21:35:18 2015 +0200
  34. 1b1cc10 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8 by Marek Vasut · Sat Aug 01 22:25:29 2015 +0200
  35. 33acf0f ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS by Marek Vasut · Sun Jul 12 20:05:54 2015 +0200
  36. 1100e34 arm: socfpga: system: Clean up pinmux_config.c by Marek Vasut · Sat Jul 25 11:09:11 2015 +0200
  37. 8306b1e arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio() by Marek Vasut · Thu Jul 09 04:40:11 2015 +0200
  38. 9c3e006 arm: socfpga: scan: Zap iocsr_scan_chain*_table() by Marek Vasut · Sat Jul 25 09:53:23 2015 +0200
  39. b4c1a00 arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg() by Marek Vasut · Sat Jul 25 09:33:28 2015 +0200
  40. 084d06c arm: socfpga: clock: Clean up pll_config.h by Marek Vasut · Sat Jul 25 08:44:27 2015 +0200
  41. 940077d arm: socfpga: clock: Get rid of cm_config_t typedef by Marek Vasut · Sat Jul 25 08:37:16 2015 +0200
  42. fc31d6e arm: socfpga: reset: Add SDMMC, QSPI and DMA defines by Marek Vasut · Thu Jul 09 04:28:13 2015 +0200
  43. 49edbd4 arm: socfpga: reset: Add function to reset add peripherals by Marek Vasut · Thu Jul 09 04:27:28 2015 +0200
  44. 75f6b5c arm: socfpga: reset: Replace ad-hoc reset functions by Marek Vasut · Thu Jul 09 02:51:56 2015 +0200
  45. 3425eeb arm: socfpga: reset: Implement unified function to toggle reset by Marek Vasut · Thu Jul 09 02:45:15 2015 +0200
  46. bb1f889 arm: socfpga: reset: Start reworking the SoCFPGA reset manager by Marek Vasut · Thu Jul 09 02:30:35 2015 +0200
  47. ab8f13f arm: socfpga: reset: Add missing reset manager regs by Marek Vasut · Thu Jul 09 03:39:06 2015 +0200
  48. e08c559 ddr: altera: Move struct sdram_prot_rule prototype by Marek Vasut · Sun Jul 26 10:37:54 2015 +0200
  49. 43bb47e arm: socfpga: Move sdram_config.h to board dir by Marek Vasut · Sun Jul 12 15:59:10 2015 +0200
  50. 429642c driver/ddr/altera: Add DDR driver for Altera's SDRAM controller by Dinh Nguyen · Tue Jun 02 22:52:48 2015 -0500
  51. cfcf5d6 ARM: socfpga: move SoC headers to mach-socfpga/include/mach by Masahiro Yamada · Tue Apr 21 20:38:22 2015 +0900