| commit | ec6f8825a740ba74b523b72e6d8003491b7bf07f | [log] [tgz] |
|---|---|---|
| author | Ley Foon Tan <ley.foon.tan@intel.com> | Wed Apr 26 02:44:33 2017 +0800 |
| committer | Marek Vasut <marex@denx.de> | Thu May 18 11:33:16 2017 +0200 |
| tree | 2f688d87f0559d5c19d48f633681abffd10d5f52 | |
| parent | c1047f66b2764e9d2ae9b5098991dbd4158537ff [diff] |
arm: socfpga: Restructure clock manager driver Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files. - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift. - Check return value from wait_for_bit(). So change return type to int for cm_write_with_phase() and cm_basic_init(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>