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git01.mediatek.com / filogic / uboot / 64c6c1e86b87c9291284b1a6c16a2e86749c4a73 / arch / mips / lib / cache_init.S
  1. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  2. 0286885 MIPS: Ensure cache ops complete in mips_cache_reset by Paul Burton · Wed Sep 21 11:18:59 2016 +0100
  3. ac8668a MIPS: Clear hazard between TagLo writes & cache ops by Paul Burton · Wed Sep 21 11:18:58 2016 +0100
  4. a8b8bd2 MIPS: Join the coherent domain when a CM is present by Paul Burton · Wed Sep 21 11:18:55 2016 +0100
  5. 8156078 MIPS: L2 cache support by Paul Burton · Wed Sep 21 11:18:54 2016 +0100
  6. f868be5 MIPS: Define register names for cache init by Paul Burton · Wed Sep 21 11:18:52 2016 +0100
  7. 8c57b04 MIPS: Enable use of the instruction cache earlier by Paul Burton · Wed Sep 21 11:18:49 2016 +0100
  8. 62f1352 MIPS: Split I & D cache line size config by Paul Burton · Fri May 27 14:28:05 2016 +0100
  9. 5e51142 MIPS: Move cache sizes to Kconfig by Paul Burton · Fri May 27 14:28:04 2016 +0100
  10. 53c9826 MIPS: Use unchecked immediate addition/subtraction by Paul Burton · Mon May 16 10:52:10 2016 +0100
  11. a6dae71 MIPS: sync processor and register definitions with linux-4.4 by Daniel Schwierzeck · Tue Jan 12 21:48:26 2016 +0100
  12. 69acad0 MIPS: clear TagLo select 2 during cache init by Paul Burton · Thu Jan 29 01:28:03 2015 +0000
  13. 6832bdc MIPS: allow systems to skip loads during cache init by Paul Burton · Thu Jan 29 01:28:02 2015 +0000
  14. ca41a03 MIPS: inline mips_init_[id]cache functions by Paul Burton · Thu Jan 29 01:28:01 2015 +0000
  15. d878cc2 MIPS: refactor cache loops to a macro by Paul Burton · Thu Jan 29 01:28:00 2015 +0000
  16. edf1f85 MIPS: refactor L1 cache config reads to a macro by Paul Burton · Thu Jan 29 01:27:59 2015 +0000
  17. 02df4e6 MIPS: unify cache initialization code by Paul Burton · Thu Jan 29 01:27:58 2015 +0000[Renamed (95%) from arch/mips/cpu/mips32/cache.S]
  18. 5429af8 MIPS: avoid .set ISA for cache operations by Paul Burton · Thu Jan 29 01:27:56 2015 +0000
  19. f122b5a mips32: detect L1 cache sizes if they're not defined by Paul Burton · Fri Nov 08 11:18:42 2013 +0000
  20. 02d51a2 MIPS: mips32/cache.S: use v1 register for indirect function calls by Gabor Juhos · Thu Jun 13 12:59:36 2013 +0200
  21. 5b4f4ff MIPS: mips32/cache.S: store cache line size in t8 register by Gabor Juhos · Thu Jun 13 12:59:35 2013 +0200
  22. 187fe81 MIPS: mips32/cache.S: save return address in t9 register by Gabor Juhos · Thu Jun 13 12:59:34 2013 +0200
  23. 9a26513 MIPS: mips32/cache.S: remove superfluous register assignment by Gabor Juhos · Wed Jun 12 18:02:46 2013 +0200
  24. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  25. 724f618 MIPS: don't use camel-case style by Zhi-zhou Zhang · Tue Oct 16 15:02:08 2012 +0200
  26. 9adc190 MIPS: fix inconsistency in config option for cache operation mode by Daniel Schwierzeck · Mon Apr 02 02:57:55 2012 +0000
  27. 6911d0a MIPS: Coding style cleanups on common assembly files by Shinya Kuribayashi · Sat May 07 00:18:13 2011 +0900
  28. 1949d53 MIPS: Remove mips_cache_lock() feature by Shinya Kuribayashi · Sat May 07 00:18:13 2011 +0900
  29. ce82730 MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32 by Daniel Schwierzeck · Mon Mar 28 18:33:55 2011 +0200[Renamed from arch/mips/cpu/cache.S]
  30. 95a3e6f MIPS: Purple: Remove Purple support by Daniel Schwierzeck · Mon Mar 28 18:33:54 2011 +0200
  31. 0191e47 Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value by Wolfgang Denk · Tue Oct 26 14:34:52 2010 +0200
  32. 1d85dee mips: Move cpu/mips/* to arch/mips/cpu/* by Peter Tyser · Mon Apr 12 22:28:14 2010 -0500[Renamed from cpu/mips/cache.S]
  33. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  34. 6c6b261 [MIPS] Update <asm/addrspace.h> header by Shinya Kuribayashi · Thu Jun 05 22:29:00 2008 +0900
  35. a0fbd83 [MIPS] Kill unused <version.h> inclusions by Shinya Kuribayashi · Thu Jun 05 22:29:00 2008 +0900
  36. b128882 [MIPS] cpu/mips/cache.S: Fix build warning by Shinya Kuribayashi · Tue May 06 13:22:52 2008 +0900
  37. 4d0e2c9 [MIPS] cpu/mips/cache.S: Add dcache_enable by Shinya Kuribayashi · Sat May 03 13:51:28 2008 +0900
  38. 9dabea1 Use jr as register jump instruction by Shinya Kuribayashi · Thu Apr 17 23:35:13 2008 +0900
  39. 396aa80 [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB by Shinya Kuribayashi · Tue Mar 25 21:30:07 2008 +0900
  40. 3bdce4f [MIPS] Fix dcache_status() by Shinya Kuribayashi · Tue Mar 25 21:30:07 2008 +0900
  41. 5bb51af [MIPS] Fix I-/D-cache initialization loops by Shinya Kuribayashi · Tue Mar 25 21:30:06 2008 +0900
  42. 52c27e6 [MIPS] Replace memory clearance code with f_fill64 by Shinya Kuribayashi · Tue Mar 25 21:30:06 2008 +0900
  43. 0622212 [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros by Shinya Kuribayashi · Tue Mar 25 21:30:06 2008 +0900
  44. b827589 [MIPS] Request for the 'mips_cache_lock()' removal by Shinya Kuribayashi · Tue Mar 25 11:39:29 2008 +0900
  45. c7faac5 [MIPS] MIPS 4K core: Coding style cleanups by Shinya Kuribayashi · Sat Oct 27 15:27:06 2007 +0900
  46. 9b7f384 * Patch by Steven Scholz, 10 Oct 2003 - Add support for Altera FPGA ACEX1K by wdenk · Thu Oct 09 20:09:04 2003 +0000
  47. 57b2d80 * Code cleanup: by wdenk · Fri Jun 27 21:31:46 2003 +0000
  48. a6db71d Prepare for 0.3.0 release by wdenk · Tue Apr 08 23:25:21 2003 +0000
  49. b02744a * Patch by Arun Dharankar, 4 Apr 2003: by wdenk · Sat Apr 05 00:53:31 2003 +0000
  50. bb1b826 * Add support for MIPS32 4Kc CPUs by wdenk · Thu Mar 27 12:09:35 2003 +0000