| commit | ac8668a8d7666a86385a0c98c487b46cf26b9d70 | [log] [tgz] |
|---|---|---|
| author | Paul Burton <paul.burton@imgtec.com> | Wed Sep 21 11:18:58 2016 +0100 |
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Wed Sep 21 15:04:04 2016 +0200 |
| tree | 08974b3c02079cc147794c9a28eab7f35e0cd156 | |
| parent | 82c9d89596e16994b716dfa08365808ea767900d [diff] |
MIPS: Clear hazard between TagLo writes & cache ops Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton <paul.burton@imgtec.com>