| commit | 69acad0b1ee9141531993d1be080e8ae89e90c6c | [log] [tgz] |
|---|---|---|
| author | Paul Burton <paul.burton@imgtec.com> | Thu Jan 29 01:28:03 2015 +0000 |
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Thu Jan 29 12:55:01 2015 +0100 |
| tree | b7730ef7f29fc91b729413d7f447075972f3a2f3 | |
| parent | 6832bdcef203816127b1fae723afc56e52fd5305 [diff] |
MIPS: clear TagLo select 2 during cache init Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>