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git01.mediatek.com / filogic / uboot / 64042099e61a8aa14cfd3ce3d9c91301d2d65d5d / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 8107926 fsl-ddr: Add extra cycle to turnaround times by Dave Liu · 15 years ago
  2. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · 15 years ago[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  3. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · 15 years ago[Renamed from cpu/mpc8xxx/ddr/ctrl_regs.c]
  4. 3525e1a fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 by Dave Liu · 15 years ago
  5. 625b268 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · 15 years ago
  6. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · 15 years ago
  7. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  8. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · 15 years ago
  9. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  10. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  11. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  12. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  13. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  14. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  15. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  16. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  17. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  18. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  19. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  20. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago