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git01.mediatek.com / filogic / uboot / 3761ffc0ca02f822575d36331fde27bc23031254 / arch / riscv
  1. 49cb706 riscv: cache: use CCTL to flush d-cache by Rick Chen · Wed Aug 28 18:46:11 2019 +0800
  2. 5ff8f41 riscv: dts: move out AE350 L2 node from cpus node by Rick Chen · Wed Aug 28 18:46:10 2019 +0800
  3. 05a684e riscv: cache: Flush L2 cache before jump to linux by Rick Chen · Wed Aug 28 18:46:09 2019 +0800
  4. 19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · Thu Aug 29 10:30:13 2019 +0800
  5. eaae83b riscv: andes_plic: init plic by scanning each cpu node by Rick Chen · Wed Aug 21 11:26:50 2019 +0800
  6. b9ad45d riscv: update fix_rela_dyn by Marcus Comstedt · Sun Aug 11 14:45:29 2019 +0200
  7. e9fbc71 riscv: add a generic FIT generator script by Lukas Auer · Wed Aug 21 21:14:47 2019 +0200
  8. 2a2a925 riscv: support SPL stack and global data relocation by Lukas Auer · Wed Aug 21 21:14:46 2019 +0200
  9. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  10. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  11. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · Wed Jul 10 23:43:13 2019 -0700
  12. a27264c riscv: Sync csr.h with Linux kernel v5.2 by Bin Meng · Wed Jul 10 23:43:12 2019 -0700
  13. 9cce6f7 env: Drop environment.h header file where not needed by Simon Glass · Thu Aug 01 09:47:12 2019 -0600
  14. d680e9a efi_loader: use predefined constants in crt0_*_efi.S by Heinrich Schuchardt · Thu Jul 11 06:39:32 2019 +0200
  15. 4216f34 riscv: Add Microchip MPFS Icicle board support by Padmarao Begari · Tue May 28 15:47:51 2019 +0530
  16. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · Fri May 03 09:41:00 2019 -0400
  17. ba64b8b CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig by Trevor Woerner · Fri May 03 09:40:59 2019 -0400
  18. 583b409 RISCV: image: Add booti support by Atish Patra · Mon May 06 17:49:39 2019 -0700
  19. 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · Tue Apr 30 13:49:35 2019 +0800
  20. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  21. a009fa7 dts: switch spi-flash to jedec, spi-nor compatible by Neil Armstrong · Sun Feb 10 10:16:20 2019 +0000
  22. 5ca381e riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure by Rick Chen · Wed Apr 03 10:43:37 2019 +0800
  23. 5e56cda riscv: dts: ae350 support SMP by Rick Chen · Tue Apr 02 15:56:43 2019 +0800
  24. f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · Tue Apr 02 15:56:42 2019 +0800
  25. 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · Tue Apr 02 15:56:41 2019 +0800
  26. 7376677 riscv: Add a SYSCON driver for Andestech's PLMT by Rick Chen · Tue Apr 02 15:56:40 2019 +0800
  27. 6df4ed0 riscv: Add a SYSCON driver for Andestech's PLIC by Rick Chen · Tue Apr 02 15:56:39 2019 +0800
  28. cddde09 riscv: hang if relocation of secondary harts fails by Lukas Auer · Sun Mar 17 19:28:40 2019 +0100
  29. 9ebf294 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · Sun Mar 17 19:28:39 2019 +0100
  30. c4a6c8f riscv: boot images passed to bootm on all harts by Lukas Auer · Sun Mar 17 19:28:38 2019 +0100
  31. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  32. 8de4b3e riscv: save hart ID in register tp instead of s0 by Lukas Auer · Sun Mar 17 19:28:36 2019 +0100
  33. 01558e2 riscv: delay initialization of caches and debug UART by Lukas Auer · Sun Mar 17 19:28:35 2019 +0100
  34. e79178b riscv: implement IPI platform functions using SBI by Lukas Auer · Sun Mar 17 19:28:34 2019 +0100
  35. 9c03845 riscv: import the supervisor binary interface header file by Lukas Auer · Sun Mar 17 19:28:33 2019 +0100
  36. 83d573d riscv: add infrastructure for calling functions on other harts by Lukas Auer · Sun Mar 17 19:28:32 2019 +0100
  37. 818d49a riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd by Anup Patel · Mon Feb 25 08:15:33 2019 +0000
  38. 7a167f2 riscv: Add SiFive FU540 board support by Anup Patel · Mon Feb 25 08:15:19 2019 +0000
  39. 0bbe9cf riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems by Anup Patel · Mon Feb 25 08:14:30 2019 +0000
  40. 6f07f45 riscv: Add place-holder asm/arch/clk.h for driver compilation by Anup Patel · Mon Feb 25 08:14:24 2019 +0000
  41. 928452a riscv: Add asm/dma-mapping.h for DMA mappings by Anup Patel · Mon Feb 25 08:14:17 2019 +0000
  42. 1240cd6 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · Mon Feb 25 08:14:10 2019 +0000
  43. bf12fe9 riscv: qemu: define standalone load address by Lukas Auer · Fri Jan 04 01:37:34 2019 +0100
  44. d4e2417 riscv: remove RISC-V standalone linker script by Lukas Auer · Fri Jan 04 01:37:31 2019 +0100
  45. 09dfc3c riscv: use invalidate/flush_*cache_range functions in cache.c by Lukas Auer · Fri Jan 04 01:37:30 2019 +0100
  46. 6280e32 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · Fri Jan 04 01:37:29 2019 +0100
  47. 8318e89 riscv: clarify error message on undefined exceptions by Lukas Auer · Fri Jan 04 01:37:28 2019 +0100
  48. e63488f riscv: bootm: Support booting VxWorks by Bin Meng · Fri Dec 21 07:13:41 2018 -0800
  49. f331b9b riscv: Remove ae350.dts by Bin Meng · Wed Dec 12 06:12:47 2018 -0800
  50. fda01b6 riscv: bootm: Change to use boot_hart from global data by Bin Meng · Wed Dec 12 06:12:46 2018 -0800
  51. 89681a7 riscv: Save boot hart id to the global data by Bin Meng · Wed Dec 12 06:12:45 2018 -0800
  52. bcc6c74 riscv: Adjust the _exit_trap() position to come before handle_trap() by Bin Meng · Wed Dec 12 06:12:44 2018 -0800
  53. 1f46f6d riscv: Return to previous privilege level after trap handling by Bin Meng · Wed Dec 12 06:12:43 2018 -0800
  54. ea95452 riscv: Fix context restore before returning from trap handler by Bin Meng · Wed Dec 12 06:12:42 2018 -0800
  55. 2e128a7 riscv: Move trap handler codes to mtrap.S by Bin Meng · Wed Dec 12 06:12:41 2018 -0800
  56. a7544ed riscv: Do some basic architecture level cpu initialization by Bin Meng · Wed Dec 12 06:12:40 2018 -0800
  57. 9e9e6fe riscv: Add indirect stringification to csr_xxx ops by Bin Meng · Wed Dec 12 06:12:39 2018 -0800
  58. edfe9a9 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · Wed Dec 12 06:12:38 2018 -0800
  59. 731e2d4 riscv: Add exception codes for xcause register by Bin Meng · Wed Dec 12 06:12:37 2018 -0800
  60. ea5086b riscv: Add CSR numbers by Bin Meng · Wed Dec 12 06:12:36 2018 -0800
  61. 2caa1ee riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · Wed Dec 12 06:12:35 2018 -0800
  62. 7a3bbfb riscv: Probe cpus during boot by Bin Meng · Wed Dec 12 06:12:34 2018 -0800
  63. dada2d1 riscv: Enlarge the default SYS_MALLOC_F_LEN by Bin Meng · Wed Dec 12 06:12:33 2018 -0800
  64. 8fa4478 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · Wed Dec 12 06:12:32 2018 -0800
  65. f3c8479 riscv: Implement riscv_get_time() API using rdtime instruction by Anup Patel · Wed Dec 12 06:12:31 2018 -0800
  66. b6ee5e1 riscv: Add a SYSCON driver for SiFive's Core Local Interruptor by Bin Meng · Wed Dec 12 06:12:30 2018 -0800
  67. 2788177 riscv: Introduce a Kconfig option for machine mode by Anup Patel · Wed Dec 12 06:12:29 2018 -0800
  68. 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · Wed Dec 12 06:12:28 2018 -0800
  69. 66c6935 riscv: qemu: Create a simple-bus driver for the soc node by Bin Meng · Wed Dec 12 06:12:25 2018 -0800
  70. ecc5d83 riscv: add Kconfig entries for the code model by Lukas Auer · Wed Dec 12 06:12:23 2018 -0800
  71. 2a21815 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · Mon Dec 03 17:48:20 2018 +0800
  72. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · Mon Dec 03 10:57:40 2018 +0530
  73. 5354888 riscv: efi: Generate Microsoft PE format compliant images by Bin Meng · Tue Oct 02 07:39:34 2018 -0700
  74. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  75. baaa062 riscv: dts: Add ae350_32.dts for RV32I by Rick Chen · Tue Nov 13 16:33:29 2018 +0800
  76. 2dab6d4 riscv: dts: Sync to Linux Kernel ae350 dts. by Rick Chen · Tue Nov 13 15:13:34 2018 +0800
  77. 86feab3 riscv: align bootm implementation with that of other architectures by Lukas Auer · Thu Nov 22 11:26:32 2018 +0100
  78. 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · Thu Nov 22 11:26:29 2018 +0100
  79. 8598e6b riscv: do not blindly modify the mstatus CSR by Lukas Auer · Thu Nov 22 11:26:28 2018 +0100
  80. 230ab8a riscv: remove unused labels in start.S by Lukas Auer · Thu Nov 22 11:26:27 2018 +0100
  81. ccd035a Drop CONFIG_INIT_CRITICAL by Bin Meng · Thu Nov 22 11:26:26 2018 +0100
  82. af51285 riscv: align mtvec on a 4-byte boundary by Lukas Auer · Thu Nov 22 11:26:25 2018 +0100
  83. 7cf4368 riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · Thu Nov 22 11:26:24 2018 +0100
  84. 7656228 riscv: implement the invalidate_icache_* functions by Lukas Auer · Thu Nov 22 11:26:23 2018 +0100
  85. 306b31d riscv: hang on unhandled exceptions by Lukas Auer · Thu Nov 22 11:26:22 2018 +0100
  86. ae525d5 riscv: treat undefined exception codes as reserved by Lukas Auer · Thu Nov 22 11:26:21 2018 +0100
  87. 40f7eb5 riscv: complete the list of exception codes by Lukas Auer · Thu Nov 22 11:26:20 2018 +0100
  88. 09db5fc riscv: do not reimplement generic io functions by Lukas Auer · Thu Nov 22 11:26:19 2018 +0100
  89. 78da26d riscv: make use of the barrier functions from Linux by Lukas Auer · Thu Nov 22 11:26:18 2018 +0100
  90. e429a1e riscv: fix use of incorrectly sized variables by Lukas Auer · Thu Nov 22 11:26:17 2018 +0100
  91. 93478f1 riscv: enable -fdata-sections by Lukas Auer · Thu Nov 22 11:26:16 2018 +0100
  92. 17d3e90 riscv: set -march and -mabi based on the Kconfig configuration by Lukas Auer · Thu Nov 22 11:26:15 2018 +0100
  93. 002012f riscv: add Kconfig entries for the C and A ISA extensions by Lukas Auer · Thu Nov 22 11:26:14 2018 +0100
  94. 7ab1df0 riscv: select CONFIG_PHYS_64BIT on RV64I systems by Lukas Auer · Thu Nov 22 11:26:13 2018 +0100
  95. 54ebfe7 riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I by Lukas Auer · Thu Nov 22 11:26:12 2018 +0100
  96. 401885a Use _AC and UL macros from linux/const.h by Baruch Siach · Sun Nov 11 12:31:01 2018 +0200
  97. 9dc13da Kbuild: add LDFLAGS_STANDALONE by Daniel Schwierzeck · Sun Sep 23 19:15:15 2018 +0200
  98. 635a253 riscv: bootm: Add dm_remove_devices_flags() call to do_bootm_linux() by Bin Meng · Mon Oct 15 02:20:59 2018 -0700
  99. 920f7dc riscv: allow native compilation by Heinrich Schuchardt · Mon Aug 06 19:15:38 2018 +0200
  100. f25398e riscv: cosmetic: Reword do_reset() printf message. by Rick Chen · Wed Oct 03 13:59:03 2018 +0800