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git01.mediatek.com / filogic / uboot / 324cb4d73d2883138305686b6f013e9e84de580d / arch / riscv / dts / jh7110.dtsi
  1. ecfd53c riscv: dts: jh7110: add power management unit controller node by Nam Cao · Mon Jan 29 09:43:08 2024 +0100
  2. 0fe44f6 riscv: dts: jh7110: Add watchdog device tree node by Chanho Park · Mon Nov 06 08:13:17 2023 +0900
  3. 601941c riscv: dts: jh7110: Add rng device tree node by Chanho Park · Wed Nov 01 21:16:51 2023 +0900
  4. 42fa87e riscv: jh7110: enable riscv,timer in the device tree by Torsten Duwe · Mon Aug 14 18:05:33 2023 +0200
  5. 23dfd81 riscv: dts: starfive: Enable PCIe host controller by Mason Huo · Tue Jul 25 17:46:50 2023 +0800
  6. 1345c9e riscv: dts: jh7110: Add clock source from PLL by Xingyu Wu · Fri Jul 07 18:50:09 2023 +0800
  7. 7ae81bb riscv: dts: jh7110: Add PLL clock controller node by Xingyu Wu · Fri Jul 07 18:50:08 2023 +0800
  8. 7f63bd9 riscv: dts: jh7110: Add ethernet device tree nodes by Yanhong Wang · Thu Jun 15 17:36:44 2023 +0800
  9. 96c3eb72 riscv: dts: jh7110: Add initial StarFive JH7110 device tree by Yanhong Wang · Wed Mar 29 11:42:21 2023 +0800