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git01.mediatek.com / filogic / uboot / 2d0f125d88788dffaf899d0046c49699084c14d1 / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · 15 years ago
  2. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  3. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · 15 years ago
  4. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  5. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  6. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  7. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  8. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  9. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  10. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  11. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  12. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  13. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  14. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  15. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago