Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 2d0f125d88788dffaf899d0046c49699084c14d1 / cpu / mpc8xxx
  1. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · 15 years ago
  2. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  3. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · 15 years ago
  4. a6c612c ppc/8xxx: Remove is_fsl_pci_agent by Kumar Gala · 15 years ago
  5. b49b09b ppc/8xxx: Don't use pci_cfg on FSL_CORENET platforms by Kumar Gala · 15 years ago
  6. 0f9318f fsl-ddr: Fix the chip-select interleaving issue by Dave Liu · 15 years ago
  7. 63fa48d mpc8xxx: improve LAW error messages when setting up DDR by Paul Gortmaker · 15 years ago
  8. bb5409c ppc/p4080: Add various p4080 related defines (and p4040) by Kumar Gala · 16 years ago
  9. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  10. 36a6843 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). by Poonam Aggrwal · 15 years ago
  11. 4ca72ae ppc/85xx/86xx: Device tree fixup for number of cores by Poonam Aggrwal · 15 years ago
  12. da6e1ca ppc/85xx,86xx: Handling Unknown SOC version by Poonam Aggrwal · 15 years ago
  13. 666ced1 ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host by Kumar Gala · 15 years ago
  14. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  15. 13e21b1 85xx: Added single core members of FSL P1xx/P2xx processors series by Poonam Aggrwal · 15 years ago
  16. dfe86a7 85xx: Added P1020 Processor Support. by Poonam Aggrwal · 15 years ago
  17. 4baef82 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx by Poonam Aggrwal · 15 years ago
  18. 9120884 8xxx: Refactored common cpu specific code for 85xx/86xx into one file. by Poonam Aggrwal · 15 years ago
  19. f4018f9 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  20. efb8ce3 fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more by Timur Tabi · 15 years ago
  21. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  22. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  23. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  24. 45eea1d fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  25. c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · 16 years ago
  26. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  27. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  28. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  29. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  30. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  31. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  32. b834f92 Check DDR interleaving mode by Haiying Wang · 16 years ago
  33. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  34. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  35. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  36. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  37. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  38. fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  39. 711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  40. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago