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git01.mediatek.com / filogic / uboot / 25abdb38ec4ec9b97b33cd907ee017e02871a7c3 / drivers / clk / renesas
  1. 7885dca clk: renesas: Drop include common.h by Marek Vasut · Sun Jan 21 18:31:21 2024 +0100
  2. 8319840 clk: renesas: Synchronize RZ R8A774E1 RZ/G2H clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:20 2023 +0100
  3. 8d712ee clk: renesas: Synchronize RZ R8A774C0 RZ/G2E clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:19 2023 +0100
  4. 8a8e103 clk: renesas: Synchronize RZ R8A774B1 RZ/G2N clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:18 2023 +0100
  5. aa50693 clk: renesas: Synchronize RZ R8A774A1 RZ/G2M clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:17 2023 +0100
  6. f689f58 clk: renesas: Synchronize R-Car R8A77995 D3 clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:16 2023 +0100
  7. f887994 clk: renesas: Synchronize R-Car R8A77990 E3 clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:15 2023 +0100
  8. 68f8e87 clk: renesas: Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:14 2023 +0100
  9. e1418a0 clk: renesas: Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.6.3 by Marek Vasut · Sun Dec 03 14:15:13 2023 +0100
  10. cb2a62e clk: rzg2l: Drop <common.h> by Paul Barker · Wed Nov 01 20:05:58 2023 +0000
  11. 132d7ea clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver by Paul Barker · Mon Oct 16 10:25:29 2023 +0100
  12. 436358e clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:41 2023 +0200
  13. 2f8e987 clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:40 2023 +0200
  14. 618da65 clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:39 2023 +0200
  15. 8fbe782 clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:38 2023 +0200
  16. 3c7646e clk: renesas: Synchronize R8A779G0 V4H clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:37 2023 +0200
  17. 97e1ba3 clk: renesas: Synchronize R8A779F0 S4 clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:36 2023 +0200
  18. 91c6541 clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:35 2023 +0200
  19. 0a4b3ae clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:34 2023 +0200
  20. cbf6914 clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:33 2023 +0200
  21. 6f008ee clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:32 2023 +0200
  22. 7d79af5 clk: renesas: Synchronize R8A77970 V3M clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:31 2023 +0200
  23. 561e8be clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:30 2023 +0200
  24. c6698f9 clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:29 2023 +0200
  25. fa9525c clk: renesas: Synchronize R8A77951 H3 clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:28 2023 +0200
  26. bff3e0e clk: renesas: Synchronize R8A7794 E2 clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:27 2023 +0200
  27. b25bd80 clk: renesas: Synchronize R8A7792 V2H clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:26 2023 +0200
  28. dde6069 clk: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:25 2023 +0200
  29. 23cbd51 clk: renesas: Synchronize R8A7790 H2 clock tables with Linux 6.5.3 by Marek Vasut · Sun Sep 17 16:11:24 2023 +0200
  30. 5ab7ef0 clk: renesas: Tear clock controller down last before booting OS by Marek Vasut · Sat Apr 25 14:57:55 2020 +0200
  31. a0dfc71 clk: renesas: add R906G032 driver by Ralph Siemsen · Fri May 12 21:36:51 2023 -0400
  32. 0bdc94a clk: renesas: prepare for non R-Car clock drivers by Ralph Siemsen · Fri May 12 21:36:50 2023 -0400
  33. 68f1ac0 clk: renesas: Add R8A779G0 V4H clock tables by Hai Pham · Tue Feb 28 22:37:02 2023 +0100
  34. 99d4039 clk: renesas: Add R8A779F0 S4 clock tables by Hai Pham · Tue Feb 28 22:34:39 2023 +0100
  35. ba2c7d2 clk: renesas: Update R-Car Gen3 driver Gen4 support by Marek Vasut · Tue Feb 28 22:34:38 2023 +0100
  36. f5e6084 Merge branch 'master' into next by Tom Rini · Mon Mar 27 15:19:57 2023 -0400
  37. ef5c0b1 clk: renesas: Pack reset identifier before look up by Marek Vasut · Sat Mar 18 12:30:53 2023 +0100
  38. ea8505e clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching by Marek Vasut · Tue Feb 28 07:25:11 2023 +0100
  39. 3e55ce3 clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver by Marek Vasut · Tue Feb 28 22:16:02 2023 +0100
  40. 06d8f97 clk: renesas: rcar-gen3: Factor out CPG library by Hai Pham · Thu Jan 26 21:06:07 2023 +0100
  41. 6811b57 clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI by Hai Pham · Thu Jan 26 21:06:06 2023 +0100
  42. 4dae076 clk: renesas: Switch to new SD clock handling by Hai Pham · Sun Jan 29 02:50:22 2023 +0100
  43. 85e691e clk: renesas: Handle E3/D3 RPCSRC clock by Hai Pham · Thu Jan 26 21:06:04 2023 +0100
  44. e83700a clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function by Hai Pham · Thu Jan 26 21:06:03 2023 +0100
  45. b2970fd clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_table by Marek Vasut · Thu Jan 26 21:06:02 2023 +0100
  46. 1bd2521 clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_reg by Marek Vasut · Thu Jan 26 21:02:05 2023 +0100
  47. a80b061 clk: renesas: Use pre-defined offset for RPC clocks by Hai Pham · Thu Jan 26 21:02:04 2023 +0100
  48. f6b3202 clk: renesas: Add and enable CPG reset driver by Marek Vasut · Thu Jan 26 21:02:03 2023 +0100
  49. f144d50 clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support by Hai Pham · Thu Jan 26 21:02:02 2023 +0100
  50. cef5c2f clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960 by Hai Pham · Thu Jan 26 21:02:01 2023 +0100
  51. ffdcb5d clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7 by Marek Vasut · Sun Jan 29 02:37:50 2023 +0100
  52. d4b102a clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:59 2023 +0100
  53. 43b3fdb clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:58 2023 +0100
  54. 7883e0d clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:57 2023 +0100
  55. 569acef clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:56 2023 +0100
  56. d1ff7e0 clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:55 2023 +0100
  57. fdc9314 clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:54 2023 +0100
  58. c3bb162 clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:53 2023 +0100
  59. d5b2e95 clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:52 2023 +0100
  60. fd44059 clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:51 2023 +0100
  61. ade5532 clk: renesas: Synchronize R8A7795 H3 clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:50 2023 +0100
  62. 0985e0e clk: renesas: Add dummy SDnH clock by Hai Pham · Thu Jan 26 21:01:49 2023 +0100
  63. a1b654b treewide: invaild -> invalid by Sean Anderson · Wed Dec 01 14:26:53 2021 -0500
  64. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  65. 0fbb8a7 clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code by Marek Vasut · Tue Apr 27 19:52:53 2021 +0200
  66. 8f56786 clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling by Marek Vasut · Tue Apr 27 19:36:39 2021 +0200
  67. 9480346 clk: renesas: Add register pointers into struct cpg_mssr_info by Hai Pham · Thu Nov 05 22:30:37 2020 +0700
  68. 016a4c2 clk: renesas: Introduce enum clk_reg_layout by Hai Pham · Thu Nov 05 21:32:38 2020 +0700
  69. 5460ee0 clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() by Hai Pham · Fri May 22 10:39:04 2020 +0700
  70. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  71. 215de2b clk: renesas: Add support for RPCD2 clock by Hai Pham · Tue Aug 11 10:25:28 2020 +0700
  72. 1a61896 clk: renesas: Fix Realtime Module Stop Control Register offsets by Hai Pham · Tue May 19 17:42:05 2020 +0700
  73. f2279df clk: renesas: Fix incorrect return RPC clk_get_rate by Hai Pham · Sat Dec 05 09:35:40 2020 +0700
  74. f5fec9d clk: renesas: Reinstate RPC clock on R-Car D3/E3 by Marek Vasut · Sun Apr 25 21:26:22 2021 +0200
  75. 0e8dcb7 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:10:40 2021 +0200
  76. aac4de2 clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:09:10 2021 +0200
  77. 8538d53 clk: renesas: Synchronize RZ/G2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:08:18 2021 +0200
  78. 5af8b6a clk: renesas: Synchronize Gen2 MSTP teardown tables by Marek Vasut · Sat Jun 06 15:26:14 2020 +0200
  79. 22f9fc7 clk: renesas: Only ever access documented bits in clock driver teardown by Marek Vasut · Sat Apr 25 14:57:45 2020 +0200
  80. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  81. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  82. 3434a5f clk: renesas: Import R8A774C0 clock tables from Linux 5.9 by Lad Prabhakar · Fri Oct 16 08:37:14 2020 +0100
  83. eb6474c clk: renesas: Add R8A774E1 clock tables by Biju Das · Wed Oct 14 18:17:36 2020 +0100
  84. 69159a2 clk: renesas: Add R8A774B1 clock tables by Biju Das · Wed Oct 14 18:17:35 2020 +0100
  85. 161bf54 clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clock by Biju Das · Tue Sep 29 11:09:44 2020 +0100
  86. 48de37a Merge tag 'dm-pull-20jul20-take2a' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm by Tom Rini · Mon Jul 27 11:15:37 2020 -0400
  87. 1096ae1 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() by Masahiro Yamada · Fri Jul 17 14:36:46 2020 +0900
  88. 06c4f9b clk: renesas: Add R8A774A1 clock tables by Adam Ford · Tue Jun 30 09:30:08 2020 -0500
  89. 5a9ecb2 Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" by Tom Rini · Fri Jul 24 08:42:06 2020 -0400
  90. a3332a1 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() by Masahiro Yamada · Fri Jul 17 14:36:46 2020 +0900
  91. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  92. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  93. ab11876 clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2 by Marek Vasut · Sat Mar 21 16:45:29 2020 +0100
  94. d52c6cb clk: renesas: Add R8A77980 V3H clock tables by Marek Vasut · Mon Jul 29 19:59:44 2019 +0200
  95. 7841483 clk: renesas: Synchronize Gen3 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:38:10 2019 +0100
  96. 3bee488 clk: renesas: Synchronize Gen2 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:23:25 2019 +0100
  97. 98c2058 clk: renesas: Add R8A77965 clock tables by Marek Vasut · Mon Mar 04 13:36:13 2019 +0100
  98. 0f6aa07 clk: renesas: Add support for setting MMCIF clock divider on Gen2 by Marek Vasut · Mon Mar 18 06:04:02 2019 +0100
  99. 31872db clk: renesas: Fix swapped div and mul in debug output on Gen2 by Marek Vasut · Mon Mar 18 05:38:08 2019 +0100
  100. 272daa7 clk: renesas: Fix SDH clock divider decoding on Gen2 by Marek Vasut · Mon Mar 18 05:11:42 2019 +0100