| commit | 5460ee0367022e871759ce7b097108752fd892bf | [log] [tgz] |
|---|---|---|
| author | Hai Pham <hai.pham.ud@renesas.com> | Fri May 22 10:39:04 2020 +0700 |
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | Fri May 21 15:00:17 2021 +0200 |
| tree | 64111125cf62505dfba48c12a8a8d40e3f751aa1 | |
| parent | 814217e927884a310af413b713c05450b4e2d13a [diff] |
clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>