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filogic
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uboot
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0b5f7e1ceba32c62b1ac72d0a46da5c1f7f18893
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arch
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arm
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mach-socfpga
5d489bf
arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
by Ley Foon Tan
· Mon Apr 20 16:17:27 2020 +0800
0bf7ab1
spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()
by Harald Seiler
· Wed Apr 15 11:33:30 2020 +0200
1d07b3e
arm: socfpga: arria10: Enable cache driver in SPL
by Ley Foon Tan
· Tue Apr 07 15:43:14 2020 +0800
f7fcc90
arm: socfpga: arria10: Add save_boot_params()
by Ley Foon Tan
· Fri Mar 06 16:55:20 2020 +0800
8f1552e
arm: socfpga: Add onchip RAM size macro
by Ley Foon Tan
· Fri Mar 06 16:55:18 2020 +0800
ddef889
ARM: socfpga: Add initial support for the ABB SECU board
by Holger Brunck
· Wed Feb 19 19:55:14 2020 +0100
b7b1838
Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
by Tom Rini
· Tue Feb 11 10:58:41 2020 -0500
9bc1564
dm: core: Create a new header file for 'compat' features
by Simon Glass
· Mon Feb 03 07:36:16 2020 -0700
6bccacf
ddr: altera: Add DDR2 support to Gen5 driver
by Marek Vasut
· Fri Oct 18 00:22:31 2019 +0200
e2a19f4
ARM: socfpga: Drop last use of socfpga_reset_manager
by Marek Vasut
· Thu Jan 09 10:56:24 2020 +0100
f11478f
common: Move hang() to the same header as panic()
by Simon Glass
· Sat Dec 28 10:45:07 2019 -0700
afb0215
common: Move reset_cpu() to the CPU header
by Simon Glass
· Sat Dec 28 10:45:01 2019 -0700
6e762d8
arm: socfpga: stratix10: Enable SMMU access
by Thor Thayer
· Fri Dec 06 13:47:31 2019 -0600
461d298
arm: socfpga: agilex: Enable Agilex SoC build
by Ley Foon Tan
· Wed Nov 27 15:55:32 2019 +0800
600c731
arm: socfpga: agilex: Add SPL for Agilex SoC
by Ley Foon Tan
· Wed Nov 27 15:55:29 2019 +0800
0767f8d
arm: agilex: Add clock handoff offset for Agilex
by Ley Foon Tan
· Wed Nov 27 15:55:25 2019 +0800
b7d95b7
arm: socfpga: agilex: Add clock wrapper functions
by Ley Foon Tan
· Wed Nov 27 15:55:23 2019 +0800
ef5458f
clk: agilex: Add clock driver for Agilex
by Ley Foon Tan
· Wed Nov 27 15:55:22 2019 +0800
a9ebd2a
arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
by Ley Foon Tan
· Wed Nov 27 15:55:21 2019 +0800
9c25671
arm: socfpga: Move Stratix10 and Agilex clock manager common code
by Ley Foon Tan
· Wed Nov 27 15:55:20 2019 +0800
905bae1
arm: socfpga: agilex: Add system manager support
by Ley Foon Tan
· Wed Nov 27 15:55:19 2019 +0800
0b1680e
arm: socfpga: Move Stratix10 and Agilex system manager common code
by Ley Foon Tan
· Wed Nov 27 15:55:18 2019 +0800
ef9805a
arm: socfpga: agilex: Add reset manager support
by Ley Foon Tan
· Wed Nov 27 15:55:17 2019 +0800
89700b4
arm: socfpga: Move Stratix10 and Agilex reset manager common code
by Ley Foon Tan
· Wed Nov 27 15:55:16 2019 +0800
f1c4bd5
arm: socfpga: Move firewall code to firewall file
by Ley Foon Tan
· Wed Nov 27 15:55:15 2019 +0800
65d25a6
arm: socfpga: agilex: Add base address for Intel Agilex SoC
by Ley Foon Tan
· Wed Nov 27 15:55:14 2019 +0800
2669591
arm: socfpga: Convert clock manager from struct to defines
by Ley Foon Tan
· Fri Nov 08 10:38:21 2019 +0800
3d3a860
arm: socfpga: Convert system manager from struct to defines
by Ley Foon Tan
· Fri Nov 08 10:38:20 2019 +0800
fed4c95
arm: socfpga: Convert reset manager from struct to defines
by Ley Foon Tan
· Fri Nov 08 10:38:19 2019 +0800
1d91ba7
common: Move some cache and MMU functions out of common.h
by Simon Glass
· Thu Nov 14 12:57:37 2019 -0700
495a5dc
common: Move get_ticks() function out of common.h
by Simon Glass
· Thu Nov 14 12:57:30 2019 -0700
8b3b890
ARM: socfpga: Unreset NAND in SPL on Gen5
by Marek Vasut
· Wed Nov 20 22:36:24 2019 +0100
47928cc
ARM: socfpga: Add ArriaV ST/SX ID
by Marek Vasut
· Wed Nov 20 22:40:19 2019 +0100
2265259
ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5
by Marek Vasut
· Wed Nov 20 22:34:31 2019 +0100
9f38a97
ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable
by Marek Vasut
· Wed Nov 20 22:34:30 2019 +0100
5216671
socfpga: fix include guard in misc.h (arch vs. global)
by Simon Goldschmidt
· Wed Oct 23 22:32:30 2019 +0200
17d7852
arm: socfpga: gen5: fix ERR_PTR_OFFSET
by Simon Goldschmidt
· Tue Oct 22 21:29:48 2019 +0200
13da18c
ARM: socfpga: vining_fpga: Rename VINING|FPGA
by Marek Vasut
· Thu Jun 27 00:19:31 2019 +0200
a8f0c94
spl: Convert CONFIG_SPL_SIZE_LIMIT to hex
by Simon Glass
· Wed Sep 25 08:56:28 2019 -0600
7611ac6
spl: Allow tiny printf() to be controlled in SPL and TPL
by Simon Glass
· Wed Sep 25 08:56:27 2019 -0600
257ab53
arm: socfpga: gen5: don't zero bss in board_init_f()
by Simon Goldschmidt
· Fri Jul 12 20:03:09 2019 +0200
5e6201b
env: Move env_set() to env.h
by Simon Glass
· Thu Aug 01 09:46:51 2019 -0600
fc82466
sysreset: add support for socfpga sysreset
by Simon Goldschmidt
· Mon Jul 15 21:47:55 2019 +0200
b32e1e8
arm: socfpga: rst: add register definition for cold reset
by Simon Goldschmidt
· Mon Jul 15 21:47:52 2019 +0200
20fd7de
arm: socfpga: provide default SPL_SIZE_LIMIT for gen5
by Simon Goldschmidt
· Thu Jun 13 21:50:28 2019 +0200
a62817a
ARM: socfpga: Clear PL310 early in SPL
by Marek Vasut
· Sat Mar 09 22:25:57 2019 +0100
b6ba490
ARM: socfpga: Pull PL310 clearing into common code
by Marek Vasut
· Thu Mar 21 23:05:38 2019 +0100
43ec7e0
CONFIG_SPL_SYS_[DI]CACHE_OFF: add
by Trevor Woerner
· Fri May 03 09:41:00 2019 -0400
7789aab2
arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board
by Wolfgang Grandegger
· Sun May 12 19:25:18 2019 +0200
c8ff687
arm: sofcpga: s10: remove unused ad-hoc reset code
by Simon Goldschmidt
· Mon May 13 21:16:44 2019 +0200
635e250
arm: socfpga: remove re-added ad-hoc reset code
by Simon Goldschmidt
· Mon May 13 21:16:43 2019 +0200
fe03d80
spl: socfpga: Implement fpga bitstream loading with socfpga loadfs
by Tien Fong Chee
· Tue May 07 17:42:30 2019 +0800
ca99a8a
ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
by Tien Fong Chee
· Tue May 07 17:42:28 2019 +0800
96a9489
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
by Tom Rini
· Tue May 07 09:37:11 2019 -0400
d740445
ARM: socfpga: stratix10: Probe FPGA status before bridge enable
by Ang, Chee Hong
· Fri May 03 01:18:27 2019 -0700
fadf65b
ARM: socfpga: stratix10: Disable FPGA2SOC reset
by Ang, Chee Hong
· Fri May 03 01:19:08 2019 -0700
3fdf436
arm: socfpga: Move Stratix 10 SDRAM driver to DM
by Ley Foon Tan
· Mon May 06 09:56:01 2019 +0800
17b9ba6
ddr: altera: Compile ALTERA SDRAM in SPL only
by Ley Foon Tan
· Mon May 06 09:55:59 2019 +0800
86fbf9d
ARM: socfpga: use the pl310 driver to configure the cache
by Dinh Nguyen
· Tue Apr 23 16:55:05 2019 -0500
b99ca37
ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
by Marek Vasut
· Tue Apr 23 17:24:22 2019 +0200
713a8a2
ARM: socfpga: Add support for selecting bridges in bridge command
by Marek Vasut
· Tue Apr 16 22:28:08 2019 +0200
0c3ddb6
ARM: socfpga: Fully unmap the FPGA bridges from L3 space
by Marek Vasut
· Tue Apr 16 22:13:29 2019 +0200
0b2502e
ARM: socfpga: Disable bridges in SPL unless booting from FPGA
by Marek Vasut
· Tue Apr 16 14:19:34 2019 +0200
79a5b2c
ARM: socfpga: Factor out handoff register configuration
by Marek Vasut
· Tue Apr 16 23:05:24 2019 +0200
374c230
arm: socfpga: mailbox: Fix off-by-one error on command length checking
by Ley Foon Tan
· Wed Apr 24 13:21:47 2019 +0800
4f57b9a
arm: socfpga: gen5: reduce SPL pre-reloc malloc
by Simon Goldschmidt
· Tue Apr 09 21:02:06 2019 +0200
b1c4269
arm: socfpga: imply/default common config options
by Simon Goldschmidt
· Tue Apr 09 21:02:05 2019 +0200
9799a67
ddr: altera: Stratix10: Add ECC memory scrubbing
by Ley Foon Tan
· Fri Mar 22 01:24:05 2019 +0800
3e263c7
arm: socfpga: stratix10: Add cpu_has_been_warmreset()
by Ley Foon Tan
· Fri Mar 22 01:24:04 2019 +0800
a9245d1
ddr: altera: stratix10: Move SDRAM size check to SDRAM driver
by Ley Foon Tan
· Fri Mar 22 01:24:00 2019 +0800
407dcc5
arm: socfpga: implement proper peripheral reset
by Simon Goldschmidt
· Fri Mar 01 20:12:36 2019 +0100
24910c3
arm: socfpga: move gen5 SDR driver to DM
by Simon Goldschmidt
· Tue Apr 16 22:04:39 2019 +0200
339da98
ARM: socfpga: Disable D cache in SPL
by Marek Vasut
· Tue May 08 20:32:01 2018 +0200
4a23a5b
ARM: socfpga: fix data and tag latency values for pl310 cache controller
by Dinh Nguyen
· Sun Mar 03 11:02:10 2019 -0600
2880c11
ARM: socfpga: Clear PL310 early in SPL
by Marek Vasut
· Tue Feb 19 01:07:21 2019 +0100
fd43442
ARM: socfpga: Configure PL310 latencies
by Marek Vasut
· Tue Feb 19 01:11:24 2019 +0100
54d329b
arm: socfpga: gen5: remove hacked ETH RST handling
by Simon Goldschmidt
· Sun Jan 13 19:58:42 2019 +0100
6091dd1
spl: Kconfig: Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPL_FS_EXT4
by Tien Fong Chee
· Wed Jan 23 14:20:05 2019 +0800
6fd0a71
spl: Kconfig: Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT
by Tien Fong Chee
· Wed Jan 23 14:20:03 2019 +0800
da9640e
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
by Ang, Chee Hong
· Wed Dec 19 18:35:16 2018 -0800
ff14f16
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
by Ang, Chee Hong
· Wed Dec 19 18:35:15 2018 -0800
11f4644
arm: socfpga: stratix10: Add macros for mailbox's arguments
by Ang, Chee Hong
· Wed Dec 19 18:35:13 2018 -0800
31b7963
arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10
by Ang, Chee Hong
· Wed Dec 19 18:35:12 2018 -0800
da13a0a
arm: socfpga: fix SPL booting from fpga OnChip RAM
by Simon Goldschmidt
· Wed Oct 10 14:55:23 2018 +0200
ceab269
arm: socfpga: make config structs const
by Simon Goldschmidt
· Wed Nov 14 21:05:12 2018 +0100
0e182f2
arm: socfpga: stratix10: add sgmii in phymode setup
by Ooi, Joyce
· Mon Sep 24 23:31:45 2018 -0700
2e75a74
arm: socfpga: Remove unused function socfpga_emac_manage_reset()
by Ley Foon Tan
· Fri Sep 21 00:22:14 2018 +0800
897dbd7
socfpga: stratix10: fix sdram_calculate_size
by Dalon Westergreen
· Tue Sep 11 10:06:14 2018 -0700
aaa40e7
ARM: socfpga: Convert Arria10 to timer framework
by Marek Vasut
· Sat Aug 18 16:00:31 2018 +0200
8fdb419
ARM: socfpga: Reorder Arria10 SPL
by Marek Vasut
· Sat Aug 18 19:11:52 2018 +0200
ff756cc
arm: socfpga: stratix10: Fix mailbox urgent command with urgent register
by Ley Foon Tan
· Fri Aug 17 16:22:03 2018 +0800
0968d4e
arm: socfpga: stratix10: Enable EMAC to FPGA bridge based on handoff
by Ley Foon Tan
· Fri Aug 17 16:22:02 2018 +0800
7ebd938
arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
by Ley Foon Tan
· Thu Aug 16 02:20:17 2018 +0800
71b1637
ARM: socfpga: clk: Convert to clock framework
by Marek Vasut
· Mon Aug 06 21:42:05 2018 +0200
fd6bcb5
ARM: socfpga: clk: Drop unused variables on Arria10
by Marek Vasut
· Tue Jul 31 17:33:42 2018 +0200
d430d9a
ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
by Marek Vasut
· Mon Aug 06 21:47:50 2018 +0200
e1dcd62
ARM: socfpga: clk: Obtain handoff base clock via DM
by Marek Vasut
· Mon Jul 30 15:56:19 2018 +0200
04c8f4f
ARM: socfpga: Remove adhoc ethernet reset and configuration
by Marek Vasut
· Mon Aug 13 20:06:46 2018 +0200
40ca091
ARM: socfpga: Zap unused reset code
by Marek Vasut
· Mon Aug 13 18:57:08 2018 +0200
8b73c87
ARM: socfpga: Zap all the UART handling complexity
by Marek Vasut
· Sun Apr 15 16:29:12 2018 +0200
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