| commit | 4a23a5be5f23ed7b98136aff8ec388eded86e73d | [log] [tgz] |
|---|---|---|
| author | Dinh Nguyen <dinguyen@kernel.org> | Sun Mar 03 11:02:10 2019 -0600 |
| committer | Marek Vasut <marex@denx.de> | Sat Mar 09 17:59:13 2019 +0100 |
| tree | a76dcbaa47389d90a8e704160517da3f8cb69653 | |
| parent | bbdbf033461c4306949a088bf39f77af771ac9e6 [diff] |
ARM: socfpga: fix data and tag latency values for pl310 cache controller The values for the data and tag latency settings on the PL310 caches controller is an (n-1). For example, the "arm,tag-latency" is specified as <1 1 1>, so the values that should be written to register should be 0x000. And for the "arm,data-latency" specified as <2 1 1>, the register value should be 0x010. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>