tree a76dcbaa47389d90a8e704160517da3f8cb69653
parent bbdbf033461c4306949a088bf39f77af771ac9e6
author Dinh Nguyen <dinguyen@kernel.org> 1551632530 -0600
committer Marek Vasut <marex@denx.de> 1552150753 +0100

ARM: socfpga: fix data and tag latency values for pl310 cache controller

The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>