| commit | fadf65b8ac7853239b1ee7faf040fcc3555b72a5 | [log] [tgz] |
|---|---|---|
| author | Ang, Chee Hong <chee.hong.ang@intel.com> | Fri May 03 01:19:08 2019 -0700 |
| committer | Marek Vasut <marex@denx.de> | Mon May 06 12:44:45 2019 +0200 |
| tree | 7bd7bbed5c8f5dbbee3934e8484a22f7c89b4248 | |
| parent | 3fdf4361009798c473aaf234985d07732286aff9 [diff] |
ARM: socfpga: stratix10: Disable FPGA2SOC reset Software must never reset FPGA2SOC bridge. This bridge must only be reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software can cause the SoC to lock-up if there are traffics being drived into FPGA2SOC bridge. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>