Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 084d88f3889a6dd8de0506a9ad66db34325486f7 / drivers / ddr / altera
  1. 1bbf41d global: Drop common.h inclusion by Tom Rini · Thu Dec 14 13:16:47 2023 -0500
  2. b52189e drivers: use devfdt_get_addr_index_ptr when cast to pointer by Johan Jonker · Mon Mar 13 01:32:31 2023 +0100
  3. 80877fa cyclic: Use schedule() instead of WATCHDOG_RESET() by Stefan Roese · Fri Sep 02 14:10:46 2022 +0200
  4. eeea5ec ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched by Dinesh Maniyam · Wed Jun 01 18:49:02 2022 +0800
  5. 851c724 ddr: altera: Stratix10: Use phys_size_t for memory size by Tien Fong Chee · Wed Apr 27 12:52:42 2022 +0800
  6. 7bcd663 ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS by Tien Fong Chee · Wed Apr 27 12:27:21 2022 +0800
  7. 277f1f4 intel: n5x: ddr: update license by Tien Fong Chee · Fri Jun 10 19:18:00 2022 +0800
  8. a321d04 drivers/ddr/altera/sequencer.c: Fix spelling of "resetting". by Vagrant Cascadian · Tue Dec 21 13:07:01 2021 -0800
  9. 3fd6633 WS cleanup: remove trailing empty lines by Wolfgang Denk · Mon Sep 27 17:42:36 2021 +0200
  10. ed6c1ab ddr: altera: use KBUILD_BASENAME instead of __FILE__ by Marek Vasut · Tue Sep 14 05:20:19 2021 +0200
  11. f8e2eab ddr: altera: Add SDRAM driver for Intel N5X device by Tien Fong Chee · Tue Aug 10 11:26:37 2021 +0800
  12. a513238 ddr: socfpga: Enable memory test on memory size less than 1GB by Tien Fong Chee · Tue Aug 10 11:26:36 2021 +0800
  13. 8a71416 arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 by Siew Chin Lim · Mon Mar 01 20:04:10 2021 +0800
  14. d3f1735 dm: ddr: socfpga: don't assign values that are not used by Heinrich Schuchardt · Sat Feb 20 10:40:23 2021 +0100
  15. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  16. 9558862 dm: Use access methods for dev/uclass private data by Simon Glass · Tue Dec 22 19:30:28 2020 -0700
  17. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  18. aad29ae dm: treewide: Rename ofdata_to_platdata() to of_to_plat() by Simon Glass · Thu Dec 03 16:55:21 2020 -0700
  19. 71fa5b4 dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · Thu Dec 03 16:55:18 2020 -0700
  20. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  21. f7ed78b treewide: convert bd_t to struct bd_info by coccinelle by Masahiro Yamada · Fri Jun 26 15:13:33 2020 +0900
  22. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  23. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  24. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  25. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600
  26. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  27. b7b1838 Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm by Tom Rini · Tue Feb 11 10:58:41 2020 -0500
  28. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  29. 6bccacf ddr: altera: Add DDR2 support to Gen5 driver by Marek Vasut · Fri Oct 18 00:22:31 2019 +0200
  30. f11478f common: Move hang() to the same header as panic() by Simon Glass · Sat Dec 28 10:45:07 2019 -0700
  31. 8e16b1e common: Move RAM-sizing functions to init.h by Simon Glass · Sat Dec 28 10:45:05 2019 -0700
  32. 7ead421 ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access by Thor Thayer · Fri Dec 06 13:47:32 2019 -0600
  33. 6e762d8 arm: socfpga: stratix10: Enable SMMU access by Thor Thayer · Fri Dec 06 13:47:31 2019 -0600
  34. 4ddb909 ddr: altera: agilex: Add SDRAM driver for Agilex by Ley Foon Tan · Wed Nov 27 15:55:27 2019 +0800
  35. 25572cf ddr: altera: Restructure Stratix 10 SDRAM driver by Ley Foon Tan · Wed Nov 27 15:55:26 2019 +0800
  36. 0b1680e arm: socfpga: Move Stratix10 and Agilex system manager common code by Ley Foon Tan · Wed Nov 27 15:55:18 2019 +0800
  37. f1c4bd5 arm: socfpga: Move firewall code to firewall file by Ley Foon Tan · Wed Nov 27 15:55:15 2019 +0800
  38. 3d3a860 arm: socfpga: Convert system manager from struct to defines by Ley Foon Tan · Fri Nov 08 10:38:20 2019 +0800
  39. 1d91ba7 common: Move some cache and MMU functions out of common.h by Simon Glass · Thu Nov 14 12:57:37 2019 -0700
  40. e874433 ddr: socfpga: gen5: constify altera_gen5_sdram_ops by Simon Goldschmidt · Wed Oct 23 22:19:37 2019 +0200
  41. 2be4a3e dm: ddr: socfpga: fix gen5 ddr driver to not use bss by Simon Goldschmidt · Thu Jul 11 21:18:12 2019 +0200
  42. 3fdf436 arm: socfpga: Move Stratix 10 SDRAM driver to DM by Ley Foon Tan · Mon May 06 09:56:01 2019 +0800
  43. 17b9ba6 ddr: altera: Compile ALTERA SDRAM in SPL only by Ley Foon Tan · Mon May 06 09:55:59 2019 +0800
  44. 9799a67 ddr: altera: Stratix10: Add ECC memory scrubbing by Ley Foon Tan · Fri Mar 22 01:24:05 2019 +0800
  45. 4bbed7b ddr: altera: Stratix10: Add multi-banks DRAM size check by Ley Foon Tan · Fri Mar 22 01:24:01 2019 +0800
  46. a9245d1 ddr: altera: stratix10: Move SDRAM size check to SDRAM driver by Ley Foon Tan · Fri Mar 22 01:24:00 2019 +0800
  47. 24910c3 arm: socfpga: move gen5 SDR driver to DM by Simon Goldschmidt · Tue Apr 16 22:04:39 2019 +0200
  48. 0f36715 ddr: socfpga: Clean up ddr_setup() by Marek Vasut · Sat Mar 09 21:58:09 2019 +0100
  49. 569fe4a ddr: socfpga: Clean up EMIF reset by Marek Vasut · Sat Mar 09 21:57:58 2019 +0100
  50. a9c0470 ddr: socfpga: Fix EMIF clear timeout by Marek Vasut · Fri Mar 08 19:11:55 2019 +0100
  51. 6b44050 ddr: socfpga: Fix newline in debug print on A10 by Marek Vasut · Wed Mar 06 17:18:22 2019 +0100
  52. e2bc6b1 ddr: socfpga: Fix IO in Arria10 DDR driver by Marek Vasut · Tue Mar 05 18:37:02 2019 +0100
  53. 897dbd7 socfpga: stratix10: fix sdram_calculate_size by Dalon Westergreen · Tue Sep 11 10:06:14 2018 -0700
  54. 3693897 ddr: altera: Add ECC DRAM scrubbing support for Arria10 by Marek Vasut · Mon May 28 17:22:47 2018 +0200
  55. 023b31b ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 by Marek Vasut · Tue May 29 18:04:15 2018 +0200
  56. f9c7f79 ddr: altera: stratix10: Add DDR support for Stratix10 SoC by Ley Foon Tan · Thu May 24 00:17:30 2018 +0800
  57. 4606fc7 SPDX: Fixup SPDX tags in a few new files by Tom Rini · Sun May 20 09:47:45 2018 -0400
  58. 4d447a5 configs: Add DDR Kconfig support for Arria 10 by Tien Fong Chee · Tue Dec 05 15:58:03 2017 +0800
  59. 402735b ARM: socfpga: Add DDR driver for Arria 10 by Tien Fong Chee · Tue Dec 05 15:58:02 2017 +0800
  60. 38fad17 ARM: socfpga: Rename the gen5 sdram driver to more specific name by Tien Fong Chee · Tue Dec 05 15:58:00 2017 +0800
  61. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  62. bdfb5c4 Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR by Tom Rini · Wed Apr 18 13:50:47 2018 -0400
  63. a4af914 ddr: altera: silence PHY calibration unless in debug mode by Goldschmidt Simon · Thu Jan 25 06:04:44 2018 +0000
  64. 016539e arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig by Ley Foon Tan · Wed Apr 05 17:32:51 2017 +0800
  65. 3ea5951 ddr: altera: Configuring SDRAM extra cycles timing parameters by Chin Liang See · Wed Sep 21 10:25:56 2016 +0800
  66. 66acabc ddr: altera: Repair DQ window centering code by Marek Vasut · Tue Apr 05 23:17:35 2016 +0200
  67. a4b9fa1 ddr: altera: Staticize global variables by Marek Vasut · Tue Apr 05 11:18:38 2016 +0200
  68. 4df2d7b ddr: altera: Make DLEVEL behavior inclusive by Marek Vasut · Mon Apr 04 21:21:05 2016 +0200
  69. f4d3862 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() by Marek Vasut · Mon Apr 04 21:16:18 2016 +0200
  70. 2bf2ee5 ddr: altera: Remove unnecessary ODT mode config by Marek Vasut · Mon Apr 04 19:10:12 2016 +0200
  71. acee8fd ddr: altera: Remove unnecessary update of the SCC by Marek Vasut · Mon Apr 04 18:41:53 2016 +0200
  72. 12361a2 ddr: altera: Fix DRAM end value in protection rule by Marek Vasut · Mon Apr 04 17:52:21 2016 +0200
  73. 45ce296 ddr: altera: Fix scc_mgr_set() argument order by Marek Vasut · Mon Apr 04 17:28:16 2016 +0200
  74. 6946989 ddr: altera: Tweak DQS tracking enable handling by Marek Vasut · Tue Apr 05 23:41:56 2016 +0200
  75. 2654bc9 ddr: altera: Replace ad-hoc constant with macro by Marek Vasut · Mon Apr 04 16:07:11 2016 +0200
  76. 42aa46d ddr: altera: Init the rule ID in debug code by Marek Vasut · Tue Dec 29 09:38:52 2015 +0100
  77. eb447cb ddr: altera: Repair uninited variable by Marek Vasut · Mon Aug 10 23:01:43 2015 +0200
  78. af67cf3 ddr: altera: Replace float multiplication with integer one by Marek Vasut · Mon Aug 10 22:50:11 2015 +0200
  79. c85b9b3 ddr: altera: sequencer: Clean checkpatch issues by Marek Vasut · Sun Aug 02 19:47:01 2015 +0200
  80. 8af9ca0 ddr: altera: sequencer: Clean data types by Marek Vasut · Sun Aug 02 19:42:26 2015 +0200
  81. 5867376 ddr: altera: sequencer: Pluck out misc macros from code by Marek Vasut · Sun Aug 02 19:26:55 2015 +0200
  82. 324d3f7 ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL by Marek Vasut · Sun Aug 02 19:24:12 2015 +0200
  83. 32d813e ddr: altera: sequencer: Zap VFIFO_SIZE by Marek Vasut · Sun Aug 02 19:21:56 2015 +0200
  84. f00a6ea ddr: altera: sequencer: Wrap misc remaining macros by Marek Vasut · Sun Aug 02 19:18:47 2015 +0200
  85. 7e8f8a7 ddr: altera: sequencer: Pluck out IO_* macros from code by Marek Vasut · Sun Aug 02 19:10:58 2015 +0200
  86. 3bf9204 ddr: altera: sequencer: Wrap IO_* macros by Marek Vasut · Sun Aug 02 19:00:23 2015 +0200
  87. 2dfc76b ddr: altera: sequencer: Pluck out RW_MGR_* macros from code by Marek Vasut · Sun Aug 02 18:44:06 2015 +0200
  88. 39b620e ddr: altera: sequencer: Wrap RW_MGR_* macros by Marek Vasut · Sun Aug 02 18:12:08 2015 +0200
  89. 3384e74 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init by Marek Vasut · Sun Aug 02 17:15:19 2015 +0200
  90. 42ed1f2 ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS by Marek Vasut · Sun Aug 02 18:40:27 2015 +0200
  91. eb98b38 ddr: altera: sequencer: Zap unused params and macros by Marek Vasut · Sun Aug 02 18:27:21 2015 +0200
  92. 662a8a6 ddr: altera: sequencer: Move qts-generated files to board dir by Marek Vasut · Sun Aug 02 16:55:45 2015 +0200
  93. 6772cd9 ddr: altera: sdram: Make sdram_start and sdram_end into u32 by Marek Vasut · Sat Aug 01 23:12:11 2015 +0200
  94. 9114407 ddr: altera: sdram: Minor cleanup in sdram_get_rule() by Marek Vasut · Sat Aug 01 23:21:23 2015 +0200
  95. 7fce5bc ddr: altera: sdram: Minor cleanup in sdram_set_rule() by Marek Vasut · Sat Aug 01 22:40:48 2015 +0200
  96. b0d848c ddr: altera: sdram: Add missing kerneldoc by Marek Vasut · Sat Aug 01 22:28:30 2015 +0200
  97. 116d88f ddr: altera: sdram: Clean up sdram_write_verify() by Marek Vasut · Sat Aug 01 22:26:11 2015 +0200
  98. 1796a09 ddr: altera: sdram: Clean up sdram_calculate_size() part 2 by Marek Vasut · Sat Aug 01 21:47:16 2015 +0200
  99. 6d6fbba ddr: altera: sdram: Clean up sdram_calculate_size() part 1 by Marek Vasut · Sat Aug 01 21:44:00 2015 +0200
  100. 32ada57 ddr: altera: sdram: Introduce socfpga_sdram_get_config() by Marek Vasut · Sat Aug 01 21:35:18 2015 +0200