| commit | 7bcd66344d0489bdcb1010c1f71f830f921d85b9 | [log] [tgz] |
|---|---|---|
| author | Tien Fong Chee <tien.fong.chee@intel.com> | Wed Apr 27 12:27:21 2022 +0800 |
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | Thu Jun 16 16:10:44 2022 +0800 |
| tree | fb14185e5c4c674453af6f93ec7d18a12ef5b878 | |
| parent | f5190c955b9fbd54df1506e20d7b125927ef84cd [diff] |
ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>