Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / fec07318b92b859612c6f4d9004b4553acd5d09e / . / configs / firefly-rk3288_defconfig
blob: c0dbd8470a783d19330566dbcff6d852bada0c07 [file] [log] [blame]
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
3CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]4CONFIG_SYS_ARCH_TIMER=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]5CONFIG_ARCH_ROCKCHIP=y
Kever Yang89d08842019-10-16 16:50:03 +0800[diff] [blame]6CONFIG_SYS_TEXT_BASE=0x01000000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]10CONFIG_ROCKCHIP_RK3288=y
11CONFIG_TARGET_FIREFLY_RK3288=y
Tom Rinifdc7e362019-11-11 20:04:24 -0500[diff] [blame]12CONFIG_SPL_STACK_R_ADDR=0x80000
Ovidiu Panaitb7232622020-09-25 21:12:56 +0300[diff] [blame]13CONFIG_SPL_SIZE_LIMIT=0x40000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]14CONFIG_DEBUG_UART_BASE=0xff690000
15CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]16CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]17CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]18# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]19CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]20CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]21CONFIG_SILENT_CONSOLE=y
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]22CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]23CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]24CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]25CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]26CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]27CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]28CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]29CONFIG_CMD_SPI=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]30CONFIG_CMD_USB=y
Urja Rannikko17dd9d32019-05-13 13:51:04 +0000[diff] [blame]31CONFIG_CMD_USB_MASS_STORAGE=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]32# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]33CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]34CONFIG_CMD_TIME=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]35CONFIG_CMD_PMIC=y
36CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]37# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]38# CONFIG_SPL_EFI_PARTITION is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]39CONFIG_SPL_OF_CONTROL=y
Simon Glass813d4602016-05-14 14:03:00 -0600[diff] [blame]40CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]41CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]42CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Romain Perier04cad6e2017-01-17 10:32:25 +0100[diff] [blame]43CONFIG_NET_RANDOM_ETHADDR=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]44CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]45CONFIG_SPL_REGMAP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]46CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]47CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]48# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]49CONFIG_CLK=y
50CONFIG_SPL_CLK=y
Alex Kiernane80d2942018-05-29 15:30:55 +0000[diff] [blame]51CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]52CONFIG_ROCKCHIP_GPIO=y
53CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]54CONFIG_LED=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]55CONFIG_LED_GPIO=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]56CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]57CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]58CONFIG_MTD=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]59CONFIG_SF_DEFAULT_SPEED=20000000
Sjoerd Simons613848c2017-01-11 11:46:12 +0100[diff] [blame]60CONFIG_DM_ETH=y
Sjoerd Simons613848c2017-01-11 11:46:12 +0100[diff] [blame]61CONFIG_ETH_DESIGNWARE=y
62CONFIG_GMAC_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]63CONFIG_PINCTRL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]64CONFIG_SPL_PINCTRL=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]65CONFIG_DM_PMIC=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]66# CONFIG_SPL_PMIC_CHILDREN is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]67CONFIG_PMIC_ACT8846=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]68CONFIG_REGULATOR_ACT8846=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]69CONFIG_DM_REGULATOR_FIXED=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]70CONFIG_PWM_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]71CONFIG_RAM=y
72CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]73CONFIG_DEBUG_UART_SHIFT=2
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]74CONFIG_SYSRESET=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]75CONFIG_USB=y
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]76CONFIG_USB_DWC2=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]77CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini4100de42017-07-31 18:59:01 -0400[diff] [blame]78CONFIG_USB_KEYBOARD=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]79CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]80CONFIG_USB_ETHER_ASIX=y
81CONFIG_USB_ETHER_SMSC95XX=y
Tom Rini2c082ab2021-07-26 21:10:37 -0400[diff] [blame]82CONFIG_USB_GADGET=y
83CONFIG_USB_GADGET_DWC2_OTG=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]84CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]85# CONFIG_VIDEO_BPP8 is not set
Anatolij Gustschin4601eb42016-01-25 17:17:22 +0100[diff] [blame]86CONFIG_DISPLAY=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]87CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]88CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glassd76f29a2016-10-17 20:12:57 -0600[diff] [blame]89CONFIG_CONSOLE_SCROLL_LINES=10
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]90CONFIG_CMD_DHRYSTONE=y
91CONFIG_ERRNO_STR=y