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git01.mediatek.com / filogic / uboot / 0f2dcb9022a0db684ea6a49409697bc97a55bd8a / . / configs / firefly-rk3288_defconfig
blob: 1c7155f771f57a6bad95951ff0feed6af0cfb88b [file] [log] [blame]
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
5CONFIG_TARGET_FIREFLY_RK3288=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]6CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]7CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
8CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]9CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]10CONFIG_HUSH_PARSER=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]11# CONFIG_CMD_IMLS is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame^]12CONFIG_CMD_SF=y
13CONFIG_CMD_SPI=y
14CONFIG_CMD_I2C=y
15CONFIG_CMD_GPIO=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]16# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame^]17CONFIG_CMD_DHCP=y
18CONFIG_CMD_PING=y
19CONFIG_CMD_TIME=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]20CONFIG_CMD_PMIC=y
21CONFIG_CMD_REGULATOR=y
22CONFIG_SPL_OF_CONTROL=y
Simon Glass8d32f4b2016-01-21 19:43:38 -0700[diff] [blame]23CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]24CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]25CONFIG_SPL_REGMAP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]26CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]27CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]28# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]29CONFIG_CLK=y
30CONFIG_SPL_CLK=y
31CONFIG_ROCKCHIP_GPIO=y
32CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]33CONFIG_LED=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]34CONFIG_LED_GPIO=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]35CONFIG_RESET=y
36CONFIG_DM_MMC=y
37CONFIG_ROCKCHIP_DWMMC=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]38CONFIG_PINCTRL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]39CONFIG_SPL_PINCTRL=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]40# CONFIG_SPL_PINCTRL_FULL is not set
41CONFIG_ROCKCHIP_PINCTRL=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]42CONFIG_DM_PMIC=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]43# CONFIG_SPL_PMIC_CHILDREN is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]44CONFIG_PMIC_ACT8846=y
45CONFIG_DM_REGULATOR=y
46CONFIG_REGULATOR_ACT8846=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]47CONFIG_DM_REGULATOR_FIXED=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]48CONFIG_DM_PWM=y
49CONFIG_PWM_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]50CONFIG_RAM=y
51CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]52CONFIG_DEBUG_UART=y
53CONFIG_DEBUG_UART_BASE=0xff690000
54CONFIG_DEBUG_UART_CLOCK=24000000
55CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]56CONFIG_SYS_NS16550=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]57CONFIG_DM_VIDEO=y
Anatolij Gustschin4601eb42016-01-25 17:17:22 +0100[diff] [blame]58CONFIG_DISPLAY=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]59CONFIG_VIDEO_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]60CONFIG_USE_PRIVATE_LIBGCC=y
Sjoerd Simonsf26619a2015-12-04 23:27:41 +0100[diff] [blame]61CONFIG_USE_TINY_PRINTF=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]62CONFIG_CMD_DHRYSTONE=y
63CONFIG_ERRNO_STR=y