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git01.mediatek.com / filogic / uboot / f7e077258c28b7d567e25e2d9d21131dbf989543 / . / configs / firefly-rk3288_defconfig
blob: d3efe6e7f9bcf06b8e2092a7a11446d533b55f30 [file] [log] [blame]
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
5CONFIG_TARGET_FIREFLY_RK3288=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]6CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]7CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]8CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]9# CONFIG_DISPLAY_CPUINFO is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]10CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]11CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]12# CONFIG_CMD_IMLS is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]13CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]14CONFIG_CMD_SF=y
15CONFIG_CMD_SPI=y
16CONFIG_CMD_I2C=y
17CONFIG_CMD_GPIO=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]18# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]19CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]20CONFIG_CMD_TIME=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]21CONFIG_CMD_PMIC=y
22CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame^]23# CONFIG_SPL_DOS_PARTITION is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]24CONFIG_SPL_OF_CONTROL=y
Simon Glass813d4602016-05-14 14:03:00 -0600[diff] [blame]25CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]26CONFIG_SPL_OF_PLATDATA=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]27CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]28CONFIG_SPL_REGMAP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]29CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]30CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]31# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]32CONFIG_CLK=y
33CONFIG_SPL_CLK=y
34CONFIG_ROCKCHIP_GPIO=y
35CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]36CONFIG_LED=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]37CONFIG_LED_GPIO=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]38CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]39CONFIG_MMC_DW_ROCKCHIP=y
Sjoerd Simons613848c2017-01-11 11:46:12 +0100[diff] [blame]40CONFIG_DM_ETH=y
Sjoerd Simons613848c2017-01-11 11:46:12 +0100[diff] [blame]41CONFIG_ETH_DESIGNWARE=y
42CONFIG_GMAC_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]43CONFIG_PINCTRL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]44CONFIG_SPL_PINCTRL=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]45# CONFIG_SPL_PINCTRL_FULL is not set
Heiko Stübner66bd8d32016-07-16 00:17:13 +0200[diff] [blame]46CONFIG_ROCKCHIP_RK3288_PINCTRL=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]47CONFIG_DM_PMIC=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]48# CONFIG_SPL_PMIC_CHILDREN is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]49CONFIG_PMIC_ACT8846=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]50CONFIG_REGULATOR_ACT8846=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]51CONFIG_DM_REGULATOR_FIXED=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]52CONFIG_PWM_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]53CONFIG_RAM=y
54CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]55CONFIG_DEBUG_UART=y
56CONFIG_DEBUG_UART_BASE=0xff690000
57CONFIG_DEBUG_UART_CLOCK=24000000
58CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]59CONFIG_SYS_NS16550=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]60CONFIG_ROCKCHIP_SERIAL=y
61CONFIG_SYSRESET=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]62CONFIG_DM_VIDEO=y
Anatolij Gustschin4601eb42016-01-25 17:17:22 +0100[diff] [blame]63CONFIG_DISPLAY=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]64CONFIG_VIDEO_ROCKCHIP=y
Simon Glassd76f29a2016-10-17 20:12:57 -0600[diff] [blame]65CONFIG_CONSOLE_SCROLL_LINES=10
Sjoerd Simonsf26619a2015-12-04 23:27:41 +0100[diff] [blame]66CONFIG_USE_TINY_PRINTF=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]67CONFIG_CMD_DHRYSTONE=y
68CONFIG_ERRNO_STR=y
Simon Glass1475e492016-07-04 11:58:36 -0600[diff] [blame]69# CONFIG_SPL_OF_LIBFDT is not set