blob: 507b19b759757c72745bcfae4f08142bdd6b5350 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek19dfc472012-09-13 20:23:34 +00002/*
3 * (C) Copyright 2011 Michal Simek
4 *
5 * Michal SIMEK <monstr@monstr.eu>
6 *
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
Michal Simek19dfc472012-09-13 20:23:34 +00009 */
10
Siva Durga Prasad Paladugubaa20352016-11-15 16:15:42 +053011#include <clk.h>
Michal Simek19dfc472012-09-13 20:23:34 +000012#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -070013#include <cpu_func.h>
Michal Simek250e05e2015-11-30 14:14:56 +010014#include <dm.h>
Michal Simekc8142d42021-12-15 11:00:01 +010015#include <generic-phy.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
Michal Simek19dfc472012-09-13 20:23:34 +000017#include <net.h>
Michal Simekb055f672014-04-25 14:17:38 +020018#include <netdev.h>
Michal Simek19dfc472012-09-13 20:23:34 +000019#include <config.h>
Michal Simekd9cfa972015-09-24 20:13:45 +020020#include <console.h>
Michal Simek19dfc472012-09-13 20:23:34 +000021#include <malloc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060022#include <asm/cache.h>
Michal Simek19dfc472012-09-13 20:23:34 +000023#include <asm/io.h>
24#include <phy.h>
Michal Simekc86e7fc2021-12-06 16:25:20 +010025#include <reset.h>
Michal Simek19dfc472012-09-13 20:23:34 +000026#include <miiphy.h>
Mateusz Kulikowski93597d72016-01-23 11:54:33 +010027#include <wait_bit.h>
Michal Simek19dfc472012-09-13 20:23:34 +000028#include <watchdog.h>
Siva Durga Prasad Paladugu2b0690e2014-12-06 12:57:53 +053029#include <asm/system.h>
David Andrey73875dc2013-04-05 17:24:24 +020030#include <asm/arch/hardware.h>
Michal Simekd9f2c112012-10-15 14:01:23 +020031#include <asm/arch/sys_proto.h>
Simon Glass9bc15642020-02-03 07:36:16 -070032#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060033#include <linux/bitops.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070034#include <linux/err.h>
Masahiro Yamada64e4f7f2016-09-21 11:28:57 +090035#include <linux/errno.h>
Michal Simekb0017982022-03-30 11:07:53 +020036#include <eth_phy.h>
T Karthik Reddy4a0e6b52022-03-30 11:07:58 +020037#include <zynqmp_firmware.h>
Michal Simek19dfc472012-09-13 20:23:34 +000038
Michal Simek19dfc472012-09-13 20:23:34 +000039/* Bit/mask specification */
40#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
41#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
42#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
43#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
44#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
45
46#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
47#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
48#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
49
50#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
51#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
52#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
53
54/* Wrap bit, last descriptor */
55#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
56#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
Michal Simek1dc446e2015-08-17 09:58:54 +020057#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
Michal Simek19dfc472012-09-13 20:23:34 +000058
Michal Simek19dfc472012-09-13 20:23:34 +000059#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
60#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
61#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
62#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
63
Siva Durga Prasad Paladugu7e7fcc32016-05-16 15:31:37 +053064#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
65#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
66#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
67#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
Siva Durga Prasad Paladuguf6c2d202016-05-16 15:31:38 +053068#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
Siva Durga Prasad Paladugu7e7fcc32016-05-16 15:31:37 +053069#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
Michal Simek780c5352015-09-08 17:20:01 +020070#ifdef CONFIG_ARM64
Siva Durga Prasad Paladugu7e7fcc32016-05-16 15:31:37 +053071#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
Michal Simek780c5352015-09-08 17:20:01 +020072#else
Siva Durga Prasad Paladugu7e7fcc32016-05-16 15:31:37 +053073#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
Michal Simek780c5352015-09-08 17:20:01 +020074#endif
Michal Simek19dfc472012-09-13 20:23:34 +000075
Siva Durga Prasad Paladugu71245a42014-07-08 15:31:03 +053076#ifdef CONFIG_ARM64
77# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
78#else
79# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
80#endif
81
82#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
83 ZYNQ_GEM_NWCFG_FDEN | \
Michal Simek19dfc472012-09-13 20:23:34 +000084 ZYNQ_GEM_NWCFG_FSREM | \
85 ZYNQ_GEM_NWCFG_MDCCLKDIV)
86
87#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
88
89#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
90/* Use full configured addressable space (8 Kb) */
91#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
92/* Use full configured addressable space (4 Kb) */
93#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
94/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
95#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
96
Vipul Kumarcbc2ed62018-11-26 16:27:38 +053097#if defined(CONFIG_PHYS_64BIT)
98# define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
99#else
100# define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
101#endif
102
Michal Simek19dfc472012-09-13 20:23:34 +0000103#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
104 ZYNQ_GEM_DMACR_RXSIZE | \
105 ZYNQ_GEM_DMACR_TXSIZE | \
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530106 ZYNQ_GEM_DMACR_RXBUF | \
107 ZYNQ_GEM_DMA_BUS_WIDTH)
Michal Simek19dfc472012-09-13 20:23:34 +0000108
Michal Simek975ae352015-08-17 09:57:46 +0200109#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
110
Siva Durga Prasad Paladugu45467002016-03-25 12:53:44 +0530111#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
112
Siva Durga Prasad Paladugub7b36372018-11-26 16:27:39 +0530113#define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
114
Ashok Reddy Soma06250462021-11-18 13:05:24 +0100115#define MDIO_IDLE_TIMEOUT_MS 100
116
Michal Simekab72cb42013-04-22 14:41:09 +0200117/* Use MII register 1 (MII status register) to detect PHY */
118#define PHY_DETECT_REG 1
119
120/* Mask used to verify certain PHY features (or register contents)
121 * in the register above:
122 * 0x1000: 10Mbps full duplex support
123 * 0x0800: 10Mbps half duplex support
124 * 0x0008: Auto-negotiation support
125 */
126#define PHY_DETECT_MASK 0x1808
127
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530128/* TX BD status masks */
129#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
130#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
131#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
132
Soren Brinkmann4dded982013-11-21 13:39:01 -0800133/* Clock frequencies for different speeds */
134#define ZYNQ_GEM_FREQUENCY_10 2500000UL
135#define ZYNQ_GEM_FREQUENCY_100 25000000UL
136#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
137
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700138#define RXCLK_EN BIT(0)
139
Michal Simek19dfc472012-09-13 20:23:34 +0000140/* Device registers */
141struct zynq_gem_regs {
Michal Simek74a86e82015-10-05 11:49:43 +0200142 u32 nwctrl; /* 0x0 - Network Control reg */
143 u32 nwcfg; /* 0x4 - Network Config reg */
144 u32 nwsr; /* 0x8 - Network Status reg */
Michal Simek19dfc472012-09-13 20:23:34 +0000145 u32 reserved1;
Michal Simek74a86e82015-10-05 11:49:43 +0200146 u32 dmacr; /* 0x10 - DMA Control reg */
147 u32 txsr; /* 0x14 - TX Status reg */
148 u32 rxqbase; /* 0x18 - RX Q Base address reg */
149 u32 txqbase; /* 0x1c - TX Q Base address reg */
150 u32 rxsr; /* 0x20 - RX Status reg */
Michal Simek19dfc472012-09-13 20:23:34 +0000151 u32 reserved2[2];
Michal Simek74a86e82015-10-05 11:49:43 +0200152 u32 idr; /* 0x2c - Interrupt Disable reg */
Michal Simek19dfc472012-09-13 20:23:34 +0000153 u32 reserved3;
Michal Simek74a86e82015-10-05 11:49:43 +0200154 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
Michal Simek19dfc472012-09-13 20:23:34 +0000155 u32 reserved4[18];
Michal Simek74a86e82015-10-05 11:49:43 +0200156 u32 hashl; /* 0x80 - Hash Low address reg */
157 u32 hashh; /* 0x84 - Hash High address reg */
Michal Simek19dfc472012-09-13 20:23:34 +0000158#define LADDR_LOW 0
159#define LADDR_HIGH 1
Michal Simek74a86e82015-10-05 11:49:43 +0200160 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
161 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
Michal Simek19dfc472012-09-13 20:23:34 +0000162 u32 reserved6[18];
Michal Simekff5dbef2015-10-05 12:49:48 +0200163#define STAT_SIZE 44
164 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
Siva Durga Prasad Paladugu45467002016-03-25 12:53:44 +0530165 u32 reserved9[20];
166 u32 pcscntrl;
Siva Durga Prasad Paladugub7b36372018-11-26 16:27:39 +0530167 u32 rserved12[36];
168 u32 dcfg6; /* 0x294 Design config reg6 */
169 u32 reserved7[106];
Edgar E. Iglesias23045112015-09-25 23:50:07 -0700170 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
171 u32 reserved8[15];
172 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530173 u32 reserved10[17];
174 u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
175 u32 reserved11[2];
176 u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
Michal Simek19dfc472012-09-13 20:23:34 +0000177};
178
179/* BD descriptors */
180struct emac_bd {
181 u32 addr; /* Next descriptor pointer */
182 u32 status;
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530183#if defined(CONFIG_PHYS_64BIT)
184 u32 addr_hi;
185 u32 reserved;
186#endif
Michal Simek19dfc472012-09-13 20:23:34 +0000187};
188
Michal Simekc40c93e2019-05-22 14:12:20 +0200189/* Reduce amount of BUFs if you have limited amount of memory */
Siva Durga Prasad Paladugu55931cf2015-04-15 12:15:01 +0530190#define RX_BUF 32
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530191/* Page table entries are set to 1MB, or multiples of 1MB
192 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
193 */
194#define BD_SPACE 0x100000
195/* BD separation space */
Michal Simekc6eb0bc2015-08-17 09:45:53 +0200196#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
Michal Simek19dfc472012-09-13 20:23:34 +0000197
Edgar E. Iglesias23045112015-09-25 23:50:07 -0700198/* Setup the first free TX descriptor */
199#define TX_FREE_DESC 2
200
Michal Simek19dfc472012-09-13 20:23:34 +0000201/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
202struct zynq_gem_priv {
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530203 struct emac_bd *tx_bd;
204 struct emac_bd *rx_bd;
205 char *rxbuffers;
Michal Simek19dfc472012-09-13 20:23:34 +0000206 u32 rxbd_current;
207 u32 rx_first_buf;
208 int phyaddr;
Michal Simeka94f84d2013-01-24 13:04:12 +0100209 int init;
Michal Simek1a63ee22015-11-30 10:24:15 +0100210 struct zynq_gem_regs *iobase;
Michal Simek55ee1862016-05-30 10:43:11 +0200211 struct zynq_gem_regs *mdiobase;
Michal Simek492de0f2015-10-07 16:42:56 +0200212 phy_interface_t interface;
Michal Simek19dfc472012-09-13 20:23:34 +0000213 struct phy_device *phydev;
Siva Durga Prasad Paladugu34a48e52018-07-16 18:25:45 +0530214 ofnode phy_of_node;
Michal Simek19dfc472012-09-13 20:23:34 +0000215 struct mii_dev *bus;
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700216 struct clk rx_clk;
217 struct clk tx_clk;
Siva Durga Prasad Paladugu0703cc52018-04-12 12:22:17 +0200218 u32 max_speed;
Siva Durga Prasad Paladugu134cfa62017-11-23 12:56:55 +0530219 bool int_pcs;
Siva Durga Prasad Paladugub7b36372018-11-26 16:27:39 +0530220 bool dma_64bit;
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700221 u32 clk_en_info;
Michal Simekc86e7fc2021-12-06 16:25:20 +0100222 struct reset_ctl_bulk resets;
Michal Simek19dfc472012-09-13 20:23:34 +0000223};
224
Michal Simek70551ca2018-06-13 10:00:30 +0200225static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
Michal Simek1a63ee22015-11-30 10:24:15 +0100226 u32 op, u16 *data)
Michal Simek19dfc472012-09-13 20:23:34 +0000227{
228 u32 mgtcr;
Michal Simek55ee1862016-05-30 10:43:11 +0200229 struct zynq_gem_regs *regs = priv->mdiobase;
Michal Simeke6709652016-12-12 09:47:26 +0100230 int err;
Michal Simek19dfc472012-09-13 20:23:34 +0000231
Álvaro Fernåndez Rojas918de032018-01-23 17:14:55 +0100232 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
Ashok Reddy Soma06250462021-11-18 13:05:24 +0100233 true, MDIO_IDLE_TIMEOUT_MS, false);
Michal Simeke6709652016-12-12 09:47:26 +0100234 if (err)
235 return err;
Michal Simek19dfc472012-09-13 20:23:34 +0000236
237 /* Construct mgtcr mask for the operation */
238 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
239 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
240 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
241
242 /* Write mgtcr and wait for completion */
243 writel(mgtcr, &regs->phymntnc);
244
Álvaro Fernåndez Rojas918de032018-01-23 17:14:55 +0100245 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
Ashok Reddy Soma06250462021-11-18 13:05:24 +0100246 true, MDIO_IDLE_TIMEOUT_MS, false);
Michal Simeke6709652016-12-12 09:47:26 +0100247 if (err)
248 return err;
Michal Simek19dfc472012-09-13 20:23:34 +0000249
250 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
251 *data = readl(&regs->phymntnc);
252
253 return 0;
254}
255
Michal Simek70551ca2018-06-13 10:00:30 +0200256static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
Michal Simek1a63ee22015-11-30 10:24:15 +0100257 u32 regnum, u16 *val)
Michal Simek19dfc472012-09-13 20:23:34 +0000258{
Michal Simek70551ca2018-06-13 10:00:30 +0200259 int ret;
Michal Simekc919c2c2015-10-07 16:34:51 +0200260
Michal Simek1a63ee22015-11-30 10:24:15 +0100261 ret = phy_setup_op(priv, phy_addr, regnum,
262 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
Michal Simekc919c2c2015-10-07 16:34:51 +0200263
264 if (!ret)
265 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
266 phy_addr, regnum, *val);
267
268 return ret;
Michal Simek19dfc472012-09-13 20:23:34 +0000269}
270
Michal Simek70551ca2018-06-13 10:00:30 +0200271static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
Michal Simek1a63ee22015-11-30 10:24:15 +0100272 u32 regnum, u16 data)
Michal Simek19dfc472012-09-13 20:23:34 +0000273{
Michal Simekc919c2c2015-10-07 16:34:51 +0200274 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
275 regnum, data);
276
Michal Simek1a63ee22015-11-30 10:24:15 +0100277 return phy_setup_op(priv, phy_addr, regnum,
278 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
Michal Simek19dfc472012-09-13 20:23:34 +0000279}
280
Michal Simek250e05e2015-11-30 14:14:56 +0100281static int zynq_gem_setup_mac(struct udevice *dev)
Michal Simek19dfc472012-09-13 20:23:34 +0000282{
283 u32 i, macaddrlow, macaddrhigh;
Simon Glassfa20e932020-12-03 16:55:20 -0700284 struct eth_pdata *pdata = dev_get_plat(dev);
Michal Simek250e05e2015-11-30 14:14:56 +0100285 struct zynq_gem_priv *priv = dev_get_priv(dev);
286 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek19dfc472012-09-13 20:23:34 +0000287
288 /* Set the MAC bits [31:0] in BOT */
Michal Simek250e05e2015-11-30 14:14:56 +0100289 macaddrlow = pdata->enetaddr[0];
290 macaddrlow |= pdata->enetaddr[1] << 8;
291 macaddrlow |= pdata->enetaddr[2] << 16;
292 macaddrlow |= pdata->enetaddr[3] << 24;
Michal Simek19dfc472012-09-13 20:23:34 +0000293
294 /* Set MAC bits [47:32] in TOP */
Michal Simek250e05e2015-11-30 14:14:56 +0100295 macaddrhigh = pdata->enetaddr[4];
296 macaddrhigh |= pdata->enetaddr[5] << 8;
Michal Simek19dfc472012-09-13 20:23:34 +0000297
298 for (i = 0; i < 4; i++) {
299 writel(0, &regs->laddr[i][LADDR_LOW]);
300 writel(0, &regs->laddr[i][LADDR_HIGH]);
301 /* Do not use MATCHx register */
302 writel(0, &regs->match[i]);
303 }
304
305 writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
306 writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
307
308 return 0;
309}
310
Michal Simek250e05e2015-11-30 14:14:56 +0100311static int zynq_phy_init(struct udevice *dev)
Michal Simek19dfc472012-09-13 20:23:34 +0000312{
Michal Simek75fbb692015-11-30 13:38:32 +0100313 int ret;
Michal Simek250e05e2015-11-30 14:14:56 +0100314 struct zynq_gem_priv *priv = dev_get_priv(dev);
Michal Simek55ee1862016-05-30 10:43:11 +0200315 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
Michal Simek19dfc472012-09-13 20:23:34 +0000316 const u32 supported = SUPPORTED_10baseT_Half |
317 SUPPORTED_10baseT_Full |
318 SUPPORTED_100baseT_Half |
319 SUPPORTED_100baseT_Full |
320 SUPPORTED_1000baseT_Half |
321 SUPPORTED_1000baseT_Full;
322
Michal Simeke9ecc1c2015-11-30 13:58:36 +0100323 /* Enable only MDIO bus */
Michal Simek55ee1862016-05-30 10:43:11 +0200324 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs_mdio->nwctrl);
Michal Simeke9ecc1c2015-11-30 13:58:36 +0100325
Michal Simekb0017982022-03-30 11:07:53 +0200326 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
327 priv->phyaddr = eth_phy_get_addr(dev);
328
Michal Simek7cd7ea62015-11-30 13:54:43 +0100329 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
330 priv->interface);
Venkatesh Yadav Abbarapu1bbe4502022-09-29 10:26:05 +0530331 if (IS_ERR_OR_NULL(priv->phydev))
Michal Simek2c68e082015-11-30 14:03:37 +0100332 return -ENODEV;
Michal Simek7cd7ea62015-11-30 13:54:43 +0100333
Siva Durga Prasad Paladugu0703cc52018-04-12 12:22:17 +0200334 if (priv->max_speed) {
335 ret = phy_set_supported(priv->phydev, priv->max_speed);
336 if (ret)
337 return ret;
338 }
339
Siva Durga Prasad Paladugu12203502019-03-27 17:39:59 +0530340 priv->phydev->supported &= supported | ADVERTISED_Pause |
341 ADVERTISED_Asym_Pause;
342
Michal Simek7cd7ea62015-11-30 13:54:43 +0100343 priv->phydev->advertising = priv->phydev->supported;
Ashok Reddy Somabea12f42022-01-14 13:08:07 +0100344 if (!ofnode_valid(priv->phydev->node))
345 priv->phydev->node = priv->phy_of_node;
Dan Murphya5828712016-05-02 15:45:57 -0500346
Michal Simek24ce2322016-05-18 14:37:23 +0200347 return phy_config(priv->phydev);
Michal Simek7cd7ea62015-11-30 13:54:43 +0100348}
349
Michal Simek250e05e2015-11-30 14:14:56 +0100350static int zynq_gem_init(struct udevice *dev)
Michal Simek7cd7ea62015-11-30 13:54:43 +0100351{
Siva Durga Prasad Paladugu65d3f3a2016-02-05 13:22:11 +0530352 u32 i, nwconfig;
Michal Simekdbc0cfc2016-05-18 12:37:22 +0200353 int ret;
Michal Simek7cd7ea62015-11-30 13:54:43 +0100354 unsigned long clk_rate = 0;
Michal Simek250e05e2015-11-30 14:14:56 +0100355 struct zynq_gem_priv *priv = dev_get_priv(dev);
356 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek55ee1862016-05-30 10:43:11 +0200357 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
Michal Simek7cd7ea62015-11-30 13:54:43 +0100358 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
359 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
360
Siva Durga Prasad Paladugub7b36372018-11-26 16:27:39 +0530361 if (readl(&regs->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
362 priv->dma_64bit = true;
363 else
364 priv->dma_64bit = false;
365
366#if defined(CONFIG_PHYS_64BIT)
367 if (!priv->dma_64bit) {
368 printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
369 __func__);
370 return -EINVAL;
371 }
372#else
373 if (priv->dma_64bit)
374 debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
375 __func__);
376#endif
377
Michal Simeka94f84d2013-01-24 13:04:12 +0100378 if (!priv->init) {
379 /* Disable all interrupts */
380 writel(0xFFFFFFFF, &regs->idr);
Michal Simek19dfc472012-09-13 20:23:34 +0000381
Michal Simeka94f84d2013-01-24 13:04:12 +0100382 /* Disable the receiver & transmitter */
383 writel(0, &regs->nwctrl);
384 writel(0, &regs->txsr);
385 writel(0, &regs->rxsr);
386 writel(0, &regs->phymntnc);
Michal Simek19dfc472012-09-13 20:23:34 +0000387
Michal Simeka94f84d2013-01-24 13:04:12 +0100388 /* Clear the Hash registers for the mac address
389 * pointed by AddressPtr
390 */
391 writel(0x0, &regs->hashl);
392 /* Write bits [63:32] in TOP */
393 writel(0x0, &regs->hashh);
Michal Simek19dfc472012-09-13 20:23:34 +0000394
Michal Simeka94f84d2013-01-24 13:04:12 +0100395 /* Clear all counters */
Michal Simekff5dbef2015-10-05 12:49:48 +0200396 for (i = 0; i < STAT_SIZE; i++)
Michal Simeka94f84d2013-01-24 13:04:12 +0100397 readl(&regs->stat[i]);
Michal Simek19dfc472012-09-13 20:23:34 +0000398
Michal Simeka94f84d2013-01-24 13:04:12 +0100399 /* Setup RxBD space */
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530400 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
Michal Simek19dfc472012-09-13 20:23:34 +0000401
Michal Simeka94f84d2013-01-24 13:04:12 +0100402 for (i = 0; i < RX_BUF; i++) {
403 priv->rx_bd[i].status = 0xF0000000;
404 priv->rx_bd[i].addr =
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530405 (lower_32_bits((ulong)(priv->rxbuffers)
406 + (i * PKTSIZE_ALIGN)));
407#if defined(CONFIG_PHYS_64BIT)
408 priv->rx_bd[i].addr_hi =
409 (upper_32_bits((ulong)(priv->rxbuffers)
410 + (i * PKTSIZE_ALIGN)));
411#endif
412 }
Michal Simeka94f84d2013-01-24 13:04:12 +0100413 /* WRAP bit to last BD */
414 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
415 /* Write RxBDs to IP */
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530416 writel(lower_32_bits((ulong)priv->rx_bd), &regs->rxqbase);
417#if defined(CONFIG_PHYS_64BIT)
418 writel(upper_32_bits((ulong)priv->rx_bd), &regs->upper_rxqbase);
419#endif
Michal Simek19dfc472012-09-13 20:23:34 +0000420
Michal Simeka94f84d2013-01-24 13:04:12 +0100421 /* Setup for DMA Configuration register */
422 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
Michal Simek19dfc472012-09-13 20:23:34 +0000423
Michal Simeka94f84d2013-01-24 13:04:12 +0100424 /* Setup for Network Control register, MDIO, Rx and Tx enable */
Michal Simek55ee1862016-05-30 10:43:11 +0200425 setbits_le32(&regs_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
Michal Simek19dfc472012-09-13 20:23:34 +0000426
Edgar E. Iglesias23045112015-09-25 23:50:07 -0700427 /* Disable the second priority queue */
428 dummy_tx_bd->addr = 0;
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530429#if defined(CONFIG_PHYS_64BIT)
430 dummy_tx_bd->addr_hi = 0;
431#endif
Edgar E. Iglesias23045112015-09-25 23:50:07 -0700432 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
433 ZYNQ_GEM_TXBUF_LAST_MASK|
434 ZYNQ_GEM_TXBUF_USED_MASK;
435
436 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
437 ZYNQ_GEM_RXBUF_NEW_MASK;
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530438#if defined(CONFIG_PHYS_64BIT)
439 dummy_rx_bd->addr_hi = 0;
440#endif
Edgar E. Iglesias23045112015-09-25 23:50:07 -0700441 dummy_rx_bd->status = 0;
Edgar E. Iglesias23045112015-09-25 23:50:07 -0700442
443 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
444 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
445
Michal Simeka94f84d2013-01-24 13:04:12 +0100446 priv->init++;
447 }
448
Michal Simekdbc0cfc2016-05-18 12:37:22 +0200449 ret = phy_startup(priv->phydev);
450 if (ret)
451 return ret;
Michal Simek19dfc472012-09-13 20:23:34 +0000452
Michal Simek43b38322015-11-30 13:44:49 +0100453 if (!priv->phydev->link) {
454 printf("%s: No link.\n", priv->phydev->dev->name);
Michal Simek216b96d2013-11-12 14:25:29 +0100455 return -1;
456 }
457
Siva Durga Prasad Paladugu65d3f3a2016-02-05 13:22:11 +0530458 nwconfig = ZYNQ_GEM_NWCFG_INIT;
459
Siva Durga Prasad Paladugu134cfa62017-11-23 12:56:55 +0530460 /*
461 * Set SGMII enable PCS selection only if internal PCS/PMA
462 * core is used and interface is SGMII.
463 */
464 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
465 priv->int_pcs) {
Siva Durga Prasad Paladugu65d3f3a2016-02-05 13:22:11 +0530466 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
467 ZYNQ_GEM_NWCFG_PCS_SEL;
Siva Durga Prasad Paladugu45467002016-03-25 12:53:44 +0530468 }
Siva Durga Prasad Paladugu65d3f3a2016-02-05 13:22:11 +0530469
Michal Simek43b38322015-11-30 13:44:49 +0100470 switch (priv->phydev->speed) {
Michal Simekd9f2c112012-10-15 14:01:23 +0200471 case SPEED_1000:
Siva Durga Prasad Paladugu65d3f3a2016-02-05 13:22:11 +0530472 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
Michal Simekd9f2c112012-10-15 14:01:23 +0200473 &regs->nwcfg);
Soren Brinkmann4dded982013-11-21 13:39:01 -0800474 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
Michal Simekd9f2c112012-10-15 14:01:23 +0200475 break;
476 case SPEED_100:
Siva Durga Prasad Paladugu65d3f3a2016-02-05 13:22:11 +0530477 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
Michal Simek64295952015-09-08 16:55:42 +0200478 &regs->nwcfg);
Soren Brinkmann4dded982013-11-21 13:39:01 -0800479 clk_rate = ZYNQ_GEM_FREQUENCY_100;
Michal Simekd9f2c112012-10-15 14:01:23 +0200480 break;
481 case SPEED_10:
Soren Brinkmann4dded982013-11-21 13:39:01 -0800482 clk_rate = ZYNQ_GEM_FREQUENCY_10;
Michal Simekd9f2c112012-10-15 14:01:23 +0200483 break;
484 }
Robert Hancock3d6a9e02021-03-11 16:55:50 -0600485
486#ifdef CONFIG_ARM64
487 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
488 priv->int_pcs) {
489 /*
490 * Disable AN for fixed link configuration, enable otherwise.
491 * Must be written after PCS_SEL is set in nwconfig,
492 * otherwise writes will not take effect.
493 */
494 if (priv->phydev->phy_id != PHY_FIXED_ID)
495 writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
496 &regs->pcscntrl);
497 else
498 writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
499 &regs->pcscntrl);
500 }
501#endif
David Andrey73875dc2013-04-05 17:24:24 +0200502
Michal Simeka170e432022-08-26 10:30:47 +0200503 ret = clk_get_rate(&priv->tx_clk);
504 if (ret != clk_rate) {
505 ret = clk_set_rate(&priv->tx_clk, clk_rate);
506 if (IS_ERR_VALUE(ret)) {
507 dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate);
508 return ret;
509 }
Stefan Herbrechtsmeierbb433972017-01-17 16:27:25 +0100510 }
511
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700512 ret = clk_enable(&priv->tx_clk);
Michal Simek41710952021-02-09 15:28:15 +0100513 if (ret) {
Stefan Herbrechtsmeierbb433972017-01-17 16:27:25 +0100514 dev_err(dev, "failed to enable tx clock\n");
515 return ret;
516 }
Michal Simekd9f2c112012-10-15 14:01:23 +0200517
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700518 if (priv->clk_en_info & RXCLK_EN) {
519 ret = clk_enable(&priv->rx_clk);
520 if (ret) {
521 dev_err(dev, "failed to enable rx clock\n");
522 return ret;
523 }
524 }
Michal Simekd9f2c112012-10-15 14:01:23 +0200525 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
526 ZYNQ_GEM_NWCTRL_TXEN_MASK);
527
Michal Simek19dfc472012-09-13 20:23:34 +0000528 return 0;
529}
530
Michal Simek250e05e2015-11-30 14:14:56 +0100531static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
Michal Simek19dfc472012-09-13 20:23:34 +0000532{
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530533 dma_addr_t addr;
534 u32 size;
Michal Simek250e05e2015-11-30 14:14:56 +0100535 struct zynq_gem_priv *priv = dev_get_priv(dev);
536 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek1dc446e2015-08-17 09:58:54 +0200537 struct emac_bd *current_bd = &priv->tx_bd[1];
Michal Simek19dfc472012-09-13 20:23:34 +0000538
Michal Simek19dfc472012-09-13 20:23:34 +0000539 /* Setup Tx BD */
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530540 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
Michal Simek19dfc472012-09-13 20:23:34 +0000541
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530542 priv->tx_bd->addr = lower_32_bits((ulong)ptr);
543#if defined(CONFIG_PHYS_64BIT)
544 priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
545#endif
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530546 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
Michal Simek1dc446e2015-08-17 09:58:54 +0200547 ZYNQ_GEM_TXBUF_LAST_MASK;
548 /* Dummy descriptor to mark it as the last in descriptor chain */
549 current_bd->addr = 0x0;
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530550#if defined(CONFIG_PHYS_64BIT)
551 current_bd->addr_hi = 0x0;
552#endif
Michal Simek1dc446e2015-08-17 09:58:54 +0200553 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
554 ZYNQ_GEM_TXBUF_LAST_MASK|
555 ZYNQ_GEM_TXBUF_USED_MASK;
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530556
Michal Simekb6fe7ad2015-08-17 09:50:09 +0200557 /* setup BD */
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530558 writel(lower_32_bits((ulong)priv->tx_bd), &regs->txqbase);
559#if defined(CONFIG_PHYS_64BIT)
560 writel(upper_32_bits((ulong)priv->tx_bd), &regs->upper_txqbase);
561#endif
Michal Simekb6fe7ad2015-08-17 09:50:09 +0200562
Prabhakar Kushwaha1e9e6192015-10-25 13:18:54 +0530563 addr = (ulong) ptr;
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530564 addr &= ~(ARCH_DMA_MINALIGN - 1);
565 size = roundup(len, ARCH_DMA_MINALIGN);
566 flush_dcache_range(addr, addr + size);
567 barrier();
Michal Simek19dfc472012-09-13 20:23:34 +0000568
569 /* Start transmit */
570 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
571
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530572 /* Read TX BD status */
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530573 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
574 printf("TX buffers exhausted in mid frame\n");
Michal Simek19dfc472012-09-13 20:23:34 +0000575
Álvaro Fernåndez Rojas918de032018-01-23 17:14:55 +0100576 return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
577 true, 20000, true);
Michal Simek19dfc472012-09-13 20:23:34 +0000578}
579
580/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
Michal Simek250e05e2015-11-30 14:14:56 +0100581static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek19dfc472012-09-13 20:23:34 +0000582{
583 int frame_len;
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530584 dma_addr_t addr;
Michal Simek250e05e2015-11-30 14:14:56 +0100585 struct zynq_gem_priv *priv = dev_get_priv(dev);
Michal Simek19dfc472012-09-13 20:23:34 +0000586 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
Michal Simek19dfc472012-09-13 20:23:34 +0000587
588 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
Michal Simek57b02692015-12-09 14:26:48 +0100589 return -1;
Michal Simek19dfc472012-09-13 20:23:34 +0000590
591 if (!(current_bd->status &
592 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
593 printf("GEM: SOF or EOF not set for last buffer received!\n");
Michal Simek57b02692015-12-09 14:26:48 +0100594 return -1;
Michal Simek19dfc472012-09-13 20:23:34 +0000595 }
596
597 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
Michal Simek57b02692015-12-09 14:26:48 +0100598 if (!frame_len) {
599 printf("%s: Zero size packet?\n", __func__);
600 return -1;
601 }
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530602
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530603#if defined(CONFIG_PHYS_64BIT)
604 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
605 | ((dma_addr_t)current_bd->addr_hi << 32));
606#else
Michal Simek57b02692015-12-09 14:26:48 +0100607 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530608#endif
Michal Simek57b02692015-12-09 14:26:48 +0100609 addr &= ~(ARCH_DMA_MINALIGN - 1);
Vipul Kumarcbc2ed62018-11-26 16:27:38 +0530610
Michal Simek57b02692015-12-09 14:26:48 +0100611 *packetp = (uchar *)(uintptr_t)addr;
Michal Simek19dfc472012-09-13 20:23:34 +0000612
Stefan Theil0f407c92018-12-17 09:12:30 +0100613 invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
614 barrier();
615
Michal Simek57b02692015-12-09 14:26:48 +0100616 return frame_len;
617}
618
619static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
620{
621 struct zynq_gem_priv *priv = dev_get_priv(dev);
622 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
623 struct emac_bd *first_bd;
Ashok Reddy Soma47572532020-02-23 08:01:29 -0700624 dma_addr_t addr;
Michal Simek19dfc472012-09-13 20:23:34 +0000625
Michal Simek57b02692015-12-09 14:26:48 +0100626 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
627 priv->rx_first_buf = priv->rxbd_current;
628 } else {
629 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
630 current_bd->status = 0xF0000000; /* FIXME */
631 }
Michal Simek19dfc472012-09-13 20:23:34 +0000632
Michal Simek57b02692015-12-09 14:26:48 +0100633 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
634 first_bd = &priv->rx_bd[priv->rx_first_buf];
635 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
636 first_bd->status = 0xF0000000;
Michal Simek19dfc472012-09-13 20:23:34 +0000637 }
638
Ashok Reddy Soma47572532020-02-23 08:01:29 -0700639 /* Flush the cache for the packet as well */
640#if defined(CONFIG_PHYS_64BIT)
641 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
642 | ((dma_addr_t)current_bd->addr_hi << 32));
643#else
644 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
645#endif
646 flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN,
647 ARCH_DMA_MINALIGN));
648 barrier();
649
Michal Simek57b02692015-12-09 14:26:48 +0100650 if ((++priv->rxbd_current) >= RX_BUF)
651 priv->rxbd_current = 0;
652
Michal Simek139f4102015-12-09 14:16:32 +0100653 return 0;
Michal Simek19dfc472012-09-13 20:23:34 +0000654}
655
Michal Simek250e05e2015-11-30 14:14:56 +0100656static void zynq_gem_halt(struct udevice *dev)
Michal Simek19dfc472012-09-13 20:23:34 +0000657{
Michal Simek250e05e2015-11-30 14:14:56 +0100658 struct zynq_gem_priv *priv = dev_get_priv(dev);
659 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek19dfc472012-09-13 20:23:34 +0000660
Michal Simekd9f2c112012-10-15 14:01:23 +0200661 clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
662 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
Michal Simek19dfc472012-09-13 20:23:34 +0000663}
664
Michal Simek250e05e2015-11-30 14:14:56 +0100665static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
666 int devad, int reg)
Michal Simek19dfc472012-09-13 20:23:34 +0000667{
Michal Simek250e05e2015-11-30 14:14:56 +0100668 struct zynq_gem_priv *priv = bus->priv;
Michal Simek19dfc472012-09-13 20:23:34 +0000669 int ret;
Michal Simekd061bfd2018-06-14 09:08:44 +0200670 u16 val = 0;
Michal Simek19dfc472012-09-13 20:23:34 +0000671
Michal Simek250e05e2015-11-30 14:14:56 +0100672 ret = phyread(priv, addr, reg, &val);
673 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
674 return val;
Michal Simek19dfc472012-09-13 20:23:34 +0000675}
676
Michal Simek250e05e2015-11-30 14:14:56 +0100677static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
678 int reg, u16 value)
Michal Simek19dfc472012-09-13 20:23:34 +0000679{
Michal Simek250e05e2015-11-30 14:14:56 +0100680 struct zynq_gem_priv *priv = bus->priv;
Michal Simek19dfc472012-09-13 20:23:34 +0000681
Michal Simek250e05e2015-11-30 14:14:56 +0100682 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
683 return phywrite(priv, addr, reg, value);
Michal Simek19dfc472012-09-13 20:23:34 +0000684}
685
Michal Simekc86e7fc2021-12-06 16:25:20 +0100686static int zynq_gem_reset_init(struct udevice *dev)
687{
688 struct zynq_gem_priv *priv = dev_get_priv(dev);
689 int ret;
690
691 ret = reset_get_bulk(dev, &priv->resets);
692 if (ret == -ENOTSUPP || ret == -ENOENT)
693 return 0;
694 else if (ret)
695 return ret;
696
697 ret = reset_deassert_bulk(&priv->resets);
698 if (ret) {
699 reset_release_bulk(&priv->resets);
700 return ret;
701 }
702
703 return 0;
704}
705
T Karthik Reddy4a0e6b52022-03-30 11:07:58 +0200706static int gem_zynqmp_set_dynamic_config(struct udevice *dev)
707{
708 u32 pm_info[2];
709 int ret;
710
711 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) {
712 if (!zynqmp_pm_is_function_supported(PM_IOCTL,
713 IOCTL_SET_GEM_CONFIG)) {
714 ret = ofnode_read_u32_array(dev_ofnode(dev),
715 "power-domains",
716 pm_info,
717 ARRAY_SIZE(pm_info));
718 if (ret) {
719 dev_err(dev,
720 "Failed to read power-domains info\n");
721 return ret;
722 }
723
724 ret = zynqmp_pm_set_gem_config(pm_info[1],
725 GEM_CONFIG_FIXED, 0);
726 if (ret)
727 return ret;
728
729 ret = zynqmp_pm_set_gem_config(pm_info[1],
730 GEM_CONFIG_SGMII_MODE,
731 1);
732 if (ret)
733 return ret;
734 }
735 }
736
737 return 0;
738}
739
Michal Simek250e05e2015-11-30 14:14:56 +0100740static int zynq_gem_probe(struct udevice *dev)
Michal Simek19dfc472012-09-13 20:23:34 +0000741{
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530742 void *bd_space;
Michal Simek250e05e2015-11-30 14:14:56 +0100743 struct zynq_gem_priv *priv = dev_get_priv(dev);
744 int ret;
Michal Simekc8142d42021-12-15 11:00:01 +0100745 struct phy phy;
746
747 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
748 ret = generic_phy_get_by_index(dev, 0, &phy);
749 if (!ret) {
750 ret = generic_phy_init(&phy);
751 if (ret)
752 return ret;
753 } else if (ret != -ENOENT) {
754 debug("could not get phy (err %d)\n", ret);
755 return ret;
756 }
757 }
Michal Simek19dfc472012-09-13 20:23:34 +0000758
Michal Simekc86e7fc2021-12-06 16:25:20 +0100759 ret = zynq_gem_reset_init(dev);
760 if (ret)
761 return ret;
762
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530763 /* Align rxbuffers to ARCH_DMA_MINALIGN */
764 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
Michal Simekc8959f42018-06-13 15:20:35 +0200765 if (!priv->rxbuffers)
766 return -ENOMEM;
767
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530768 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
T Karthik Reddy60bf2162020-01-15 02:15:13 -0700769 ulong addr = (ulong)priv->rxbuffers;
Stefan Theil0f407c92018-12-17 09:12:30 +0100770 flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
771 barrier();
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530772
Siva Durga Prasad Paladugu2b0690e2014-12-06 12:57:53 +0530773 /* Align bd_space to MMU_SECTION_SHIFT */
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530774 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Michal Simek049c65b2020-02-06 14:36:46 +0100775 if (!bd_space) {
776 ret = -ENOMEM;
777 goto err1;
778 }
Michal Simekc8959f42018-06-13 15:20:35 +0200779
Michal Simek0afb6b22015-04-15 13:31:28 +0200780 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
781 BD_SPACE, DCACHE_OFF);
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530782
783 /* Initialize the bd spaces for tx and rx bd's */
784 priv->tx_bd = (struct emac_bd *)bd_space;
Prabhakar Kushwaha1e9e6192015-10-25 13:18:54 +0530785 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
Srikanth Thokalacbf20b22013-11-08 22:55:48 +0530786
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700787 ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk);
Siva Durga Prasad Paladugubaa20352016-11-15 16:15:42 +0530788 if (ret < 0) {
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700789 dev_err(dev, "failed to get tx_clock\n");
Michal Simek179f7d72021-02-11 19:03:30 +0100790 goto err2;
Siva Durga Prasad Paladugubaa20352016-11-15 16:15:42 +0530791 }
Siva Durga Prasad Paladugubaa20352016-11-15 16:15:42 +0530792
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700793 if (priv->clk_en_info & RXCLK_EN) {
794 ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk);
795 if (ret < 0) {
796 dev_err(dev, "failed to get rx_clock\n");
Michal Simek179f7d72021-02-11 19:03:30 +0100797 goto err2;
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700798 }
799 }
800
Michal Simekb0017982022-03-30 11:07:53 +0200801 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
802 priv->bus = eth_phy_get_mdio_bus(dev);
Michal Simek19dfc472012-09-13 20:23:34 +0000803
Michal Simekb0017982022-03-30 11:07:53 +0200804 if (!priv->bus) {
805 priv->bus = mdio_alloc();
806 priv->bus->read = zynq_gem_miiphy_read;
807 priv->bus->write = zynq_gem_miiphy_write;
808 priv->bus->priv = priv;
809
810 ret = mdio_register_seq(priv->bus, dev_seq(dev));
811 if (ret)
812 goto err2;
813 }
814
815 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
816 eth_phy_set_mdio_bus(dev, priv->bus);
Michal Simek049c65b2020-02-06 14:36:46 +0100817
818 ret = zynq_phy_init(dev);
819 if (ret)
Michael Walle465437c2021-02-10 22:41:57 +0100820 goto err3;
Michal Simek049c65b2020-02-06 14:36:46 +0100821
Michal Simekc8142d42021-12-15 11:00:01 +0100822 if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
T Karthik Reddy4a0e6b52022-03-30 11:07:58 +0200823 if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
824 if (device_is_compatible(dev, "cdns,zynqmp-gem")) {
825 ret = gem_zynqmp_set_dynamic_config(dev);
826 if (ret) {
827 dev_err
828 (dev,
829 "Failed to set gem dynamic config\n");
830 return ret;
831 }
832 }
833 }
Michal Simekc8142d42021-12-15 11:00:01 +0100834 ret = generic_phy_power_on(&phy);
835 if (ret)
836 return ret;
837 }
838
T Karthik Reddy297521e2022-03-30 11:07:55 +0200839 printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
840 (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phydev->addr,
841 phy_string_for_interface(priv->interface));
842
Michal Simek049c65b2020-02-06 14:36:46 +0100843 return ret;
Michal Simek19dfc472012-09-13 20:23:34 +0000844
Michael Walle465437c2021-02-10 22:41:57 +0100845err3:
846 mdio_unregister(priv->bus);
Michal Simek049c65b2020-02-06 14:36:46 +0100847err2:
Michal Simek049c65b2020-02-06 14:36:46 +0100848 free(priv->tx_bd);
Michal Simek179f7d72021-02-11 19:03:30 +0100849err1:
850 free(priv->rxbuffers);
Michal Simek049c65b2020-02-06 14:36:46 +0100851 return ret;
Michal Simek250e05e2015-11-30 14:14:56 +0100852}
Michal Simek19dfc472012-09-13 20:23:34 +0000853
Michal Simek250e05e2015-11-30 14:14:56 +0100854static int zynq_gem_remove(struct udevice *dev)
855{
856 struct zynq_gem_priv *priv = dev_get_priv(dev);
Michal Simek19dfc472012-09-13 20:23:34 +0000857
Michal Simek250e05e2015-11-30 14:14:56 +0100858 free(priv->phydev);
859 mdio_unregister(priv->bus);
860 mdio_free(priv->bus);
Michal Simek19dfc472012-09-13 20:23:34 +0000861
Michal Simek250e05e2015-11-30 14:14:56 +0100862 return 0;
863}
864
865static const struct eth_ops zynq_gem_ops = {
866 .start = zynq_gem_init,
867 .send = zynq_gem_send,
868 .recv = zynq_gem_recv,
Michal Simek57b02692015-12-09 14:26:48 +0100869 .free_pkt = zynq_gem_free_pkt,
Michal Simek250e05e2015-11-30 14:14:56 +0100870 .stop = zynq_gem_halt,
871 .write_hwaddr = zynq_gem_setup_mac,
872};
Michal Simeke9ecc1c2015-11-30 13:58:36 +0100873
Simon Glassaad29ae2020-12-03 16:55:21 -0700874static int zynq_gem_of_to_plat(struct udevice *dev)
Michal Simek250e05e2015-11-30 14:14:56 +0100875{
Simon Glassfa20e932020-12-03 16:55:20 -0700876 struct eth_pdata *pdata = dev_get_plat(dev);
Michal Simek250e05e2015-11-30 14:14:56 +0100877 struct zynq_gem_priv *priv = dev_get_priv(dev);
Siva Durga Prasad Paladugu34a48e52018-07-16 18:25:45 +0530878 struct ofnode_phandle_args phandle_args;
Michal Simek250e05e2015-11-30 14:14:56 +0100879
Siva Durga Prasad Paladugu34a48e52018-07-16 18:25:45 +0530880 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
Michal Simek250e05e2015-11-30 14:14:56 +0100881 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
Michal Simek55ee1862016-05-30 10:43:11 +0200882 priv->mdiobase = priv->iobase;
Michal Simek250e05e2015-11-30 14:14:56 +0100883 /* Hardcode for now */
Michal Simekc6aa4132015-12-09 09:29:12 +0100884 priv->phyaddr = -1;
Michal Simek250e05e2015-11-30 14:14:56 +0100885
Michal Simek81145382018-09-20 09:42:27 +0200886 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
887 &phandle_args)) {
Michal Simek8ec90662016-05-30 10:43:11 +0200888 fdt_addr_t addr;
889 ofnode parent;
890
Michal Simek81145382018-09-20 09:42:27 +0200891 debug("phy-handle does exist %s\n", dev->name);
Michal Simekb0017982022-03-30 11:07:53 +0200892 if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
893 priv->phyaddr = ofnode_read_u32_default
894 (phandle_args.node, "reg", -1);
895
Michal Simek81145382018-09-20 09:42:27 +0200896 priv->phy_of_node = phandle_args.node;
897 priv->max_speed = ofnode_read_u32_default(phandle_args.node,
898 "max-speed",
899 SPEED_1000);
Michal Simek8ec90662016-05-30 10:43:11 +0200900
901 parent = ofnode_get_parent(phandle_args.node);
Michal Simekeac3c672021-12-06 14:53:17 +0100902 if (ofnode_name_eq(parent, "mdio"))
903 parent = ofnode_get_parent(parent);
904
Michal Simek8ec90662016-05-30 10:43:11 +0200905 addr = ofnode_get_addr(parent);
906 if (addr != FDT_ADDR_T_NONE) {
907 debug("MDIO bus not found %s\n", dev->name);
908 priv->mdiobase = (struct zynq_gem_regs *)addr;
909 }
Siva Durga Prasad Paladugu34a48e52018-07-16 18:25:45 +0530910 }
Michal Simek250e05e2015-11-30 14:14:56 +0100911
Marek BehĂșnbc194772022-04-07 00:33:01 +0200912 pdata->phy_interface = dev_read_phy_mode(dev);
Marek BehĂșn48631e42022-04-07 00:33:03 +0200913 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
Michal Simek3c4ce3c2015-11-30 14:17:50 +0100914 return -EINVAL;
Michal Simek3c4ce3c2015-11-30 14:17:50 +0100915 priv->interface = pdata->phy_interface;
916
Siva Durga Prasad Paladugu34a48e52018-07-16 18:25:45 +0530917 priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
Siva Durga Prasad Paladugu134cfa62017-11-23 12:56:55 +0530918
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700919 priv->clk_en_info = dev_get_driver_data(dev);
920
Michal Simek250e05e2015-11-30 14:14:56 +0100921 return 0;
Michal Simek19dfc472012-09-13 20:23:34 +0000922}
Michal Simek250e05e2015-11-30 14:14:56 +0100923
924static const struct udevice_id zynq_gem_ids[] = {
T Karthik Reddy68cd67d2021-02-03 03:10:48 -0700925 { .compatible = "cdns,versal-gem", .data = RXCLK_EN },
Michal Simek250e05e2015-11-30 14:14:56 +0100926 { .compatible = "cdns,zynqmp-gem" },
927 { .compatible = "cdns,zynq-gem" },
928 { .compatible = "cdns,gem" },
929 { }
930};
931
932U_BOOT_DRIVER(zynq_gem) = {
933 .name = "zynq_gem",
934 .id = UCLASS_ETH,
935 .of_match = zynq_gem_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700936 .of_to_plat = zynq_gem_of_to_plat,
Michal Simek250e05e2015-11-30 14:14:56 +0100937 .probe = zynq_gem_probe,
938 .remove = zynq_gem_remove,
939 .ops = &zynq_gem_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700940 .priv_auto = sizeof(struct zynq_gem_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -0700941 .plat_auto = sizeof(struct eth_pdata),
Michal Simek250e05e2015-11-30 14:14:56 +0100942};