Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011 Michal Simek |
| 4 | * |
| 5 | * Michal SIMEK <monstr@monstr.eu> |
| 6 | * |
| 7 | * Based on Xilinx gmac driver: |
| 8 | * (C) Copyright 2011 Xilinx |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 11 | #include <clk.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 12 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 13 | #include <cpu_func.h> |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 14 | #include <dm.h> |
Michal Simek | c8142d4 | 2021-12-15 11:00:01 +0100 | [diff] [blame] | 15 | #include <generic-phy.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 16 | #include <log.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 17 | #include <net.h> |
Michal Simek | b055f67 | 2014-04-25 14:17:38 +0200 | [diff] [blame] | 18 | #include <netdev.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 19 | #include <config.h> |
Michal Simek | d9cfa97 | 2015-09-24 20:13:45 +0200 | [diff] [blame] | 20 | #include <console.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 21 | #include <malloc.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 22 | #include <asm/cache.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 23 | #include <asm/io.h> |
| 24 | #include <phy.h> |
Michal Simek | c86e7fc | 2021-12-06 16:25:20 +0100 | [diff] [blame] | 25 | #include <reset.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 26 | #include <miiphy.h> |
Mateusz Kulikowski | 93597d7 | 2016-01-23 11:54:33 +0100 | [diff] [blame] | 27 | #include <wait_bit.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 28 | #include <watchdog.h> |
Siva Durga Prasad Paladugu | 2b0690e | 2014-12-06 12:57:53 +0530 | [diff] [blame] | 29 | #include <asm/system.h> |
David Andrey | 73875dc | 2013-04-05 17:24:24 +0200 | [diff] [blame] | 30 | #include <asm/arch/hardware.h> |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 31 | #include <asm/arch/sys_proto.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 32 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 33 | #include <linux/bitops.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 34 | #include <linux/err.h> |
Masahiro Yamada | 64e4f7f | 2016-09-21 11:28:57 +0900 | [diff] [blame] | 35 | #include <linux/errno.h> |
Michal Simek | b001798 | 2022-03-30 11:07:53 +0200 | [diff] [blame] | 36 | #include <eth_phy.h> |
T Karthik Reddy | 4a0e6b5 | 2022-03-30 11:07:58 +0200 | [diff] [blame] | 37 | #include <zynqmp_firmware.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 38 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 39 | /* Bit/mask specification */ |
| 40 | #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ |
| 41 | #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ |
| 42 | #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ |
| 43 | #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ |
| 44 | #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ |
| 45 | |
| 46 | #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ |
| 47 | #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ |
| 48 | #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ |
| 49 | |
| 50 | #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ |
| 51 | #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ |
| 52 | #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ |
| 53 | |
| 54 | /* Wrap bit, last descriptor */ |
| 55 | #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 |
| 56 | #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 57 | #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 58 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 59 | #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ |
| 60 | #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ |
| 61 | #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ |
| 62 | #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ |
| 63 | |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 64 | #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ |
| 65 | #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ |
| 66 | #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ |
| 67 | #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ |
Siva Durga Prasad Paladugu | f6c2d20 | 2016-05-16 15:31:38 +0530 | [diff] [blame] | 68 | #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 69 | #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ |
Michal Simek | 780c535 | 2015-09-08 17:20:01 +0200 | [diff] [blame] | 70 | #ifdef CONFIG_ARM64 |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 71 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ |
Michal Simek | 780c535 | 2015-09-08 17:20:01 +0200 | [diff] [blame] | 72 | #else |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 73 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ |
Michal Simek | 780c535 | 2015-09-08 17:20:01 +0200 | [diff] [blame] | 74 | #endif |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 75 | |
Siva Durga Prasad Paladugu | 71245a4 | 2014-07-08 15:31:03 +0530 | [diff] [blame] | 76 | #ifdef CONFIG_ARM64 |
| 77 | # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ |
| 78 | #else |
| 79 | # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ |
| 80 | #endif |
| 81 | |
| 82 | #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ |
| 83 | ZYNQ_GEM_NWCFG_FDEN | \ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 84 | ZYNQ_GEM_NWCFG_FSREM | \ |
| 85 | ZYNQ_GEM_NWCFG_MDCCLKDIV) |
| 86 | |
| 87 | #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ |
| 88 | |
| 89 | #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ |
| 90 | /* Use full configured addressable space (8 Kb) */ |
| 91 | #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 |
| 92 | /* Use full configured addressable space (4 Kb) */ |
| 93 | #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 |
| 94 | /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ |
| 95 | #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 |
| 96 | |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 97 | #if defined(CONFIG_PHYS_64BIT) |
| 98 | # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */ |
| 99 | #else |
| 100 | # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */ |
| 101 | #endif |
| 102 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 103 | #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ |
| 104 | ZYNQ_GEM_DMACR_RXSIZE | \ |
| 105 | ZYNQ_GEM_DMACR_TXSIZE | \ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 106 | ZYNQ_GEM_DMACR_RXBUF | \ |
| 107 | ZYNQ_GEM_DMA_BUS_WIDTH) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 108 | |
Michal Simek | 975ae35 | 2015-08-17 09:57:46 +0200 | [diff] [blame] | 109 | #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ |
| 110 | |
Siva Durga Prasad Paladugu | 4546700 | 2016-03-25 12:53:44 +0530 | [diff] [blame] | 111 | #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 |
| 112 | |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 113 | #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23) |
| 114 | |
Ashok Reddy Soma | 0625046 | 2021-11-18 13:05:24 +0100 | [diff] [blame] | 115 | #define MDIO_IDLE_TIMEOUT_MS 100 |
| 116 | |
Michal Simek | ab72cb4 | 2013-04-22 14:41:09 +0200 | [diff] [blame] | 117 | /* Use MII register 1 (MII status register) to detect PHY */ |
| 118 | #define PHY_DETECT_REG 1 |
| 119 | |
| 120 | /* Mask used to verify certain PHY features (or register contents) |
| 121 | * in the register above: |
| 122 | * 0x1000: 10Mbps full duplex support |
| 123 | * 0x0800: 10Mbps half duplex support |
| 124 | * 0x0008: Auto-negotiation support |
| 125 | */ |
| 126 | #define PHY_DETECT_MASK 0x1808 |
| 127 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 128 | /* TX BD status masks */ |
| 129 | #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff |
| 130 | #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 |
| 131 | #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 |
| 132 | |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 133 | /* Clock frequencies for different speeds */ |
| 134 | #define ZYNQ_GEM_FREQUENCY_10 2500000UL |
| 135 | #define ZYNQ_GEM_FREQUENCY_100 25000000UL |
| 136 | #define ZYNQ_GEM_FREQUENCY_1000 125000000UL |
| 137 | |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 138 | #define RXCLK_EN BIT(0) |
| 139 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 140 | /* Device registers */ |
| 141 | struct zynq_gem_regs { |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 142 | u32 nwctrl; /* 0x0 - Network Control reg */ |
| 143 | u32 nwcfg; /* 0x4 - Network Config reg */ |
| 144 | u32 nwsr; /* 0x8 - Network Status reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 145 | u32 reserved1; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 146 | u32 dmacr; /* 0x10 - DMA Control reg */ |
| 147 | u32 txsr; /* 0x14 - TX Status reg */ |
| 148 | u32 rxqbase; /* 0x18 - RX Q Base address reg */ |
| 149 | u32 txqbase; /* 0x1c - TX Q Base address reg */ |
| 150 | u32 rxsr; /* 0x20 - RX Status reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 151 | u32 reserved2[2]; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 152 | u32 idr; /* 0x2c - Interrupt Disable reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 153 | u32 reserved3; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 154 | u32 phymntnc; /* 0x34 - Phy Maintaince reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 155 | u32 reserved4[18]; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 156 | u32 hashl; /* 0x80 - Hash Low address reg */ |
| 157 | u32 hashh; /* 0x84 - Hash High address reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 158 | #define LADDR_LOW 0 |
| 159 | #define LADDR_HIGH 1 |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 160 | u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ |
| 161 | u32 match[4]; /* 0xa8 - Type ID1 Match reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 162 | u32 reserved6[18]; |
Michal Simek | ff5dbef | 2015-10-05 12:49:48 +0200 | [diff] [blame] | 163 | #define STAT_SIZE 44 |
| 164 | u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ |
Siva Durga Prasad Paladugu | 4546700 | 2016-03-25 12:53:44 +0530 | [diff] [blame] | 165 | u32 reserved9[20]; |
| 166 | u32 pcscntrl; |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 167 | u32 rserved12[36]; |
| 168 | u32 dcfg6; /* 0x294 Design config reg6 */ |
| 169 | u32 reserved7[106]; |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 170 | u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ |
| 171 | u32 reserved8[15]; |
| 172 | u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 173 | u32 reserved10[17]; |
| 174 | u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */ |
| 175 | u32 reserved11[2]; |
| 176 | u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 177 | }; |
| 178 | |
| 179 | /* BD descriptors */ |
| 180 | struct emac_bd { |
| 181 | u32 addr; /* Next descriptor pointer */ |
| 182 | u32 status; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 183 | #if defined(CONFIG_PHYS_64BIT) |
| 184 | u32 addr_hi; |
| 185 | u32 reserved; |
| 186 | #endif |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 187 | }; |
| 188 | |
Michal Simek | c40c93e | 2019-05-22 14:12:20 +0200 | [diff] [blame] | 189 | /* Reduce amount of BUFs if you have limited amount of memory */ |
Siva Durga Prasad Paladugu | 55931cf | 2015-04-15 12:15:01 +0530 | [diff] [blame] | 190 | #define RX_BUF 32 |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 191 | /* Page table entries are set to 1MB, or multiples of 1MB |
| 192 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. |
| 193 | */ |
| 194 | #define BD_SPACE 0x100000 |
| 195 | /* BD separation space */ |
Michal Simek | c6eb0bc | 2015-08-17 09:45:53 +0200 | [diff] [blame] | 196 | #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 197 | |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 198 | /* Setup the first free TX descriptor */ |
| 199 | #define TX_FREE_DESC 2 |
| 200 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 201 | /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ |
| 202 | struct zynq_gem_priv { |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 203 | struct emac_bd *tx_bd; |
| 204 | struct emac_bd *rx_bd; |
| 205 | char *rxbuffers; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 206 | u32 rxbd_current; |
| 207 | u32 rx_first_buf; |
| 208 | int phyaddr; |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 209 | int init; |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 210 | struct zynq_gem_regs *iobase; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 211 | struct zynq_gem_regs *mdiobase; |
Michal Simek | 492de0f | 2015-10-07 16:42:56 +0200 | [diff] [blame] | 212 | phy_interface_t interface; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 213 | struct phy_device *phydev; |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 214 | ofnode phy_of_node; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 215 | struct mii_dev *bus; |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 216 | struct clk rx_clk; |
| 217 | struct clk tx_clk; |
Siva Durga Prasad Paladugu | 0703cc5 | 2018-04-12 12:22:17 +0200 | [diff] [blame] | 218 | u32 max_speed; |
Siva Durga Prasad Paladugu | 134cfa6 | 2017-11-23 12:56:55 +0530 | [diff] [blame] | 219 | bool int_pcs; |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 220 | bool dma_64bit; |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 221 | u32 clk_en_info; |
Michal Simek | c86e7fc | 2021-12-06 16:25:20 +0100 | [diff] [blame] | 222 | struct reset_ctl_bulk resets; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 223 | }; |
| 224 | |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 225 | static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 226 | u32 op, u16 *data) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 227 | { |
| 228 | u32 mgtcr; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 229 | struct zynq_gem_regs *regs = priv->mdiobase; |
Michal Simek | e670965 | 2016-12-12 09:47:26 +0100 | [diff] [blame] | 230 | int err; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 231 | |
Ălvaro FernĂĄndez Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 232 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
Ashok Reddy Soma | 0625046 | 2021-11-18 13:05:24 +0100 | [diff] [blame] | 233 | true, MDIO_IDLE_TIMEOUT_MS, false); |
Michal Simek | e670965 | 2016-12-12 09:47:26 +0100 | [diff] [blame] | 234 | if (err) |
| 235 | return err; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 236 | |
| 237 | /* Construct mgtcr mask for the operation */ |
| 238 | mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | |
| 239 | (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | |
| 240 | (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; |
| 241 | |
| 242 | /* Write mgtcr and wait for completion */ |
| 243 | writel(mgtcr, ®s->phymntnc); |
| 244 | |
Ălvaro FernĂĄndez Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 245 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
Ashok Reddy Soma | 0625046 | 2021-11-18 13:05:24 +0100 | [diff] [blame] | 246 | true, MDIO_IDLE_TIMEOUT_MS, false); |
Michal Simek | e670965 | 2016-12-12 09:47:26 +0100 | [diff] [blame] | 247 | if (err) |
| 248 | return err; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 249 | |
| 250 | if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) |
| 251 | *data = readl(®s->phymntnc); |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 256 | static int phyread(struct zynq_gem_priv *priv, u32 phy_addr, |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 257 | u32 regnum, u16 *val) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 258 | { |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 259 | int ret; |
Michal Simek | c919c2c | 2015-10-07 16:34:51 +0200 | [diff] [blame] | 260 | |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 261 | ret = phy_setup_op(priv, phy_addr, regnum, |
| 262 | ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); |
Michal Simek | c919c2c | 2015-10-07 16:34:51 +0200 | [diff] [blame] | 263 | |
| 264 | if (!ret) |
| 265 | debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, |
| 266 | phy_addr, regnum, *val); |
| 267 | |
| 268 | return ret; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 269 | } |
| 270 | |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 271 | static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr, |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 272 | u32 regnum, u16 data) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 273 | { |
Michal Simek | c919c2c | 2015-10-07 16:34:51 +0200 | [diff] [blame] | 274 | debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, |
| 275 | regnum, data); |
| 276 | |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 277 | return phy_setup_op(priv, phy_addr, regnum, |
| 278 | ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 279 | } |
| 280 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 281 | static int zynq_gem_setup_mac(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 282 | { |
| 283 | u32 i, macaddrlow, macaddrhigh; |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 284 | struct eth_pdata *pdata = dev_get_plat(dev); |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 285 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 286 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 287 | |
| 288 | /* Set the MAC bits [31:0] in BOT */ |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 289 | macaddrlow = pdata->enetaddr[0]; |
| 290 | macaddrlow |= pdata->enetaddr[1] << 8; |
| 291 | macaddrlow |= pdata->enetaddr[2] << 16; |
| 292 | macaddrlow |= pdata->enetaddr[3] << 24; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 293 | |
| 294 | /* Set MAC bits [47:32] in TOP */ |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 295 | macaddrhigh = pdata->enetaddr[4]; |
| 296 | macaddrhigh |= pdata->enetaddr[5] << 8; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 297 | |
| 298 | for (i = 0; i < 4; i++) { |
| 299 | writel(0, ®s->laddr[i][LADDR_LOW]); |
| 300 | writel(0, ®s->laddr[i][LADDR_HIGH]); |
| 301 | /* Do not use MATCHx register */ |
| 302 | writel(0, ®s->match[i]); |
| 303 | } |
| 304 | |
| 305 | writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); |
| 306 | writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); |
| 307 | |
| 308 | return 0; |
| 309 | } |
| 310 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 311 | static int zynq_phy_init(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 312 | { |
Michal Simek | 75fbb69 | 2015-11-30 13:38:32 +0100 | [diff] [blame] | 313 | int ret; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 314 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 315 | struct zynq_gem_regs *regs_mdio = priv->mdiobase; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 316 | const u32 supported = SUPPORTED_10baseT_Half | |
| 317 | SUPPORTED_10baseT_Full | |
| 318 | SUPPORTED_100baseT_Half | |
| 319 | SUPPORTED_100baseT_Full | |
| 320 | SUPPORTED_1000baseT_Half | |
| 321 | SUPPORTED_1000baseT_Full; |
| 322 | |
Michal Simek | e9ecc1c | 2015-11-30 13:58:36 +0100 | [diff] [blame] | 323 | /* Enable only MDIO bus */ |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 324 | writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl); |
Michal Simek | e9ecc1c | 2015-11-30 13:58:36 +0100 | [diff] [blame] | 325 | |
Michal Simek | b001798 | 2022-03-30 11:07:53 +0200 | [diff] [blame] | 326 | if (IS_ENABLED(CONFIG_DM_ETH_PHY)) |
| 327 | priv->phyaddr = eth_phy_get_addr(dev); |
| 328 | |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 329 | priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, |
| 330 | priv->interface); |
Venkatesh Yadav Abbarapu | 1bbe450 | 2022-09-29 10:26:05 +0530 | [diff] [blame] | 331 | if (IS_ERR_OR_NULL(priv->phydev)) |
Michal Simek | 2c68e08 | 2015-11-30 14:03:37 +0100 | [diff] [blame] | 332 | return -ENODEV; |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 333 | |
Siva Durga Prasad Paladugu | 0703cc5 | 2018-04-12 12:22:17 +0200 | [diff] [blame] | 334 | if (priv->max_speed) { |
| 335 | ret = phy_set_supported(priv->phydev, priv->max_speed); |
| 336 | if (ret) |
| 337 | return ret; |
| 338 | } |
| 339 | |
Siva Durga Prasad Paladugu | 1220350 | 2019-03-27 17:39:59 +0530 | [diff] [blame] | 340 | priv->phydev->supported &= supported | ADVERTISED_Pause | |
| 341 | ADVERTISED_Asym_Pause; |
| 342 | |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 343 | priv->phydev->advertising = priv->phydev->supported; |
Ashok Reddy Soma | bea12f4 | 2022-01-14 13:08:07 +0100 | [diff] [blame] | 344 | if (!ofnode_valid(priv->phydev->node)) |
| 345 | priv->phydev->node = priv->phy_of_node; |
Dan Murphy | a582871 | 2016-05-02 15:45:57 -0500 | [diff] [blame] | 346 | |
Michal Simek | 24ce232 | 2016-05-18 14:37:23 +0200 | [diff] [blame] | 347 | return phy_config(priv->phydev); |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 348 | } |
| 349 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 350 | static int zynq_gem_init(struct udevice *dev) |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 351 | { |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 352 | u32 i, nwconfig; |
Michal Simek | dbc0cfc | 2016-05-18 12:37:22 +0200 | [diff] [blame] | 353 | int ret; |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 354 | unsigned long clk_rate = 0; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 355 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 356 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 357 | struct zynq_gem_regs *regs_mdio = priv->mdiobase; |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 358 | struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; |
| 359 | struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; |
| 360 | |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 361 | if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B) |
| 362 | priv->dma_64bit = true; |
| 363 | else |
| 364 | priv->dma_64bit = false; |
| 365 | |
| 366 | #if defined(CONFIG_PHYS_64BIT) |
| 367 | if (!priv->dma_64bit) { |
| 368 | printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n", |
| 369 | __func__); |
| 370 | return -EINVAL; |
| 371 | } |
| 372 | #else |
| 373 | if (priv->dma_64bit) |
| 374 | debug("WARN: %s: Not using 64-bit dma even HW supports it\n", |
| 375 | __func__); |
| 376 | #endif |
| 377 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 378 | if (!priv->init) { |
| 379 | /* Disable all interrupts */ |
| 380 | writel(0xFFFFFFFF, ®s->idr); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 381 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 382 | /* Disable the receiver & transmitter */ |
| 383 | writel(0, ®s->nwctrl); |
| 384 | writel(0, ®s->txsr); |
| 385 | writel(0, ®s->rxsr); |
| 386 | writel(0, ®s->phymntnc); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 387 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 388 | /* Clear the Hash registers for the mac address |
| 389 | * pointed by AddressPtr |
| 390 | */ |
| 391 | writel(0x0, ®s->hashl); |
| 392 | /* Write bits [63:32] in TOP */ |
| 393 | writel(0x0, ®s->hashh); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 394 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 395 | /* Clear all counters */ |
Michal Simek | ff5dbef | 2015-10-05 12:49:48 +0200 | [diff] [blame] | 396 | for (i = 0; i < STAT_SIZE; i++) |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 397 | readl(®s->stat[i]); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 398 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 399 | /* Setup RxBD space */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 400 | memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 401 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 402 | for (i = 0; i < RX_BUF; i++) { |
| 403 | priv->rx_bd[i].status = 0xF0000000; |
| 404 | priv->rx_bd[i].addr = |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 405 | (lower_32_bits((ulong)(priv->rxbuffers) |
| 406 | + (i * PKTSIZE_ALIGN))); |
| 407 | #if defined(CONFIG_PHYS_64BIT) |
| 408 | priv->rx_bd[i].addr_hi = |
| 409 | (upper_32_bits((ulong)(priv->rxbuffers) |
| 410 | + (i * PKTSIZE_ALIGN))); |
| 411 | #endif |
| 412 | } |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 413 | /* WRAP bit to last BD */ |
| 414 | priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; |
| 415 | /* Write RxBDs to IP */ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 416 | writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase); |
| 417 | #if defined(CONFIG_PHYS_64BIT) |
| 418 | writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase); |
| 419 | #endif |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 420 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 421 | /* Setup for DMA Configuration register */ |
| 422 | writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 423 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 424 | /* Setup for Network Control register, MDIO, Rx and Tx enable */ |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 425 | setbits_le32(®s_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 426 | |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 427 | /* Disable the second priority queue */ |
| 428 | dummy_tx_bd->addr = 0; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 429 | #if defined(CONFIG_PHYS_64BIT) |
| 430 | dummy_tx_bd->addr_hi = 0; |
| 431 | #endif |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 432 | dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | |
| 433 | ZYNQ_GEM_TXBUF_LAST_MASK| |
| 434 | ZYNQ_GEM_TXBUF_USED_MASK; |
| 435 | |
| 436 | dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | |
| 437 | ZYNQ_GEM_RXBUF_NEW_MASK; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 438 | #if defined(CONFIG_PHYS_64BIT) |
| 439 | dummy_rx_bd->addr_hi = 0; |
| 440 | #endif |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 441 | dummy_rx_bd->status = 0; |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 442 | |
| 443 | writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); |
| 444 | writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); |
| 445 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 446 | priv->init++; |
| 447 | } |
| 448 | |
Michal Simek | dbc0cfc | 2016-05-18 12:37:22 +0200 | [diff] [blame] | 449 | ret = phy_startup(priv->phydev); |
| 450 | if (ret) |
| 451 | return ret; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 452 | |
Michal Simek | 43b3832 | 2015-11-30 13:44:49 +0100 | [diff] [blame] | 453 | if (!priv->phydev->link) { |
| 454 | printf("%s: No link.\n", priv->phydev->dev->name); |
Michal Simek | 216b96d | 2013-11-12 14:25:29 +0100 | [diff] [blame] | 455 | return -1; |
| 456 | } |
| 457 | |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 458 | nwconfig = ZYNQ_GEM_NWCFG_INIT; |
| 459 | |
Siva Durga Prasad Paladugu | 134cfa6 | 2017-11-23 12:56:55 +0530 | [diff] [blame] | 460 | /* |
| 461 | * Set SGMII enable PCS selection only if internal PCS/PMA |
| 462 | * core is used and interface is SGMII. |
| 463 | */ |
| 464 | if (priv->interface == PHY_INTERFACE_MODE_SGMII && |
| 465 | priv->int_pcs) { |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 466 | nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | |
| 467 | ZYNQ_GEM_NWCFG_PCS_SEL; |
Siva Durga Prasad Paladugu | 4546700 | 2016-03-25 12:53:44 +0530 | [diff] [blame] | 468 | } |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 469 | |
Michal Simek | 43b3832 | 2015-11-30 13:44:49 +0100 | [diff] [blame] | 470 | switch (priv->phydev->speed) { |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 471 | case SPEED_1000: |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 472 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 473 | ®s->nwcfg); |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 474 | clk_rate = ZYNQ_GEM_FREQUENCY_1000; |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 475 | break; |
| 476 | case SPEED_100: |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 477 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, |
Michal Simek | 6429595 | 2015-09-08 16:55:42 +0200 | [diff] [blame] | 478 | ®s->nwcfg); |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 479 | clk_rate = ZYNQ_GEM_FREQUENCY_100; |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 480 | break; |
| 481 | case SPEED_10: |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 482 | clk_rate = ZYNQ_GEM_FREQUENCY_10; |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 483 | break; |
| 484 | } |
Robert Hancock | 3d6a9e0 | 2021-03-11 16:55:50 -0600 | [diff] [blame] | 485 | |
| 486 | #ifdef CONFIG_ARM64 |
| 487 | if (priv->interface == PHY_INTERFACE_MODE_SGMII && |
| 488 | priv->int_pcs) { |
| 489 | /* |
| 490 | * Disable AN for fixed link configuration, enable otherwise. |
| 491 | * Must be written after PCS_SEL is set in nwconfig, |
| 492 | * otherwise writes will not take effect. |
| 493 | */ |
| 494 | if (priv->phydev->phy_id != PHY_FIXED_ID) |
| 495 | writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, |
| 496 | ®s->pcscntrl); |
| 497 | else |
| 498 | writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL, |
| 499 | ®s->pcscntrl); |
| 500 | } |
| 501 | #endif |
David Andrey | 73875dc | 2013-04-05 17:24:24 +0200 | [diff] [blame] | 502 | |
Michal Simek | a170e43 | 2022-08-26 10:30:47 +0200 | [diff] [blame] | 503 | ret = clk_get_rate(&priv->tx_clk); |
| 504 | if (ret != clk_rate) { |
| 505 | ret = clk_set_rate(&priv->tx_clk, clk_rate); |
| 506 | if (IS_ERR_VALUE(ret)) { |
| 507 | dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate); |
| 508 | return ret; |
| 509 | } |
Stefan Herbrechtsmeier | bb43397 | 2017-01-17 16:27:25 +0100 | [diff] [blame] | 510 | } |
| 511 | |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 512 | ret = clk_enable(&priv->tx_clk); |
Michal Simek | 4171095 | 2021-02-09 15:28:15 +0100 | [diff] [blame] | 513 | if (ret) { |
Stefan Herbrechtsmeier | bb43397 | 2017-01-17 16:27:25 +0100 | [diff] [blame] | 514 | dev_err(dev, "failed to enable tx clock\n"); |
| 515 | return ret; |
| 516 | } |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 517 | |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 518 | if (priv->clk_en_info & RXCLK_EN) { |
| 519 | ret = clk_enable(&priv->rx_clk); |
| 520 | if (ret) { |
| 521 | dev_err(dev, "failed to enable rx clock\n"); |
| 522 | return ret; |
| 523 | } |
| 524 | } |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 525 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
| 526 | ZYNQ_GEM_NWCTRL_TXEN_MASK); |
| 527 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 528 | return 0; |
| 529 | } |
| 530 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 531 | static int zynq_gem_send(struct udevice *dev, void *ptr, int len) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 532 | { |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 533 | dma_addr_t addr; |
| 534 | u32 size; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 535 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 536 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 537 | struct emac_bd *current_bd = &priv->tx_bd[1]; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 538 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 539 | /* Setup Tx BD */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 540 | memset(priv->tx_bd, 0, sizeof(struct emac_bd)); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 541 | |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 542 | priv->tx_bd->addr = lower_32_bits((ulong)ptr); |
| 543 | #if defined(CONFIG_PHYS_64BIT) |
| 544 | priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr); |
| 545 | #endif |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 546 | priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 547 | ZYNQ_GEM_TXBUF_LAST_MASK; |
| 548 | /* Dummy descriptor to mark it as the last in descriptor chain */ |
| 549 | current_bd->addr = 0x0; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 550 | #if defined(CONFIG_PHYS_64BIT) |
| 551 | current_bd->addr_hi = 0x0; |
| 552 | #endif |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 553 | current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | |
| 554 | ZYNQ_GEM_TXBUF_LAST_MASK| |
| 555 | ZYNQ_GEM_TXBUF_USED_MASK; |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 556 | |
Michal Simek | b6fe7ad | 2015-08-17 09:50:09 +0200 | [diff] [blame] | 557 | /* setup BD */ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 558 | writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase); |
| 559 | #if defined(CONFIG_PHYS_64BIT) |
| 560 | writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase); |
| 561 | #endif |
Michal Simek | b6fe7ad | 2015-08-17 09:50:09 +0200 | [diff] [blame] | 562 | |
Prabhakar Kushwaha | 1e9e619 | 2015-10-25 13:18:54 +0530 | [diff] [blame] | 563 | addr = (ulong) ptr; |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 564 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
| 565 | size = roundup(len, ARCH_DMA_MINALIGN); |
| 566 | flush_dcache_range(addr, addr + size); |
| 567 | barrier(); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 568 | |
| 569 | /* Start transmit */ |
| 570 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); |
| 571 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 572 | /* Read TX BD status */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 573 | if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) |
| 574 | printf("TX buffers exhausted in mid frame\n"); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 575 | |
Ălvaro FernĂĄndez Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 576 | return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, |
| 577 | true, 20000, true); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 581 | static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 582 | { |
| 583 | int frame_len; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 584 | dma_addr_t addr; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 585 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 586 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 587 | |
| 588 | if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 589 | return -1; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 590 | |
| 591 | if (!(current_bd->status & |
| 592 | (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { |
| 593 | printf("GEM: SOF or EOF not set for last buffer received!\n"); |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 594 | return -1; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 595 | } |
| 596 | |
| 597 | frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 598 | if (!frame_len) { |
| 599 | printf("%s: Zero size packet?\n", __func__); |
| 600 | return -1; |
| 601 | } |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 602 | |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 603 | #if defined(CONFIG_PHYS_64BIT) |
| 604 | addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) |
| 605 | | ((dma_addr_t)current_bd->addr_hi << 32)); |
| 606 | #else |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 607 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 608 | #endif |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 609 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 610 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 611 | *packetp = (uchar *)(uintptr_t)addr; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 612 | |
Stefan Theil | 0f407c9 | 2018-12-17 09:12:30 +0100 | [diff] [blame] | 613 | invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); |
| 614 | barrier(); |
| 615 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 616 | return frame_len; |
| 617 | } |
| 618 | |
| 619 | static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) |
| 620 | { |
| 621 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 622 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
| 623 | struct emac_bd *first_bd; |
Ashok Reddy Soma | 4757253 | 2020-02-23 08:01:29 -0700 | [diff] [blame] | 624 | dma_addr_t addr; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 625 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 626 | if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { |
| 627 | priv->rx_first_buf = priv->rxbd_current; |
| 628 | } else { |
| 629 | current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; |
| 630 | current_bd->status = 0xF0000000; /* FIXME */ |
| 631 | } |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 632 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 633 | if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { |
| 634 | first_bd = &priv->rx_bd[priv->rx_first_buf]; |
| 635 | first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; |
| 636 | first_bd->status = 0xF0000000; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 637 | } |
| 638 | |
Ashok Reddy Soma | 4757253 | 2020-02-23 08:01:29 -0700 | [diff] [blame] | 639 | /* Flush the cache for the packet as well */ |
| 640 | #if defined(CONFIG_PHYS_64BIT) |
| 641 | addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) |
| 642 | | ((dma_addr_t)current_bd->addr_hi << 32)); |
| 643 | #else |
| 644 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
| 645 | #endif |
| 646 | flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, |
| 647 | ARCH_DMA_MINALIGN)); |
| 648 | barrier(); |
| 649 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 650 | if ((++priv->rxbd_current) >= RX_BUF) |
| 651 | priv->rxbd_current = 0; |
| 652 | |
Michal Simek | 139f410 | 2015-12-09 14:16:32 +0100 | [diff] [blame] | 653 | return 0; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 654 | } |
| 655 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 656 | static void zynq_gem_halt(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 657 | { |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 658 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 659 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 660 | |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 661 | clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
| 662 | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 663 | } |
| 664 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 665 | static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, |
| 666 | int devad, int reg) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 667 | { |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 668 | struct zynq_gem_priv *priv = bus->priv; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 669 | int ret; |
Michal Simek | d061bfd | 2018-06-14 09:08:44 +0200 | [diff] [blame] | 670 | u16 val = 0; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 671 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 672 | ret = phyread(priv, addr, reg, &val); |
| 673 | debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); |
| 674 | return val; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 675 | } |
| 676 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 677 | static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, |
| 678 | int reg, u16 value) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 679 | { |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 680 | struct zynq_gem_priv *priv = bus->priv; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 681 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 682 | debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); |
| 683 | return phywrite(priv, addr, reg, value); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 684 | } |
| 685 | |
Michal Simek | c86e7fc | 2021-12-06 16:25:20 +0100 | [diff] [blame] | 686 | static int zynq_gem_reset_init(struct udevice *dev) |
| 687 | { |
| 688 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 689 | int ret; |
| 690 | |
| 691 | ret = reset_get_bulk(dev, &priv->resets); |
| 692 | if (ret == -ENOTSUPP || ret == -ENOENT) |
| 693 | return 0; |
| 694 | else if (ret) |
| 695 | return ret; |
| 696 | |
| 697 | ret = reset_deassert_bulk(&priv->resets); |
| 698 | if (ret) { |
| 699 | reset_release_bulk(&priv->resets); |
| 700 | return ret; |
| 701 | } |
| 702 | |
| 703 | return 0; |
| 704 | } |
| 705 | |
T Karthik Reddy | 4a0e6b5 | 2022-03-30 11:07:58 +0200 | [diff] [blame] | 706 | static int gem_zynqmp_set_dynamic_config(struct udevice *dev) |
| 707 | { |
| 708 | u32 pm_info[2]; |
| 709 | int ret; |
| 710 | |
| 711 | if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) { |
| 712 | if (!zynqmp_pm_is_function_supported(PM_IOCTL, |
| 713 | IOCTL_SET_GEM_CONFIG)) { |
| 714 | ret = ofnode_read_u32_array(dev_ofnode(dev), |
| 715 | "power-domains", |
| 716 | pm_info, |
| 717 | ARRAY_SIZE(pm_info)); |
| 718 | if (ret) { |
| 719 | dev_err(dev, |
| 720 | "Failed to read power-domains info\n"); |
| 721 | return ret; |
| 722 | } |
| 723 | |
| 724 | ret = zynqmp_pm_set_gem_config(pm_info[1], |
| 725 | GEM_CONFIG_FIXED, 0); |
| 726 | if (ret) |
| 727 | return ret; |
| 728 | |
| 729 | ret = zynqmp_pm_set_gem_config(pm_info[1], |
| 730 | GEM_CONFIG_SGMII_MODE, |
| 731 | 1); |
| 732 | if (ret) |
| 733 | return ret; |
| 734 | } |
| 735 | } |
| 736 | |
| 737 | return 0; |
| 738 | } |
| 739 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 740 | static int zynq_gem_probe(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 741 | { |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 742 | void *bd_space; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 743 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 744 | int ret; |
Michal Simek | c8142d4 | 2021-12-15 11:00:01 +0100 | [diff] [blame] | 745 | struct phy phy; |
| 746 | |
| 747 | if (priv->interface == PHY_INTERFACE_MODE_SGMII) { |
| 748 | ret = generic_phy_get_by_index(dev, 0, &phy); |
| 749 | if (!ret) { |
| 750 | ret = generic_phy_init(&phy); |
| 751 | if (ret) |
| 752 | return ret; |
| 753 | } else if (ret != -ENOENT) { |
| 754 | debug("could not get phy (err %d)\n", ret); |
| 755 | return ret; |
| 756 | } |
| 757 | } |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 758 | |
Michal Simek | c86e7fc | 2021-12-06 16:25:20 +0100 | [diff] [blame] | 759 | ret = zynq_gem_reset_init(dev); |
| 760 | if (ret) |
| 761 | return ret; |
| 762 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 763 | /* Align rxbuffers to ARCH_DMA_MINALIGN */ |
| 764 | priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); |
Michal Simek | c8959f4 | 2018-06-13 15:20:35 +0200 | [diff] [blame] | 765 | if (!priv->rxbuffers) |
| 766 | return -ENOMEM; |
| 767 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 768 | memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); |
T Karthik Reddy | 60bf216 | 2020-01-15 02:15:13 -0700 | [diff] [blame] | 769 | ulong addr = (ulong)priv->rxbuffers; |
Stefan Theil | 0f407c9 | 2018-12-17 09:12:30 +0100 | [diff] [blame] | 770 | flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); |
| 771 | barrier(); |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 772 | |
Siva Durga Prasad Paladugu | 2b0690e | 2014-12-06 12:57:53 +0530 | [diff] [blame] | 773 | /* Align bd_space to MMU_SECTION_SHIFT */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 774 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 775 | if (!bd_space) { |
| 776 | ret = -ENOMEM; |
| 777 | goto err1; |
| 778 | } |
Michal Simek | c8959f4 | 2018-06-13 15:20:35 +0200 | [diff] [blame] | 779 | |
Michal Simek | 0afb6b2 | 2015-04-15 13:31:28 +0200 | [diff] [blame] | 780 | mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, |
| 781 | BD_SPACE, DCACHE_OFF); |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 782 | |
| 783 | /* Initialize the bd spaces for tx and rx bd's */ |
| 784 | priv->tx_bd = (struct emac_bd *)bd_space; |
Prabhakar Kushwaha | 1e9e619 | 2015-10-25 13:18:54 +0530 | [diff] [blame] | 785 | priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 786 | |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 787 | ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk); |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 788 | if (ret < 0) { |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 789 | dev_err(dev, "failed to get tx_clock\n"); |
Michal Simek | 179f7d7 | 2021-02-11 19:03:30 +0100 | [diff] [blame] | 790 | goto err2; |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 791 | } |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 792 | |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 793 | if (priv->clk_en_info & RXCLK_EN) { |
| 794 | ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk); |
| 795 | if (ret < 0) { |
| 796 | dev_err(dev, "failed to get rx_clock\n"); |
Michal Simek | 179f7d7 | 2021-02-11 19:03:30 +0100 | [diff] [blame] | 797 | goto err2; |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 798 | } |
| 799 | } |
| 800 | |
Michal Simek | b001798 | 2022-03-30 11:07:53 +0200 | [diff] [blame] | 801 | if (IS_ENABLED(CONFIG_DM_ETH_PHY)) |
| 802 | priv->bus = eth_phy_get_mdio_bus(dev); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 803 | |
Michal Simek | b001798 | 2022-03-30 11:07:53 +0200 | [diff] [blame] | 804 | if (!priv->bus) { |
| 805 | priv->bus = mdio_alloc(); |
| 806 | priv->bus->read = zynq_gem_miiphy_read; |
| 807 | priv->bus->write = zynq_gem_miiphy_write; |
| 808 | priv->bus->priv = priv; |
| 809 | |
| 810 | ret = mdio_register_seq(priv->bus, dev_seq(dev)); |
| 811 | if (ret) |
| 812 | goto err2; |
| 813 | } |
| 814 | |
| 815 | if (IS_ENABLED(CONFIG_DM_ETH_PHY)) |
| 816 | eth_phy_set_mdio_bus(dev, priv->bus); |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 817 | |
| 818 | ret = zynq_phy_init(dev); |
| 819 | if (ret) |
Michael Walle | 465437c | 2021-02-10 22:41:57 +0100 | [diff] [blame] | 820 | goto err3; |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 821 | |
Michal Simek | c8142d4 | 2021-12-15 11:00:01 +0100 | [diff] [blame] | 822 | if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) { |
T Karthik Reddy | 4a0e6b5 | 2022-03-30 11:07:58 +0200 | [diff] [blame] | 823 | if (IS_ENABLED(CONFIG_DM_ETH_PHY)) { |
| 824 | if (device_is_compatible(dev, "cdns,zynqmp-gem")) { |
| 825 | ret = gem_zynqmp_set_dynamic_config(dev); |
| 826 | if (ret) { |
| 827 | dev_err |
| 828 | (dev, |
| 829 | "Failed to set gem dynamic config\n"); |
| 830 | return ret; |
| 831 | } |
| 832 | } |
| 833 | } |
Michal Simek | c8142d4 | 2021-12-15 11:00:01 +0100 | [diff] [blame] | 834 | ret = generic_phy_power_on(&phy); |
| 835 | if (ret) |
| 836 | return ret; |
| 837 | } |
| 838 | |
T Karthik Reddy | 297521e | 2022-03-30 11:07:55 +0200 | [diff] [blame] | 839 | printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n", |
| 840 | (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phydev->addr, |
| 841 | phy_string_for_interface(priv->interface)); |
| 842 | |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 843 | return ret; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 844 | |
Michael Walle | 465437c | 2021-02-10 22:41:57 +0100 | [diff] [blame] | 845 | err3: |
| 846 | mdio_unregister(priv->bus); |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 847 | err2: |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 848 | free(priv->tx_bd); |
Michal Simek | 179f7d7 | 2021-02-11 19:03:30 +0100 | [diff] [blame] | 849 | err1: |
| 850 | free(priv->rxbuffers); |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 851 | return ret; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 852 | } |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 853 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 854 | static int zynq_gem_remove(struct udevice *dev) |
| 855 | { |
| 856 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 857 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 858 | free(priv->phydev); |
| 859 | mdio_unregister(priv->bus); |
| 860 | mdio_free(priv->bus); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 861 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 862 | return 0; |
| 863 | } |
| 864 | |
| 865 | static const struct eth_ops zynq_gem_ops = { |
| 866 | .start = zynq_gem_init, |
| 867 | .send = zynq_gem_send, |
| 868 | .recv = zynq_gem_recv, |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 869 | .free_pkt = zynq_gem_free_pkt, |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 870 | .stop = zynq_gem_halt, |
| 871 | .write_hwaddr = zynq_gem_setup_mac, |
| 872 | }; |
Michal Simek | e9ecc1c | 2015-11-30 13:58:36 +0100 | [diff] [blame] | 873 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 874 | static int zynq_gem_of_to_plat(struct udevice *dev) |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 875 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 876 | struct eth_pdata *pdata = dev_get_plat(dev); |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 877 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 878 | struct ofnode_phandle_args phandle_args; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 879 | |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 880 | pdata->iobase = (phys_addr_t)dev_read_addr(dev); |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 881 | priv->iobase = (struct zynq_gem_regs *)pdata->iobase; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 882 | priv->mdiobase = priv->iobase; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 883 | /* Hardcode for now */ |
Michal Simek | c6aa413 | 2015-12-09 09:29:12 +0100 | [diff] [blame] | 884 | priv->phyaddr = -1; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 885 | |
Michal Simek | 8114538 | 2018-09-20 09:42:27 +0200 | [diff] [blame] | 886 | if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, |
| 887 | &phandle_args)) { |
Michal Simek | 8ec9066 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 888 | fdt_addr_t addr; |
| 889 | ofnode parent; |
| 890 | |
Michal Simek | 8114538 | 2018-09-20 09:42:27 +0200 | [diff] [blame] | 891 | debug("phy-handle does exist %s\n", dev->name); |
Michal Simek | b001798 | 2022-03-30 11:07:53 +0200 | [diff] [blame] | 892 | if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) |
| 893 | priv->phyaddr = ofnode_read_u32_default |
| 894 | (phandle_args.node, "reg", -1); |
| 895 | |
Michal Simek | 8114538 | 2018-09-20 09:42:27 +0200 | [diff] [blame] | 896 | priv->phy_of_node = phandle_args.node; |
| 897 | priv->max_speed = ofnode_read_u32_default(phandle_args.node, |
| 898 | "max-speed", |
| 899 | SPEED_1000); |
Michal Simek | 8ec9066 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 900 | |
| 901 | parent = ofnode_get_parent(phandle_args.node); |
Michal Simek | eac3c67 | 2021-12-06 14:53:17 +0100 | [diff] [blame] | 902 | if (ofnode_name_eq(parent, "mdio")) |
| 903 | parent = ofnode_get_parent(parent); |
| 904 | |
Michal Simek | 8ec9066 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 905 | addr = ofnode_get_addr(parent); |
| 906 | if (addr != FDT_ADDR_T_NONE) { |
| 907 | debug("MDIO bus not found %s\n", dev->name); |
| 908 | priv->mdiobase = (struct zynq_gem_regs *)addr; |
| 909 | } |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 910 | } |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 911 | |
Marek BehĂșn | bc19477 | 2022-04-07 00:33:01 +0200 | [diff] [blame] | 912 | pdata->phy_interface = dev_read_phy_mode(dev); |
Marek BehĂșn | 48631e4 | 2022-04-07 00:33:03 +0200 | [diff] [blame] | 913 | if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) |
Michal Simek | 3c4ce3c | 2015-11-30 14:17:50 +0100 | [diff] [blame] | 914 | return -EINVAL; |
Michal Simek | 3c4ce3c | 2015-11-30 14:17:50 +0100 | [diff] [blame] | 915 | priv->interface = pdata->phy_interface; |
| 916 | |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 917 | priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); |
Siva Durga Prasad Paladugu | 134cfa6 | 2017-11-23 12:56:55 +0530 | [diff] [blame] | 918 | |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 919 | priv->clk_en_info = dev_get_driver_data(dev); |
| 920 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 921 | return 0; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 922 | } |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 923 | |
| 924 | static const struct udevice_id zynq_gem_ids[] = { |
T Karthik Reddy | 68cd67d | 2021-02-03 03:10:48 -0700 | [diff] [blame] | 925 | { .compatible = "cdns,versal-gem", .data = RXCLK_EN }, |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 926 | { .compatible = "cdns,zynqmp-gem" }, |
| 927 | { .compatible = "cdns,zynq-gem" }, |
| 928 | { .compatible = "cdns,gem" }, |
| 929 | { } |
| 930 | }; |
| 931 | |
| 932 | U_BOOT_DRIVER(zynq_gem) = { |
| 933 | .name = "zynq_gem", |
| 934 | .id = UCLASS_ETH, |
| 935 | .of_match = zynq_gem_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 936 | .of_to_plat = zynq_gem_of_to_plat, |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 937 | .probe = zynq_gem_probe, |
| 938 | .remove = zynq_gem_remove, |
| 939 | .ops = &zynq_gem_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 940 | .priv_auto = sizeof(struct zynq_gem_priv), |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 941 | .plat_auto = sizeof(struct eth_pdata), |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 942 | }; |