| commit | 780c535e5f4e4d8faeebdf061c02743eb01bfa31 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Tue Sep 08 17:20:01 2015 +0200 |
| committer | Michal Simek <michal.simek@xilinx.com> | Wed Jan 27 15:55:54 2016 +0100 |
| tree | 6564b5c2ee3a91ef81910c3be092ab1b2119ad16 | |
| parent | f6459151c66d67c8e81796d21570ad7fdf85fdf7 [diff] |
net: zynq: Change MDC setup for arm64 MDC setting depends on pclk input clocks which varies across SoC. This driver is used by xilinx zynq and zynqmp SOC. Input clock frequence on silicon is 125MHz where divider 64 put frequency below 2.5MHz requires by spec (125/64=1.95). Signed-off-by: Michal Simek <michal.simek@xilinx.com>