Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2 | /************************************************************************** |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 3 | Intel Pro 1000 for ppcboot/das-u-boot |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4 | Drivers are port from Intel's Linux driver e1000-4.3.15 |
| 5 | and from Etherboot pro 1000 driver by mrakes at vivato dot net |
| 6 | tested on both gig copper and gig fiber boards |
| 7 | ***************************************************************************/ |
| 8 | /******************************************************************************* |
| 9 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 10 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 11 | Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 12 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 13 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 14 | Contact Information: |
| 15 | Linux NICS <linux.nics@intel.com> |
| 16 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 17 | |
| 18 | *******************************************************************************/ |
| 19 | /* |
| 20 | * Copyright (C) Archway Digital Solutions. |
| 21 | * |
| 22 | * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> |
| 23 | * 2/9/2002 |
| 24 | * |
| 25 | * Copyright (C) Linux Networx. |
| 26 | * Massive upgrade to work with the new intel gigabit NICs. |
| 27 | * <ebiederman at lnxi dot com> |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 28 | * |
| 29 | * Copyright 2011 Freescale Semiconductor, Inc. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
Simon Glass | cece904 | 2015-08-19 09:33:38 -0600 | [diff] [blame] | 32 | #include <common.h> |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 33 | #include <command.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 34 | #include <cpu_func.h> |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 35 | #include <dm.h> |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 36 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 37 | #include <log.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 38 | #include <malloc.h> |
Simon Glass | 2dd337a | 2015-09-02 17:24:58 -0600 | [diff] [blame] | 39 | #include <memalign.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 40 | #include <net.h> |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 41 | #include <pci.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 42 | #include <linux/delay.h> |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 43 | #include "e1000.h" |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 44 | #include <asm/cache.h> |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 45 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 46 | #define TOUT_LOOP 100000 |
| 47 | |
Roy Zang | 966172e | 2009-08-22 03:49:52 +0800 | [diff] [blame] | 48 | #define E1000_DEFAULT_PCI_PBA 0x00000030 |
| 49 | #define E1000_DEFAULT_PCIE_PBA 0x000a0026 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 50 | |
| 51 | /* NIC specific static variables go here */ |
| 52 | |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 53 | /* Intel i210 needs the DMA descriptor rings aligned to 128b */ |
| 54 | #define E1000_BUFFER_ALIGN 128 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 55 | |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 56 | /* |
| 57 | * TODO(sjg@chromium.org): Even with driver model we share these buffers. |
| 58 | * Concurrent receiving on multiple active Ethernet devices will not work. |
| 59 | * Normally U-Boot does not support this anyway. To fix it in this driver, |
| 60 | * move these buffers and the tx/rx pointers to struct e1000_hw. |
| 61 | */ |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 62 | DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); |
| 63 | DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); |
| 64 | DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 65 | |
| 66 | static int tx_tail; |
| 67 | static int rx_tail, rx_last; |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 68 | static int num_cards; /* Number of E1000 devices seen so far */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 69 | |
Kyle Moffett | 7b698d5 | 2011-10-18 11:05:26 +0000 | [diff] [blame] | 70 | static struct pci_device_id e1000_supported[] = { |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 71 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, |
| 72 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, |
| 73 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, |
| 74 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, |
| 75 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, |
| 76 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, |
| 77 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, |
| 78 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, |
| 79 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, |
| 80 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, |
| 81 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, |
| 82 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, |
| 83 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, |
| 84 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, |
| 85 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, |
| 86 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, |
| 87 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 88 | /* E1000 PCIe card */ |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 89 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, |
| 90 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, |
| 91 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, |
| 92 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, |
| 93 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, |
| 94 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, |
| 95 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, |
| 96 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, |
| 97 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, |
| 98 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, |
| 99 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, |
| 100 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, |
| 101 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, |
| 102 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, |
| 103 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, |
| 104 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, |
| 105 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, |
| 106 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, |
| 107 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, |
| 108 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, |
| 109 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, |
| 110 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, |
| 111 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, |
| 112 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, |
| 113 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, |
| 114 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, |
| 115 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, |
| 116 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, |
| 117 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, |
| 118 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 119 | |
Stefan Althoefer | bc6d2fc | 2008-12-20 19:40:41 +0100 | [diff] [blame] | 120 | {} |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 121 | }; |
| 122 | |
| 123 | /* Function forward declarations */ |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 124 | static int e1000_setup_link(struct e1000_hw *hw); |
| 125 | static int e1000_setup_fiber_link(struct e1000_hw *hw); |
| 126 | static int e1000_setup_copper_link(struct e1000_hw *hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 127 | static int e1000_phy_setup_autoneg(struct e1000_hw *hw); |
| 128 | static void e1000_config_collision_dist(struct e1000_hw *hw); |
| 129 | static int e1000_config_mac_to_phy(struct e1000_hw *hw); |
| 130 | static int e1000_config_fc_after_link_up(struct e1000_hw *hw); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 131 | static int e1000_check_for_link(struct e1000_hw *hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 132 | static int e1000_wait_autoneg(struct e1000_hw *hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 133 | static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 134 | uint16_t * duplex); |
| 135 | static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, |
| 136 | uint16_t * phy_data); |
| 137 | static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, |
| 138 | uint16_t phy_data); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 139 | static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 140 | static int e1000_phy_reset(struct e1000_hw *hw); |
| 141 | static int e1000_detect_gig_phy(struct e1000_hw *hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 142 | static void e1000_set_media_type(struct e1000_hw *hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 143 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 144 | static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); |
Tim Harvey | 5cb59ec | 2015-05-19 10:01:18 -0700 | [diff] [blame] | 145 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 146 | static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 147 | |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 148 | #ifndef CONFIG_E1000_NO_NVM |
| 149 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); |
Hannu Lounento | c56999e | 2018-01-10 20:31:24 +0100 | [diff] [blame] | 150 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); |
Roy Zang | 9b7c430 | 2009-08-11 03:48:05 +0800 | [diff] [blame] | 151 | static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, |
| 152 | uint16_t words, |
| 153 | uint16_t *data); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 154 | /****************************************************************************** |
| 155 | * Raises the EEPROM's clock input. |
| 156 | * |
| 157 | * hw - Struct containing variables accessed by shared code |
| 158 | * eecd - EECD's current value |
| 159 | *****************************************************************************/ |
Kyle Moffett | 142cbf8 | 2011-10-18 11:05:28 +0000 | [diff] [blame] | 160 | void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 161 | { |
| 162 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
| 163 | * wait 50 microseconds. |
| 164 | */ |
| 165 | *eecd = *eecd | E1000_EECD_SK; |
| 166 | E1000_WRITE_REG(hw, EECD, *eecd); |
| 167 | E1000_WRITE_FLUSH(hw); |
| 168 | udelay(50); |
| 169 | } |
| 170 | |
| 171 | /****************************************************************************** |
| 172 | * Lowers the EEPROM's clock input. |
| 173 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 174 | * hw - Struct containing variables accessed by shared code |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 175 | * eecd - EECD's current value |
| 176 | *****************************************************************************/ |
Kyle Moffett | 142cbf8 | 2011-10-18 11:05:28 +0000 | [diff] [blame] | 177 | void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 178 | { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 179 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
| 180 | * wait 50 microseconds. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 181 | */ |
| 182 | *eecd = *eecd & ~E1000_EECD_SK; |
| 183 | E1000_WRITE_REG(hw, EECD, *eecd); |
| 184 | E1000_WRITE_FLUSH(hw); |
| 185 | udelay(50); |
| 186 | } |
| 187 | |
| 188 | /****************************************************************************** |
| 189 | * Shift data bits out to the EEPROM. |
| 190 | * |
| 191 | * hw - Struct containing variables accessed by shared code |
| 192 | * data - data to send to the EEPROM |
| 193 | * count - number of bits to shift out |
| 194 | *****************************************************************************/ |
| 195 | static void |
| 196 | e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) |
| 197 | { |
| 198 | uint32_t eecd; |
| 199 | uint32_t mask; |
| 200 | |
| 201 | /* We need to shift "count" bits out to the EEPROM. So, value in the |
| 202 | * "data" parameter will be shifted out to the EEPROM one bit at a time. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 203 | * In order to do this, "data" must be broken down into bits. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 204 | */ |
| 205 | mask = 0x01 << (count - 1); |
| 206 | eecd = E1000_READ_REG(hw, EECD); |
| 207 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
| 208 | do { |
| 209 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
| 210 | * and then raising and then lowering the clock (the SK bit controls |
| 211 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
| 212 | * by setting "DI" to "0" and then raising and then lowering the clock. |
| 213 | */ |
| 214 | eecd &= ~E1000_EECD_DI; |
| 215 | |
| 216 | if (data & mask) |
| 217 | eecd |= E1000_EECD_DI; |
| 218 | |
| 219 | E1000_WRITE_REG(hw, EECD, eecd); |
| 220 | E1000_WRITE_FLUSH(hw); |
| 221 | |
| 222 | udelay(50); |
| 223 | |
| 224 | e1000_raise_ee_clk(hw, &eecd); |
| 225 | e1000_lower_ee_clk(hw, &eecd); |
| 226 | |
| 227 | mask = mask >> 1; |
| 228 | |
| 229 | } while (mask); |
| 230 | |
| 231 | /* We leave the "DI" bit set to "0" when we leave this routine. */ |
| 232 | eecd &= ~E1000_EECD_DI; |
| 233 | E1000_WRITE_REG(hw, EECD, eecd); |
| 234 | } |
| 235 | |
| 236 | /****************************************************************************** |
| 237 | * Shift data bits in from the EEPROM |
| 238 | * |
| 239 | * hw - Struct containing variables accessed by shared code |
| 240 | *****************************************************************************/ |
| 241 | static uint16_t |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 242 | e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 243 | { |
| 244 | uint32_t eecd; |
| 245 | uint32_t i; |
| 246 | uint16_t data; |
| 247 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 248 | /* In order to read a register from the EEPROM, we need to shift 'count' |
| 249 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
| 250 | * input to the EEPROM (setting the SK bit), and then reading the |
| 251 | * value of the "DO" bit. During this "shifting in" process the |
| 252 | * "DI" bit should always be clear. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 253 | */ |
| 254 | |
| 255 | eecd = E1000_READ_REG(hw, EECD); |
| 256 | |
| 257 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
| 258 | data = 0; |
| 259 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 260 | for (i = 0; i < count; i++) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 261 | data = data << 1; |
| 262 | e1000_raise_ee_clk(hw, &eecd); |
| 263 | |
| 264 | eecd = E1000_READ_REG(hw, EECD); |
| 265 | |
| 266 | eecd &= ~(E1000_EECD_DI); |
| 267 | if (eecd & E1000_EECD_DO) |
| 268 | data |= 1; |
| 269 | |
| 270 | e1000_lower_ee_clk(hw, &eecd); |
| 271 | } |
| 272 | |
| 273 | return data; |
| 274 | } |
| 275 | |
| 276 | /****************************************************************************** |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 277 | * Returns EEPROM to a "standby" state |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 278 | * |
| 279 | * hw - Struct containing variables accessed by shared code |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 280 | *****************************************************************************/ |
Kyle Moffett | 142cbf8 | 2011-10-18 11:05:28 +0000 | [diff] [blame] | 281 | void e1000_standby_eeprom(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 282 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 283 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 284 | uint32_t eecd; |
| 285 | |
| 286 | eecd = E1000_READ_REG(hw, EECD); |
| 287 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 288 | if (eeprom->type == e1000_eeprom_microwire) { |
| 289 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
| 290 | E1000_WRITE_REG(hw, EECD, eecd); |
| 291 | E1000_WRITE_FLUSH(hw); |
| 292 | udelay(eeprom->delay_usec); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 293 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 294 | /* Clock high */ |
| 295 | eecd |= E1000_EECD_SK; |
| 296 | E1000_WRITE_REG(hw, EECD, eecd); |
| 297 | E1000_WRITE_FLUSH(hw); |
| 298 | udelay(eeprom->delay_usec); |
| 299 | |
| 300 | /* Select EEPROM */ |
| 301 | eecd |= E1000_EECD_CS; |
| 302 | E1000_WRITE_REG(hw, EECD, eecd); |
| 303 | E1000_WRITE_FLUSH(hw); |
| 304 | udelay(eeprom->delay_usec); |
| 305 | |
| 306 | /* Clock low */ |
| 307 | eecd &= ~E1000_EECD_SK; |
| 308 | E1000_WRITE_REG(hw, EECD, eecd); |
| 309 | E1000_WRITE_FLUSH(hw); |
| 310 | udelay(eeprom->delay_usec); |
| 311 | } else if (eeprom->type == e1000_eeprom_spi) { |
| 312 | /* Toggle CS to flush commands */ |
| 313 | eecd |= E1000_EECD_CS; |
| 314 | E1000_WRITE_REG(hw, EECD, eecd); |
| 315 | E1000_WRITE_FLUSH(hw); |
| 316 | udelay(eeprom->delay_usec); |
| 317 | eecd &= ~E1000_EECD_CS; |
| 318 | E1000_WRITE_REG(hw, EECD, eecd); |
| 319 | E1000_WRITE_FLUSH(hw); |
| 320 | udelay(eeprom->delay_usec); |
| 321 | } |
| 322 | } |
| 323 | |
| 324 | /*************************************************************************** |
| 325 | * Description: Determines if the onboard NVM is FLASH or EEPROM. |
| 326 | * |
| 327 | * hw - Struct containing variables accessed by shared code |
| 328 | ****************************************************************************/ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 329 | static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 330 | { |
| 331 | uint32_t eecd = 0; |
| 332 | |
| 333 | DEBUGFUNC(); |
| 334 | |
| 335 | if (hw->mac_type == e1000_ich8lan) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 336 | return false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 337 | |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 338 | if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 339 | eecd = E1000_READ_REG(hw, EECD); |
| 340 | |
| 341 | /* Isolate bits 15 & 16 */ |
| 342 | eecd = ((eecd >> 15) & 0x03); |
| 343 | |
| 344 | /* If both bits are set, device is Flash type */ |
| 345 | if (eecd == 0x03) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 346 | return false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 347 | } |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 348 | return true; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | /****************************************************************************** |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 352 | * Prepares EEPROM for access |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 353 | * |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 354 | * hw - Struct containing variables accessed by shared code |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 355 | * |
| 356 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
| 357 | * function should be called before issuing a command to the EEPROM. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 358 | *****************************************************************************/ |
Kyle Moffett | 142cbf8 | 2011-10-18 11:05:28 +0000 | [diff] [blame] | 359 | int32_t e1000_acquire_eeprom(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 360 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 361 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 362 | uint32_t eecd, i = 0; |
| 363 | |
Timur Tabi | edc45b5 | 2009-08-17 15:55:38 -0500 | [diff] [blame] | 364 | DEBUGFUNC(); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 365 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 366 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
| 367 | return -E1000_ERR_SWFW_SYNC; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 368 | eecd = E1000_READ_REG(hw, EECD); |
| 369 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 370 | if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 371 | /* Request EEPROM Access */ |
| 372 | if (hw->mac_type > e1000_82544) { |
| 373 | eecd |= E1000_EECD_REQ; |
| 374 | E1000_WRITE_REG(hw, EECD, eecd); |
| 375 | eecd = E1000_READ_REG(hw, EECD); |
| 376 | while ((!(eecd & E1000_EECD_GNT)) && |
| 377 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
| 378 | i++; |
| 379 | udelay(5); |
| 380 | eecd = E1000_READ_REG(hw, EECD); |
| 381 | } |
| 382 | if (!(eecd & E1000_EECD_GNT)) { |
| 383 | eecd &= ~E1000_EECD_REQ; |
| 384 | E1000_WRITE_REG(hw, EECD, eecd); |
| 385 | DEBUGOUT("Could not acquire EEPROM grant\n"); |
| 386 | return -E1000_ERR_EEPROM; |
| 387 | } |
| 388 | } |
| 389 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 390 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 391 | /* Setup EEPROM for Read/Write */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 392 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 393 | if (eeprom->type == e1000_eeprom_microwire) { |
| 394 | /* Clear SK and DI */ |
| 395 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
| 396 | E1000_WRITE_REG(hw, EECD, eecd); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 397 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 398 | /* Set CS */ |
| 399 | eecd |= E1000_EECD_CS; |
| 400 | E1000_WRITE_REG(hw, EECD, eecd); |
| 401 | } else if (eeprom->type == e1000_eeprom_spi) { |
| 402 | /* Clear SK and CS */ |
| 403 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
| 404 | E1000_WRITE_REG(hw, EECD, eecd); |
| 405 | udelay(1); |
| 406 | } |
| 407 | |
| 408 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 409 | } |
| 410 | |
| 411 | /****************************************************************************** |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 412 | * Sets up eeprom variables in the hw struct. Must be called after mac_type |
| 413 | * is configured. Additionally, if this is ICH8, the flash controller GbE |
| 414 | * registers must be mapped, or this will crash. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 415 | * |
| 416 | * hw - Struct containing variables accessed by shared code |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 417 | *****************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 418 | static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 419 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 420 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 421 | uint32_t eecd; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 422 | int32_t ret_val = E1000_SUCCESS; |
| 423 | uint16_t eeprom_size; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 424 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 425 | if (hw->mac_type == e1000_igb) |
| 426 | eecd = E1000_READ_REG(hw, I210_EECD); |
| 427 | else |
| 428 | eecd = E1000_READ_REG(hw, EECD); |
| 429 | |
Timur Tabi | edc45b5 | 2009-08-17 15:55:38 -0500 | [diff] [blame] | 430 | DEBUGFUNC(); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 431 | |
| 432 | switch (hw->mac_type) { |
| 433 | case e1000_82542_rev2_0: |
| 434 | case e1000_82542_rev2_1: |
| 435 | case e1000_82543: |
| 436 | case e1000_82544: |
| 437 | eeprom->type = e1000_eeprom_microwire; |
| 438 | eeprom->word_size = 64; |
| 439 | eeprom->opcode_bits = 3; |
| 440 | eeprom->address_bits = 6; |
| 441 | eeprom->delay_usec = 50; |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 442 | eeprom->use_eerd = false; |
| 443 | eeprom->use_eewr = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 444 | break; |
| 445 | case e1000_82540: |
| 446 | case e1000_82545: |
| 447 | case e1000_82545_rev_3: |
| 448 | case e1000_82546: |
| 449 | case e1000_82546_rev_3: |
| 450 | eeprom->type = e1000_eeprom_microwire; |
| 451 | eeprom->opcode_bits = 3; |
| 452 | eeprom->delay_usec = 50; |
| 453 | if (eecd & E1000_EECD_SIZE) { |
| 454 | eeprom->word_size = 256; |
| 455 | eeprom->address_bits = 8; |
| 456 | } else { |
| 457 | eeprom->word_size = 64; |
| 458 | eeprom->address_bits = 6; |
| 459 | } |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 460 | eeprom->use_eerd = false; |
| 461 | eeprom->use_eewr = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 462 | break; |
| 463 | case e1000_82541: |
| 464 | case e1000_82541_rev_2: |
| 465 | case e1000_82547: |
| 466 | case e1000_82547_rev_2: |
| 467 | if (eecd & E1000_EECD_TYPE) { |
| 468 | eeprom->type = e1000_eeprom_spi; |
| 469 | eeprom->opcode_bits = 8; |
| 470 | eeprom->delay_usec = 1; |
| 471 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 472 | eeprom->page_size = 32; |
| 473 | eeprom->address_bits = 16; |
| 474 | } else { |
| 475 | eeprom->page_size = 8; |
| 476 | eeprom->address_bits = 8; |
| 477 | } |
| 478 | } else { |
| 479 | eeprom->type = e1000_eeprom_microwire; |
| 480 | eeprom->opcode_bits = 3; |
| 481 | eeprom->delay_usec = 50; |
| 482 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 483 | eeprom->word_size = 256; |
| 484 | eeprom->address_bits = 8; |
| 485 | } else { |
| 486 | eeprom->word_size = 64; |
| 487 | eeprom->address_bits = 6; |
| 488 | } |
| 489 | } |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 490 | eeprom->use_eerd = false; |
| 491 | eeprom->use_eewr = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 492 | break; |
| 493 | case e1000_82571: |
| 494 | case e1000_82572: |
| 495 | eeprom->type = e1000_eeprom_spi; |
| 496 | eeprom->opcode_bits = 8; |
| 497 | eeprom->delay_usec = 1; |
| 498 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 499 | eeprom->page_size = 32; |
| 500 | eeprom->address_bits = 16; |
| 501 | } else { |
| 502 | eeprom->page_size = 8; |
| 503 | eeprom->address_bits = 8; |
| 504 | } |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 505 | eeprom->use_eerd = false; |
| 506 | eeprom->use_eewr = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 507 | break; |
| 508 | case e1000_82573: |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 509 | case e1000_82574: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 510 | eeprom->type = e1000_eeprom_spi; |
| 511 | eeprom->opcode_bits = 8; |
| 512 | eeprom->delay_usec = 1; |
| 513 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 514 | eeprom->page_size = 32; |
| 515 | eeprom->address_bits = 16; |
| 516 | } else { |
| 517 | eeprom->page_size = 8; |
| 518 | eeprom->address_bits = 8; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 519 | } |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 520 | if (e1000_is_onboard_nvm_eeprom(hw) == false) { |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 521 | eeprom->use_eerd = true; |
| 522 | eeprom->use_eewr = true; |
| 523 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 524 | eeprom->type = e1000_eeprom_flash; |
| 525 | eeprom->word_size = 2048; |
| 526 | |
| 527 | /* Ensure that the Autonomous FLASH update bit is cleared due to |
| 528 | * Flash update issue on parts which use a FLASH for NVM. */ |
| 529 | eecd &= ~E1000_EECD_AUPDEN; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 530 | E1000_WRITE_REG(hw, EECD, eecd); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 531 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 532 | break; |
| 533 | case e1000_80003es2lan: |
| 534 | eeprom->type = e1000_eeprom_spi; |
| 535 | eeprom->opcode_bits = 8; |
| 536 | eeprom->delay_usec = 1; |
| 537 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 538 | eeprom->page_size = 32; |
| 539 | eeprom->address_bits = 16; |
| 540 | } else { |
| 541 | eeprom->page_size = 8; |
| 542 | eeprom->address_bits = 8; |
| 543 | } |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 544 | eeprom->use_eerd = true; |
| 545 | eeprom->use_eewr = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 546 | break; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 547 | case e1000_igb: |
| 548 | /* i210 has 4k of iNVM mapped as EEPROM */ |
| 549 | eeprom->type = e1000_eeprom_invm; |
| 550 | eeprom->opcode_bits = 8; |
| 551 | eeprom->delay_usec = 1; |
| 552 | eeprom->page_size = 32; |
| 553 | eeprom->address_bits = 16; |
| 554 | eeprom->use_eerd = true; |
| 555 | eeprom->use_eewr = false; |
| 556 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 557 | default: |
| 558 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 559 | } |
| 560 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 561 | if (eeprom->type == e1000_eeprom_spi || |
| 562 | eeprom->type == e1000_eeprom_invm) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 563 | /* eeprom_size will be an enum [0..8] that maps |
| 564 | * to eeprom sizes 128B to |
| 565 | * 32KB (incremented by powers of 2). |
| 566 | */ |
| 567 | if (hw->mac_type <= e1000_82547_rev_2) { |
| 568 | /* Set to default value for initial eeprom read. */ |
| 569 | eeprom->word_size = 64; |
| 570 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, |
| 571 | &eeprom_size); |
| 572 | if (ret_val) |
| 573 | return ret_val; |
| 574 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) |
| 575 | >> EEPROM_SIZE_SHIFT; |
| 576 | /* 256B eeprom size was not supported in earlier |
| 577 | * hardware, so we bump eeprom_size up one to |
| 578 | * ensure that "1" (which maps to 256B) is never |
| 579 | * the result used in the shifting logic below. */ |
| 580 | if (eeprom_size) |
| 581 | eeprom_size++; |
| 582 | } else { |
| 583 | eeprom_size = (uint16_t)((eecd & |
| 584 | E1000_EECD_SIZE_EX_MASK) >> |
| 585 | E1000_EECD_SIZE_EX_SHIFT); |
| 586 | } |
| 587 | |
| 588 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
| 589 | } |
| 590 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 591 | } |
| 592 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 593 | /****************************************************************************** |
| 594 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
| 595 | * |
| 596 | * hw - Struct containing variables accessed by shared code |
| 597 | *****************************************************************************/ |
| 598 | static int32_t |
| 599 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 600 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 601 | uint32_t attempts = 100000; |
| 602 | uint32_t i, reg = 0; |
| 603 | int32_t done = E1000_ERR_EEPROM; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 604 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 605 | for (i = 0; i < attempts; i++) { |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 606 | if (eerd == E1000_EEPROM_POLL_READ) { |
| 607 | if (hw->mac_type == e1000_igb) |
| 608 | reg = E1000_READ_REG(hw, I210_EERD); |
| 609 | else |
| 610 | reg = E1000_READ_REG(hw, EERD); |
| 611 | } else { |
| 612 | if (hw->mac_type == e1000_igb) |
| 613 | reg = E1000_READ_REG(hw, I210_EEWR); |
| 614 | else |
| 615 | reg = E1000_READ_REG(hw, EEWR); |
| 616 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 617 | |
| 618 | if (reg & E1000_EEPROM_RW_REG_DONE) { |
| 619 | done = E1000_SUCCESS; |
| 620 | break; |
| 621 | } |
| 622 | udelay(5); |
| 623 | } |
| 624 | |
| 625 | return done; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 626 | } |
| 627 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 628 | /****************************************************************************** |
| 629 | * Reads a 16 bit word from the EEPROM using the EERD register. |
| 630 | * |
| 631 | * hw - Struct containing variables accessed by shared code |
| 632 | * offset - offset of word in the EEPROM to read |
| 633 | * data - word read from the EEPROM |
| 634 | * words - number of words to read |
| 635 | *****************************************************************************/ |
| 636 | static int32_t |
| 637 | e1000_read_eeprom_eerd(struct e1000_hw *hw, |
| 638 | uint16_t offset, |
| 639 | uint16_t words, |
| 640 | uint16_t *data) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 641 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 642 | uint32_t i, eerd = 0; |
| 643 | int32_t error = 0; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 644 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 645 | for (i = 0; i < words; i++) { |
| 646 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + |
| 647 | E1000_EEPROM_RW_REG_START; |
| 648 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 649 | if (hw->mac_type == e1000_igb) |
| 650 | E1000_WRITE_REG(hw, I210_EERD, eerd); |
| 651 | else |
| 652 | E1000_WRITE_REG(hw, EERD, eerd); |
| 653 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 654 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
| 655 | |
| 656 | if (error) |
| 657 | break; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 658 | |
| 659 | if (hw->mac_type == e1000_igb) { |
| 660 | data[i] = (E1000_READ_REG(hw, I210_EERD) >> |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 661 | E1000_EEPROM_RW_REG_DATA); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 662 | } else { |
| 663 | data[i] = (E1000_READ_REG(hw, EERD) >> |
| 664 | E1000_EEPROM_RW_REG_DATA); |
| 665 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 666 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 667 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 668 | |
| 669 | return error; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 670 | } |
| 671 | |
Kyle Moffett | 142cbf8 | 2011-10-18 11:05:28 +0000 | [diff] [blame] | 672 | void e1000_release_eeprom(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 673 | { |
| 674 | uint32_t eecd; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 675 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 676 | DEBUGFUNC(); |
| 677 | |
| 678 | eecd = E1000_READ_REG(hw, EECD); |
| 679 | |
| 680 | if (hw->eeprom.type == e1000_eeprom_spi) { |
| 681 | eecd |= E1000_EECD_CS; /* Pull CS high */ |
| 682 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
| 683 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 684 | E1000_WRITE_REG(hw, EECD, eecd); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 685 | |
| 686 | udelay(hw->eeprom.delay_usec); |
| 687 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
| 688 | /* cleanup eeprom */ |
| 689 | |
| 690 | /* CS on Microwire is active-high */ |
| 691 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
| 692 | |
| 693 | E1000_WRITE_REG(hw, EECD, eecd); |
| 694 | |
| 695 | /* Rising edge of clock */ |
| 696 | eecd |= E1000_EECD_SK; |
| 697 | E1000_WRITE_REG(hw, EECD, eecd); |
| 698 | E1000_WRITE_FLUSH(hw); |
| 699 | udelay(hw->eeprom.delay_usec); |
| 700 | |
| 701 | /* Falling edge of clock */ |
| 702 | eecd &= ~E1000_EECD_SK; |
| 703 | E1000_WRITE_REG(hw, EECD, eecd); |
| 704 | E1000_WRITE_FLUSH(hw); |
| 705 | udelay(hw->eeprom.delay_usec); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 706 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 707 | |
| 708 | /* Stop requesting EEPROM access */ |
| 709 | if (hw->mac_type > e1000_82544) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 710 | eecd &= ~E1000_EECD_REQ; |
| 711 | E1000_WRITE_REG(hw, EECD, eecd); |
| 712 | } |
Tim Harvey | 5cb59ec | 2015-05-19 10:01:18 -0700 | [diff] [blame] | 713 | |
| 714 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 715 | } |
Tim Harvey | 5cb59ec | 2015-05-19 10:01:18 -0700 | [diff] [blame] | 716 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 717 | /****************************************************************************** |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 718 | * Reads a 16 bit word from the EEPROM. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 719 | * |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 720 | * hw - Struct containing variables accessed by shared code |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 721 | *****************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 722 | static int32_t |
| 723 | e1000_spi_eeprom_ready(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 724 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 725 | uint16_t retry_count = 0; |
| 726 | uint8_t spi_stat_reg; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 727 | |
| 728 | DEBUGFUNC(); |
| 729 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 730 | /* Read "Status Register" repeatedly until the LSB is cleared. The |
| 731 | * EEPROM will signal that the command has been completed by clearing |
| 732 | * bit 0 of the internal status register. If it's not cleared within |
| 733 | * 5 milliseconds, then error out. |
| 734 | */ |
| 735 | retry_count = 0; |
| 736 | do { |
| 737 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
| 738 | hw->eeprom.opcode_bits); |
| 739 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); |
| 740 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
| 741 | break; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 742 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 743 | udelay(5); |
| 744 | retry_count += 5; |
| 745 | |
| 746 | e1000_standby_eeprom(hw); |
| 747 | } while (retry_count < EEPROM_MAX_RETRY_SPI); |
| 748 | |
| 749 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
| 750 | * only 0-5mSec on 5V devices) |
| 751 | */ |
| 752 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { |
| 753 | DEBUGOUT("SPI EEPROM Status error\n"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 754 | return -E1000_ERR_EEPROM; |
| 755 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 756 | |
| 757 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 758 | } |
| 759 | |
| 760 | /****************************************************************************** |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 761 | * Reads a 16 bit word from the EEPROM. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 762 | * |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 763 | * hw - Struct containing variables accessed by shared code |
| 764 | * offset - offset of word in the EEPROM to read |
| 765 | * data - word read from the EEPROM |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 766 | *****************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 767 | static int32_t |
| 768 | e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, |
| 769 | uint16_t words, uint16_t *data) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 770 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 771 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 772 | uint32_t i = 0; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 773 | |
| 774 | DEBUGFUNC(); |
| 775 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 776 | /* If eeprom is not yet detected, do so now */ |
| 777 | if (eeprom->word_size == 0) |
| 778 | e1000_init_eeprom_params(hw); |
| 779 | |
| 780 | /* A check for invalid values: offset too large, too many words, |
| 781 | * and not enough words. |
| 782 | */ |
| 783 | if ((offset >= eeprom->word_size) || |
| 784 | (words > eeprom->word_size - offset) || |
| 785 | (words == 0)) { |
| 786 | DEBUGOUT("\"words\" parameter out of bounds." |
| 787 | "Words = %d, size = %d\n", offset, eeprom->word_size); |
| 788 | return -E1000_ERR_EEPROM; |
| 789 | } |
| 790 | |
| 791 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
| 792 | * directly. In this case, we need to acquire the EEPROM so that |
| 793 | * FW or other port software does not interrupt. |
| 794 | */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 795 | if (e1000_is_onboard_nvm_eeprom(hw) == true && |
| 796 | hw->eeprom.use_eerd == false) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 797 | |
| 798 | /* Prepare the EEPROM for bit-bang reading */ |
| 799 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
| 800 | return -E1000_ERR_EEPROM; |
| 801 | } |
| 802 | |
| 803 | /* Eerd register EEPROM access requires no eeprom aquire/release */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 804 | if (eeprom->use_eerd == true) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 805 | return e1000_read_eeprom_eerd(hw, offset, words, data); |
| 806 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 807 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
| 808 | * acquired the EEPROM at this point, so any returns should relase it */ |
| 809 | if (eeprom->type == e1000_eeprom_spi) { |
| 810 | uint16_t word_in; |
| 811 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; |
| 812 | |
| 813 | if (e1000_spi_eeprom_ready(hw)) { |
| 814 | e1000_release_eeprom(hw); |
| 815 | return -E1000_ERR_EEPROM; |
| 816 | } |
| 817 | |
| 818 | e1000_standby_eeprom(hw); |
| 819 | |
| 820 | /* Some SPI eeproms use the 8th address bit embedded in |
| 821 | * the opcode */ |
| 822 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
| 823 | read_opcode |= EEPROM_A8_OPCODE_SPI; |
| 824 | |
| 825 | /* Send the READ command (opcode + addr) */ |
| 826 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
| 827 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), |
| 828 | eeprom->address_bits); |
| 829 | |
| 830 | /* Read the data. The address of the eeprom internally |
| 831 | * increments with each byte (spi) being read, saving on the |
| 832 | * overhead of eeprom setup and tear-down. The address |
| 833 | * counter will roll over if reading beyond the size of |
| 834 | * the eeprom, thus allowing the entire memory to be read |
| 835 | * starting from any offset. */ |
| 836 | for (i = 0; i < words; i++) { |
| 837 | word_in = e1000_shift_in_ee_bits(hw, 16); |
| 838 | data[i] = (word_in >> 8) | (word_in << 8); |
| 839 | } |
| 840 | } else if (eeprom->type == e1000_eeprom_microwire) { |
| 841 | for (i = 0; i < words; i++) { |
| 842 | /* Send the READ command (opcode + addr) */ |
| 843 | e1000_shift_out_ee_bits(hw, |
| 844 | EEPROM_READ_OPCODE_MICROWIRE, |
| 845 | eeprom->opcode_bits); |
| 846 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), |
| 847 | eeprom->address_bits); |
| 848 | |
| 849 | /* Read the data. For microwire, each word requires |
| 850 | * the overhead of eeprom setup and tear-down. */ |
| 851 | data[i] = e1000_shift_in_ee_bits(hw, 16); |
| 852 | e1000_standby_eeprom(hw); |
| 853 | } |
| 854 | } |
| 855 | |
| 856 | /* End this read operation */ |
| 857 | e1000_release_eeprom(hw); |
| 858 | |
| 859 | return E1000_SUCCESS; |
| 860 | } |
| 861 | |
Hannu Lounento | c56999e | 2018-01-10 20:31:24 +0100 | [diff] [blame] | 862 | /****************************************************************************** |
| 863 | * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR |
| 864 | * @hw: pointer to the HW structure |
| 865 | * @offset: offset within the Shadow Ram to be written to |
| 866 | * @words: number of words to write |
| 867 | * @data: 16 bit word(s) to be written to the Shadow Ram |
| 868 | * |
| 869 | * Writes data to Shadow Ram at offset using EEWR register. |
| 870 | * |
| 871 | * If e1000_update_eeprom_checksum_i210 is not called after this function, the |
| 872 | * Shadow Ram will most likely contain an invalid checksum. |
| 873 | *****************************************************************************/ |
| 874 | static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset, |
| 875 | uint16_t words, uint16_t *data) |
| 876 | { |
| 877 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 878 | uint32_t i, k, eewr = 0; |
| 879 | uint32_t attempts = 100000; |
| 880 | int32_t ret_val = 0; |
| 881 | |
| 882 | /* A check for invalid values: offset too large, too many words, |
| 883 | * too many words for the offset, and not enough words. |
| 884 | */ |
| 885 | if ((offset >= eeprom->word_size) || |
| 886 | (words > (eeprom->word_size - offset)) || (words == 0)) { |
| 887 | DEBUGOUT("nvm parameter(s) out of bounds\n"); |
| 888 | ret_val = -E1000_ERR_EEPROM; |
| 889 | goto out; |
| 890 | } |
| 891 | |
| 892 | for (i = 0; i < words; i++) { |
| 893 | eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) |
| 894 | | (data[i] << E1000_EEPROM_RW_REG_DATA) | |
| 895 | E1000_EEPROM_RW_REG_START; |
| 896 | |
| 897 | E1000_WRITE_REG(hw, I210_EEWR, eewr); |
| 898 | |
| 899 | for (k = 0; k < attempts; k++) { |
| 900 | if (E1000_EEPROM_RW_REG_DONE & |
| 901 | E1000_READ_REG(hw, I210_EEWR)) { |
| 902 | ret_val = 0; |
| 903 | break; |
| 904 | } |
| 905 | udelay(5); |
| 906 | } |
| 907 | |
| 908 | if (ret_val) { |
| 909 | DEBUGOUT("Shadow RAM write EEWR timed out\n"); |
| 910 | break; |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | out: |
| 915 | return ret_val; |
| 916 | } |
| 917 | |
| 918 | /****************************************************************************** |
| 919 | * e1000_pool_flash_update_done_i210 - Pool FLUDONE status. |
| 920 | * @hw: pointer to the HW structure |
| 921 | * |
| 922 | *****************************************************************************/ |
| 923 | static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw) |
| 924 | { |
| 925 | int32_t ret_val = -E1000_ERR_EEPROM; |
| 926 | uint32_t i, reg; |
| 927 | |
| 928 | for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) { |
| 929 | reg = E1000_READ_REG(hw, EECD); |
| 930 | if (reg & E1000_EECD_FLUDONE_I210) { |
| 931 | ret_val = 0; |
| 932 | break; |
| 933 | } |
| 934 | udelay(5); |
| 935 | } |
| 936 | |
| 937 | return ret_val; |
| 938 | } |
| 939 | |
| 940 | /****************************************************************************** |
| 941 | * e1000_update_flash_i210 - Commit EEPROM to the flash |
| 942 | * @hw: pointer to the HW structure |
| 943 | * |
| 944 | *****************************************************************************/ |
| 945 | static int32_t e1000_update_flash_i210(struct e1000_hw *hw) |
| 946 | { |
| 947 | int32_t ret_val = 0; |
| 948 | uint32_t flup; |
| 949 | |
| 950 | ret_val = e1000_pool_flash_update_done_i210(hw); |
| 951 | if (ret_val == -E1000_ERR_EEPROM) { |
| 952 | DEBUGOUT("Flash update time out\n"); |
| 953 | goto out; |
| 954 | } |
| 955 | |
| 956 | flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210; |
| 957 | E1000_WRITE_REG(hw, EECD, flup); |
| 958 | |
| 959 | ret_val = e1000_pool_flash_update_done_i210(hw); |
| 960 | if (ret_val) |
| 961 | DEBUGOUT("Flash update time out\n"); |
| 962 | else |
| 963 | DEBUGOUT("Flash update complete\n"); |
| 964 | |
| 965 | out: |
| 966 | return ret_val; |
| 967 | } |
| 968 | |
| 969 | /****************************************************************************** |
| 970 | * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum |
| 971 | * @hw: pointer to the HW structure |
| 972 | * |
| 973 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM |
| 974 | * up to the checksum. Then calculates the EEPROM checksum and writes the |
| 975 | * value to the EEPROM. Next commit EEPROM data onto the Flash. |
| 976 | *****************************************************************************/ |
| 977 | static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw) |
| 978 | { |
| 979 | int32_t ret_val = 0; |
| 980 | uint16_t checksum = 0; |
| 981 | uint16_t i, nvm_data; |
| 982 | |
| 983 | /* Read the first word from the EEPROM. If this times out or fails, do |
| 984 | * not continue or we could be in for a very long wait while every |
| 985 | * EEPROM read fails |
| 986 | */ |
| 987 | ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data); |
| 988 | if (ret_val) { |
| 989 | DEBUGOUT("EEPROM read failed\n"); |
| 990 | goto out; |
| 991 | } |
| 992 | |
| 993 | if (!(e1000_get_hw_eeprom_semaphore(hw))) { |
| 994 | /* Do not use hw->nvm.ops.write, hw->nvm.ops.read |
| 995 | * because we do not want to take the synchronization |
| 996 | * semaphores twice here. |
| 997 | */ |
| 998 | |
| 999 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
| 1000 | ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data); |
| 1001 | if (ret_val) { |
| 1002 | e1000_put_hw_eeprom_semaphore(hw); |
| 1003 | DEBUGOUT("EEPROM Read Error while updating checksum.\n"); |
| 1004 | goto out; |
| 1005 | } |
| 1006 | checksum += nvm_data; |
| 1007 | } |
| 1008 | checksum = (uint16_t)EEPROM_SUM - checksum; |
| 1009 | ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1, |
| 1010 | &checksum); |
| 1011 | if (ret_val) { |
| 1012 | e1000_put_hw_eeprom_semaphore(hw); |
| 1013 | DEBUGOUT("EEPROM Write Error while updating checksum.\n"); |
| 1014 | goto out; |
| 1015 | } |
| 1016 | |
| 1017 | e1000_put_hw_eeprom_semaphore(hw); |
| 1018 | |
| 1019 | ret_val = e1000_update_flash_i210(hw); |
| 1020 | } else { |
| 1021 | ret_val = -E1000_ERR_SWFW_SYNC; |
| 1022 | } |
| 1023 | |
| 1024 | out: |
| 1025 | return ret_val; |
| 1026 | } |
Hannu Lounento | c56999e | 2018-01-10 20:31:24 +0100 | [diff] [blame] | 1027 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1028 | /****************************************************************************** |
| 1029 | * Verifies that the EEPROM has a valid checksum |
| 1030 | * |
| 1031 | * hw - Struct containing variables accessed by shared code |
| 1032 | * |
| 1033 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
| 1034 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
| 1035 | * valid. |
| 1036 | *****************************************************************************/ |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1037 | static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1038 | { |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1039 | uint16_t i, checksum, checksum_reg, *buf; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1040 | |
| 1041 | DEBUGFUNC(); |
| 1042 | |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1043 | /* Allocate a temporary buffer */ |
| 1044 | buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); |
| 1045 | if (!buf) { |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1046 | E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1047 | return -E1000_ERR_EEPROM; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1048 | } |
| 1049 | |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1050 | /* Read the EEPROM */ |
| 1051 | if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1052 | E1000_ERR(hw, "Unable to read EEPROM!\n"); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1053 | return -E1000_ERR_EEPROM; |
| 1054 | } |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1055 | |
| 1056 | /* Compute the checksum */ |
Wolfgang Denk | 1569033 | 2011-10-28 07:37:04 +0200 | [diff] [blame] | 1057 | checksum = 0; |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1058 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
| 1059 | checksum += buf[i]; |
| 1060 | checksum = ((uint16_t)EEPROM_SUM) - checksum; |
| 1061 | checksum_reg = buf[i]; |
| 1062 | |
| 1063 | /* Verify it! */ |
| 1064 | if (checksum == checksum_reg) |
| 1065 | return 0; |
| 1066 | |
| 1067 | /* Hrm, verification failed, print an error */ |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1068 | E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); |
| 1069 | E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", |
| 1070 | checksum_reg, checksum); |
Kyle Moffett | 70946bc | 2011-10-18 11:05:27 +0000 | [diff] [blame] | 1071 | |
| 1072 | return -E1000_ERR_EEPROM; |
Roy Zang | 9b7c430 | 2009-08-11 03:48:05 +0800 | [diff] [blame] | 1073 | } |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1074 | #endif /* CONFIG_E1000_NO_NVM */ |
Roy Zang | 9b7c430 | 2009-08-11 03:48:05 +0800 | [diff] [blame] | 1075 | |
| 1076 | /***************************************************************************** |
| 1077 | * Set PHY to class A mode |
| 1078 | * Assumes the following operations will follow to enable the new class mode. |
| 1079 | * 1. Do a PHY soft reset |
| 1080 | * 2. Restart auto-negotiation or force link. |
| 1081 | * |
| 1082 | * hw - Struct containing variables accessed by shared code |
| 1083 | ****************************************************************************/ |
| 1084 | static int32_t |
| 1085 | e1000_set_phy_mode(struct e1000_hw *hw) |
| 1086 | { |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1087 | #ifndef CONFIG_E1000_NO_NVM |
Roy Zang | 9b7c430 | 2009-08-11 03:48:05 +0800 | [diff] [blame] | 1088 | int32_t ret_val; |
| 1089 | uint16_t eeprom_data; |
| 1090 | |
| 1091 | DEBUGFUNC(); |
| 1092 | |
| 1093 | if ((hw->mac_type == e1000_82545_rev_3) && |
| 1094 | (hw->media_type == e1000_media_type_copper)) { |
| 1095 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, |
| 1096 | 1, &eeprom_data); |
| 1097 | if (ret_val) |
| 1098 | return ret_val; |
| 1099 | |
| 1100 | if ((eeprom_data != EEPROM_RESERVED_WORD) && |
| 1101 | (eeprom_data & EEPROM_PHY_CLASS_A)) { |
| 1102 | ret_val = e1000_write_phy_reg(hw, |
| 1103 | M88E1000_PHY_PAGE_SELECT, 0x000B); |
| 1104 | if (ret_val) |
| 1105 | return ret_val; |
| 1106 | ret_val = e1000_write_phy_reg(hw, |
| 1107 | M88E1000_PHY_GEN_CONTROL, 0x8104); |
| 1108 | if (ret_val) |
| 1109 | return ret_val; |
| 1110 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 1111 | hw->phy_reset_disable = false; |
Roy Zang | 9b7c430 | 2009-08-11 03:48:05 +0800 | [diff] [blame] | 1112 | } |
| 1113 | } |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1114 | #endif |
Roy Zang | 9b7c430 | 2009-08-11 03:48:05 +0800 | [diff] [blame] | 1115 | return E1000_SUCCESS; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1116 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1117 | |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1118 | #ifndef CONFIG_E1000_NO_NVM |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1119 | /*************************************************************************** |
| 1120 | * |
| 1121 | * Obtaining software semaphore bit (SMBI) before resetting PHY. |
| 1122 | * |
| 1123 | * hw: Struct containing variables accessed by shared code |
| 1124 | * |
| 1125 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. |
| 1126 | * E1000_SUCCESS at any other case. |
| 1127 | * |
| 1128 | ***************************************************************************/ |
| 1129 | static int32_t |
| 1130 | e1000_get_software_semaphore(struct e1000_hw *hw) |
| 1131 | { |
| 1132 | int32_t timeout = hw->eeprom.word_size + 1; |
| 1133 | uint32_t swsm; |
| 1134 | |
| 1135 | DEBUGFUNC(); |
| 1136 | |
Hannu Lounento | c56999e | 2018-01-10 20:31:24 +0100 | [diff] [blame] | 1137 | if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1138 | return E1000_SUCCESS; |
| 1139 | |
| 1140 | while (timeout) { |
| 1141 | swsm = E1000_READ_REG(hw, SWSM); |
| 1142 | /* If SMBI bit cleared, it is now set and we hold |
| 1143 | * the semaphore */ |
| 1144 | if (!(swsm & E1000_SWSM_SMBI)) |
| 1145 | break; |
| 1146 | mdelay(1); |
| 1147 | timeout--; |
| 1148 | } |
| 1149 | |
| 1150 | if (!timeout) { |
| 1151 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); |
| 1152 | return -E1000_ERR_RESET; |
| 1153 | } |
| 1154 | |
| 1155 | return E1000_SUCCESS; |
| 1156 | } |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1157 | #endif |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1158 | |
| 1159 | /*************************************************************************** |
| 1160 | * This function clears HW semaphore bits. |
| 1161 | * |
| 1162 | * hw: Struct containing variables accessed by shared code |
| 1163 | * |
| 1164 | * returns: - None. |
| 1165 | * |
| 1166 | ***************************************************************************/ |
| 1167 | static void |
| 1168 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
| 1169 | { |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1170 | #ifndef CONFIG_E1000_NO_NVM |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1171 | uint32_t swsm; |
| 1172 | |
| 1173 | DEBUGFUNC(); |
| 1174 | |
| 1175 | if (!hw->eeprom_semaphore_present) |
| 1176 | return; |
| 1177 | |
| 1178 | swsm = E1000_READ_REG(hw, SWSM); |
Bernhard Messerklinger | 801ae71 | 2018-02-15 08:55:49 +0100 | [diff] [blame] | 1179 | if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1180 | /* Release both semaphores. */ |
| 1181 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
| 1182 | } else |
| 1183 | swsm &= ~(E1000_SWSM_SWESMBI); |
| 1184 | E1000_WRITE_REG(hw, SWSM, swsm); |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1185 | #endif |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1186 | } |
| 1187 | |
| 1188 | /*************************************************************************** |
| 1189 | * |
| 1190 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting |
| 1191 | * adapter or Eeprom access. |
| 1192 | * |
| 1193 | * hw: Struct containing variables accessed by shared code |
| 1194 | * |
| 1195 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. |
| 1196 | * E1000_SUCCESS at any other case. |
| 1197 | * |
| 1198 | ***************************************************************************/ |
| 1199 | static int32_t |
| 1200 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
| 1201 | { |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1202 | #ifndef CONFIG_E1000_NO_NVM |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1203 | int32_t timeout; |
| 1204 | uint32_t swsm; |
| 1205 | |
| 1206 | DEBUGFUNC(); |
| 1207 | |
| 1208 | if (!hw->eeprom_semaphore_present) |
| 1209 | return E1000_SUCCESS; |
| 1210 | |
Hannu Lounento | c56999e | 2018-01-10 20:31:24 +0100 | [diff] [blame] | 1211 | if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1212 | /* Get the SW semaphore. */ |
| 1213 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) |
| 1214 | return -E1000_ERR_EEPROM; |
| 1215 | } |
| 1216 | |
| 1217 | /* Get the FW semaphore. */ |
| 1218 | timeout = hw->eeprom.word_size + 1; |
| 1219 | while (timeout) { |
| 1220 | swsm = E1000_READ_REG(hw, SWSM); |
| 1221 | swsm |= E1000_SWSM_SWESMBI; |
| 1222 | E1000_WRITE_REG(hw, SWSM, swsm); |
| 1223 | /* if we managed to set the bit we got the semaphore. */ |
| 1224 | swsm = E1000_READ_REG(hw, SWSM); |
| 1225 | if (swsm & E1000_SWSM_SWESMBI) |
| 1226 | break; |
| 1227 | |
| 1228 | udelay(50); |
| 1229 | timeout--; |
| 1230 | } |
| 1231 | |
| 1232 | if (!timeout) { |
| 1233 | /* Release semaphores */ |
| 1234 | e1000_put_hw_eeprom_semaphore(hw); |
| 1235 | DEBUGOUT("Driver can't access the Eeprom - " |
| 1236 | "SWESMBI bit is set.\n"); |
| 1237 | return -E1000_ERR_EEPROM; |
| 1238 | } |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1239 | #endif |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1240 | return E1000_SUCCESS; |
| 1241 | } |
| 1242 | |
Tim Harvey | 5cb59ec | 2015-05-19 10:01:18 -0700 | [diff] [blame] | 1243 | /* Take ownership of the PHY */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1244 | static int32_t |
| 1245 | e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) |
| 1246 | { |
| 1247 | uint32_t swfw_sync = 0; |
| 1248 | uint32_t swmask = mask; |
| 1249 | uint32_t fwmask = mask << 16; |
| 1250 | int32_t timeout = 200; |
| 1251 | |
| 1252 | DEBUGFUNC(); |
| 1253 | while (timeout) { |
| 1254 | if (e1000_get_hw_eeprom_semaphore(hw)) |
| 1255 | return -E1000_ERR_SWFW_SYNC; |
| 1256 | |
Tim Harvey | dca3565 | 2015-05-19 10:01:19 -0700 | [diff] [blame] | 1257 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
York Sun | 4303a83 | 2014-10-17 13:44:06 -0700 | [diff] [blame] | 1258 | if (!(swfw_sync & (fwmask | swmask))) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1259 | break; |
| 1260 | |
| 1261 | /* firmware currently using resource (fwmask) */ |
| 1262 | /* or other software thread currently using resource (swmask) */ |
| 1263 | e1000_put_hw_eeprom_semaphore(hw); |
| 1264 | mdelay(5); |
| 1265 | timeout--; |
| 1266 | } |
| 1267 | |
| 1268 | if (!timeout) { |
| 1269 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
| 1270 | return -E1000_ERR_SWFW_SYNC; |
| 1271 | } |
| 1272 | |
| 1273 | swfw_sync |= swmask; |
| 1274 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
| 1275 | |
| 1276 | e1000_put_hw_eeprom_semaphore(hw); |
| 1277 | return E1000_SUCCESS; |
| 1278 | } |
| 1279 | |
Tim Harvey | 5cb59ec | 2015-05-19 10:01:18 -0700 | [diff] [blame] | 1280 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) |
| 1281 | { |
| 1282 | uint32_t swfw_sync = 0; |
| 1283 | |
| 1284 | DEBUGFUNC(); |
| 1285 | while (e1000_get_hw_eeprom_semaphore(hw)) |
| 1286 | ; /* Empty */ |
| 1287 | |
| 1288 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
| 1289 | swfw_sync &= ~mask; |
| 1290 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
| 1291 | |
| 1292 | e1000_put_hw_eeprom_semaphore(hw); |
| 1293 | } |
| 1294 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 1295 | static bool e1000_is_second_port(struct e1000_hw *hw) |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 1296 | { |
| 1297 | switch (hw->mac_type) { |
| 1298 | case e1000_80003es2lan: |
| 1299 | case e1000_82546: |
| 1300 | case e1000_82571: |
| 1301 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 1302 | return true; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 1303 | /* Fallthrough */ |
| 1304 | default: |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 1305 | return false; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 1306 | } |
| 1307 | } |
| 1308 | |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1309 | #ifndef CONFIG_E1000_NO_NVM |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1310 | /****************************************************************************** |
Hannu Lounento | f36be3c | 2018-01-10 20:31:25 +0100 | [diff] [blame] | 1311 | * Reads the adapter's MAC address from the EEPROM |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1312 | * |
Hannu Lounento | f36be3c | 2018-01-10 20:31:25 +0100 | [diff] [blame] | 1313 | * hw - Struct containing variables accessed by shared code |
| 1314 | * enetaddr - buffering where the MAC address will be stored |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1315 | *****************************************************************************/ |
Hannu Lounento | f36be3c | 2018-01-10 20:31:25 +0100 | [diff] [blame] | 1316 | static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw, |
| 1317 | unsigned char enetaddr[6]) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1318 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1319 | uint16_t offset; |
| 1320 | uint16_t eeprom_data; |
| 1321 | int i; |
| 1322 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1323 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1324 | offset = i >> 1; |
Hannu Lounento | f36be3c | 2018-01-10 20:31:25 +0100 | [diff] [blame] | 1325 | if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1326 | DEBUGOUT("EEPROM Read Error\n"); |
| 1327 | return -E1000_ERR_EEPROM; |
| 1328 | } |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1329 | enetaddr[i] = eeprom_data & 0xff; |
| 1330 | enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1331 | } |
Hannu Lounento | f36be3c | 2018-01-10 20:31:25 +0100 | [diff] [blame] | 1332 | |
| 1333 | return 0; |
| 1334 | } |
| 1335 | |
| 1336 | /****************************************************************************** |
| 1337 | * Reads the adapter's MAC address from the RAL/RAH registers |
| 1338 | * |
| 1339 | * hw - Struct containing variables accessed by shared code |
| 1340 | * enetaddr - buffering where the MAC address will be stored |
| 1341 | *****************************************************************************/ |
| 1342 | static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw, |
| 1343 | unsigned char enetaddr[6]) |
| 1344 | { |
| 1345 | uint16_t offset, tmp; |
| 1346 | uint32_t reg_data = 0; |
| 1347 | int i; |
| 1348 | |
| 1349 | if (hw->mac_type != e1000_igb) |
| 1350 | return -E1000_ERR_MAC_TYPE; |
| 1351 | |
| 1352 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
| 1353 | offset = i >> 1; |
| 1354 | |
| 1355 | if (offset == 0) |
| 1356 | reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); |
| 1357 | else if (offset == 1) |
| 1358 | reg_data >>= 16; |
| 1359 | else if (offset == 2) |
| 1360 | reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); |
| 1361 | tmp = reg_data & 0xffff; |
| 1362 | |
| 1363 | enetaddr[i] = tmp & 0xff; |
| 1364 | enetaddr[i + 1] = (tmp >> 8) & 0xff; |
| 1365 | } |
| 1366 | |
| 1367 | return 0; |
| 1368 | } |
| 1369 | |
| 1370 | /****************************************************************************** |
| 1371 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
| 1372 | * second function of dual function devices |
| 1373 | * |
| 1374 | * hw - Struct containing variables accessed by shared code |
| 1375 | * enetaddr - buffering where the MAC address will be stored |
| 1376 | *****************************************************************************/ |
| 1377 | static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) |
| 1378 | { |
| 1379 | int ret_val; |
| 1380 | |
| 1381 | if (hw->mac_type == e1000_igb) { |
| 1382 | /* i210 preloads MAC address into RAL/RAH registers */ |
| 1383 | ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr); |
| 1384 | } else { |
| 1385 | ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr); |
| 1386 | } |
| 1387 | if (ret_val) |
| 1388 | return ret_val; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 1389 | |
| 1390 | /* Invert the last bit if this is the second device */ |
| 1391 | if (e1000_is_second_port(hw)) |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1392 | enetaddr[5] ^= 1; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 1393 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1394 | return 0; |
| 1395 | } |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 1396 | #endif |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1397 | |
| 1398 | /****************************************************************************** |
| 1399 | * Initializes receive address filters. |
| 1400 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1401 | * hw - Struct containing variables accessed by shared code |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1402 | * |
| 1403 | * Places the MAC address in receive address register 0 and clears the rest |
| 1404 | * of the receive addresss registers. Clears the multicast table. Assumes |
| 1405 | * the receiver is in reset when the routine is called. |
| 1406 | *****************************************************************************/ |
| 1407 | static void |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1408 | e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1409 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1410 | uint32_t i; |
| 1411 | uint32_t addr_low; |
| 1412 | uint32_t addr_high; |
| 1413 | |
| 1414 | DEBUGFUNC(); |
| 1415 | |
| 1416 | /* Setup the receive address. */ |
| 1417 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1418 | addr_low = (enetaddr[0] | |
| 1419 | (enetaddr[1] << 8) | |
| 1420 | (enetaddr[2] << 16) | (enetaddr[3] << 24)); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1421 | |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1422 | addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1423 | |
| 1424 | E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); |
| 1425 | E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); |
| 1426 | |
| 1427 | /* Zero out the other 15 receive addresses. */ |
| 1428 | DEBUGOUT("Clearing RAR[1-15]\n"); |
| 1429 | for (i = 1; i < E1000_RAR_ENTRIES; i++) { |
| 1430 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
| 1431 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
| 1432 | } |
| 1433 | } |
| 1434 | |
| 1435 | /****************************************************************************** |
| 1436 | * Clears the VLAN filer table |
| 1437 | * |
| 1438 | * hw - Struct containing variables accessed by shared code |
| 1439 | *****************************************************************************/ |
| 1440 | static void |
| 1441 | e1000_clear_vfta(struct e1000_hw *hw) |
| 1442 | { |
| 1443 | uint32_t offset; |
| 1444 | |
| 1445 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) |
| 1446 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); |
| 1447 | } |
| 1448 | |
| 1449 | /****************************************************************************** |
| 1450 | * Set the mac type member in the hw struct. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1451 | * |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1452 | * hw - Struct containing variables accessed by shared code |
| 1453 | *****************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1454 | int32_t |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1455 | e1000_set_mac_type(struct e1000_hw *hw) |
| 1456 | { |
| 1457 | DEBUGFUNC(); |
| 1458 | |
| 1459 | switch (hw->device_id) { |
| 1460 | case E1000_DEV_ID_82542: |
| 1461 | switch (hw->revision_id) { |
| 1462 | case E1000_82542_2_0_REV_ID: |
| 1463 | hw->mac_type = e1000_82542_rev2_0; |
| 1464 | break; |
| 1465 | case E1000_82542_2_1_REV_ID: |
| 1466 | hw->mac_type = e1000_82542_rev2_1; |
| 1467 | break; |
| 1468 | default: |
| 1469 | /* Invalid 82542 revision ID */ |
| 1470 | return -E1000_ERR_MAC_TYPE; |
| 1471 | } |
| 1472 | break; |
| 1473 | case E1000_DEV_ID_82543GC_FIBER: |
| 1474 | case E1000_DEV_ID_82543GC_COPPER: |
| 1475 | hw->mac_type = e1000_82543; |
| 1476 | break; |
| 1477 | case E1000_DEV_ID_82544EI_COPPER: |
| 1478 | case E1000_DEV_ID_82544EI_FIBER: |
| 1479 | case E1000_DEV_ID_82544GC_COPPER: |
| 1480 | case E1000_DEV_ID_82544GC_LOM: |
| 1481 | hw->mac_type = e1000_82544; |
| 1482 | break; |
| 1483 | case E1000_DEV_ID_82540EM: |
| 1484 | case E1000_DEV_ID_82540EM_LOM: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1485 | case E1000_DEV_ID_82540EP: |
| 1486 | case E1000_DEV_ID_82540EP_LOM: |
| 1487 | case E1000_DEV_ID_82540EP_LP: |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1488 | hw->mac_type = e1000_82540; |
| 1489 | break; |
| 1490 | case E1000_DEV_ID_82545EM_COPPER: |
| 1491 | case E1000_DEV_ID_82545EM_FIBER: |
| 1492 | hw->mac_type = e1000_82545; |
| 1493 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1494 | case E1000_DEV_ID_82545GM_COPPER: |
| 1495 | case E1000_DEV_ID_82545GM_FIBER: |
| 1496 | case E1000_DEV_ID_82545GM_SERDES: |
| 1497 | hw->mac_type = e1000_82545_rev_3; |
| 1498 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1499 | case E1000_DEV_ID_82546EB_COPPER: |
| 1500 | case E1000_DEV_ID_82546EB_FIBER: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1501 | case E1000_DEV_ID_82546EB_QUAD_COPPER: |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1502 | hw->mac_type = e1000_82546; |
| 1503 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1504 | case E1000_DEV_ID_82546GB_COPPER: |
| 1505 | case E1000_DEV_ID_82546GB_FIBER: |
| 1506 | case E1000_DEV_ID_82546GB_SERDES: |
| 1507 | case E1000_DEV_ID_82546GB_PCIE: |
| 1508 | case E1000_DEV_ID_82546GB_QUAD_COPPER: |
| 1509 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
| 1510 | hw->mac_type = e1000_82546_rev_3; |
| 1511 | break; |
| 1512 | case E1000_DEV_ID_82541EI: |
| 1513 | case E1000_DEV_ID_82541EI_MOBILE: |
| 1514 | case E1000_DEV_ID_82541ER_LOM: |
| 1515 | hw->mac_type = e1000_82541; |
| 1516 | break; |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 1517 | case E1000_DEV_ID_82541ER: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1518 | case E1000_DEV_ID_82541GI: |
Wolfgang Grandegger | 8562c38 | 2008-05-28 19:55:19 +0200 | [diff] [blame] | 1519 | case E1000_DEV_ID_82541GI_LF: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1520 | case E1000_DEV_ID_82541GI_MOBILE: |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 1521 | hw->mac_type = e1000_82541_rev_2; |
| 1522 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1523 | case E1000_DEV_ID_82547EI: |
| 1524 | case E1000_DEV_ID_82547EI_MOBILE: |
| 1525 | hw->mac_type = e1000_82547; |
| 1526 | break; |
| 1527 | case E1000_DEV_ID_82547GI: |
| 1528 | hw->mac_type = e1000_82547_rev_2; |
| 1529 | break; |
| 1530 | case E1000_DEV_ID_82571EB_COPPER: |
| 1531 | case E1000_DEV_ID_82571EB_FIBER: |
| 1532 | case E1000_DEV_ID_82571EB_SERDES: |
| 1533 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
| 1534 | case E1000_DEV_ID_82571EB_SERDES_QUAD: |
| 1535 | case E1000_DEV_ID_82571EB_QUAD_COPPER: |
| 1536 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
| 1537 | case E1000_DEV_ID_82571EB_QUAD_FIBER: |
| 1538 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: |
| 1539 | hw->mac_type = e1000_82571; |
| 1540 | break; |
| 1541 | case E1000_DEV_ID_82572EI_COPPER: |
| 1542 | case E1000_DEV_ID_82572EI_FIBER: |
| 1543 | case E1000_DEV_ID_82572EI_SERDES: |
| 1544 | case E1000_DEV_ID_82572EI: |
| 1545 | hw->mac_type = e1000_82572; |
| 1546 | break; |
| 1547 | case E1000_DEV_ID_82573E: |
| 1548 | case E1000_DEV_ID_82573E_IAMT: |
| 1549 | case E1000_DEV_ID_82573L: |
| 1550 | hw->mac_type = e1000_82573; |
| 1551 | break; |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 1552 | case E1000_DEV_ID_82574L: |
| 1553 | hw->mac_type = e1000_82574; |
| 1554 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1555 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: |
| 1556 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: |
| 1557 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: |
| 1558 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
| 1559 | hw->mac_type = e1000_80003es2lan; |
| 1560 | break; |
| 1561 | case E1000_DEV_ID_ICH8_IGP_M_AMT: |
| 1562 | case E1000_DEV_ID_ICH8_IGP_AMT: |
| 1563 | case E1000_DEV_ID_ICH8_IGP_C: |
| 1564 | case E1000_DEV_ID_ICH8_IFE: |
| 1565 | case E1000_DEV_ID_ICH8_IFE_GT: |
| 1566 | case E1000_DEV_ID_ICH8_IFE_G: |
| 1567 | case E1000_DEV_ID_ICH8_IGP_M: |
| 1568 | hw->mac_type = e1000_ich8lan; |
| 1569 | break; |
Marcel Ziswiler | b9f6623 | 2014-09-08 00:03:50 +0200 | [diff] [blame] | 1570 | case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: |
| 1571 | case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1572 | case PCI_DEVICE_ID_INTEL_I210_COPPER: |
Marcel Ziswiler | b9f6623 | 2014-09-08 00:03:50 +0200 | [diff] [blame] | 1573 | case PCI_DEVICE_ID_INTEL_I211_COPPER: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1574 | case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: |
| 1575 | case PCI_DEVICE_ID_INTEL_I210_SERDES: |
| 1576 | case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: |
| 1577 | case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: |
| 1578 | hw->mac_type = e1000_igb; |
| 1579 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1580 | default: |
| 1581 | /* Should never have loaded on this device */ |
| 1582 | return -E1000_ERR_MAC_TYPE; |
| 1583 | } |
| 1584 | return E1000_SUCCESS; |
| 1585 | } |
| 1586 | |
| 1587 | /****************************************************************************** |
| 1588 | * Reset the transmit and receive units; mask and clear all interrupts. |
| 1589 | * |
| 1590 | * hw - Struct containing variables accessed by shared code |
| 1591 | *****************************************************************************/ |
| 1592 | void |
| 1593 | e1000_reset_hw(struct e1000_hw *hw) |
| 1594 | { |
| 1595 | uint32_t ctrl; |
| 1596 | uint32_t ctrl_ext; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1597 | uint32_t manc; |
Roy Zang | 966172e | 2009-08-22 03:49:52 +0800 | [diff] [blame] | 1598 | uint32_t pba = 0; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1599 | uint32_t reg; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1600 | |
| 1601 | DEBUGFUNC(); |
| 1602 | |
Roy Zang | 966172e | 2009-08-22 03:49:52 +0800 | [diff] [blame] | 1603 | /* get the correct pba value for both PCI and PCIe*/ |
| 1604 | if (hw->mac_type < e1000_82571) |
| 1605 | pba = E1000_DEFAULT_PCI_PBA; |
| 1606 | else |
| 1607 | pba = E1000_DEFAULT_PCIE_PBA; |
| 1608 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1609 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
| 1610 | if (hw->mac_type == e1000_82542_rev2_0) { |
| 1611 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 1612 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, |
| 1613 | hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1614 | } |
| 1615 | |
| 1616 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 1617 | DEBUGOUT("Masking off all interrupts\n"); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1618 | if (hw->mac_type == e1000_igb) |
| 1619 | E1000_WRITE_REG(hw, I210_IAM, 0); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1620 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 1621 | |
| 1622 | /* Disable the Transmit and Receive units. Then delay to allow |
| 1623 | * any pending transactions to complete before we hit the MAC with |
| 1624 | * the global reset. |
| 1625 | */ |
| 1626 | E1000_WRITE_REG(hw, RCTL, 0); |
| 1627 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); |
| 1628 | E1000_WRITE_FLUSH(hw); |
| 1629 | |
Christian Gmeiner | 7c7b3c9 | 2020-10-06 16:08:35 +0200 | [diff] [blame] | 1630 | if (hw->mac_type == e1000_igb) { |
| 1631 | E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT); |
| 1632 | E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT); |
| 1633 | } |
| 1634 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1635 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 1636 | hw->tbi_compatibility_on = false; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1637 | |
| 1638 | /* Delay to allow any outstanding PCI transactions to complete before |
| 1639 | * resetting the device |
| 1640 | */ |
| 1641 | mdelay(10); |
| 1642 | |
| 1643 | /* Issue a global reset to the MAC. This will reset the chip's |
| 1644 | * transmit, receive, DMA, and link units. It will not effect |
| 1645 | * the current PCI configuration. The global reset bit is self- |
| 1646 | * clearing, and should clear within a microsecond. |
| 1647 | */ |
| 1648 | DEBUGOUT("Issuing a global reset to MAC\n"); |
| 1649 | ctrl = E1000_READ_REG(hw, CTRL); |
| 1650 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1651 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1652 | |
| 1653 | /* Force a reload from the EEPROM if necessary */ |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1654 | if (hw->mac_type == e1000_igb) { |
| 1655 | mdelay(20); |
| 1656 | reg = E1000_READ_REG(hw, STATUS); |
| 1657 | if (reg & E1000_STATUS_PF_RST_DONE) |
| 1658 | DEBUGOUT("PF OK\n"); |
| 1659 | reg = E1000_READ_REG(hw, I210_EECD); |
| 1660 | if (reg & E1000_EECD_AUTO_RD) |
| 1661 | DEBUGOUT("EEC OK\n"); |
| 1662 | } else if (hw->mac_type < e1000_82540) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1663 | /* Wait for reset to complete */ |
| 1664 | udelay(10); |
| 1665 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 1666 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
| 1667 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 1668 | E1000_WRITE_FLUSH(hw); |
| 1669 | /* Wait for EEPROM reload */ |
| 1670 | mdelay(2); |
| 1671 | } else { |
| 1672 | /* Wait for EEPROM reload (it happens automatically) */ |
| 1673 | mdelay(4); |
| 1674 | /* Dissable HW ARPs on ASF enabled adapters */ |
| 1675 | manc = E1000_READ_REG(hw, MANC); |
| 1676 | manc &= ~(E1000_MANC_ARP_EN); |
| 1677 | E1000_WRITE_REG(hw, MANC, manc); |
| 1678 | } |
| 1679 | |
| 1680 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 1681 | DEBUGOUT("Masking off all interrupts\n"); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1682 | if (hw->mac_type == e1000_igb) |
| 1683 | E1000_WRITE_REG(hw, I210_IAM, 0); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1684 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 1685 | |
| 1686 | /* Clear any pending interrupt events. */ |
Zang Roy-R61911 | e36d67c | 2011-11-06 22:22:36 +0000 | [diff] [blame] | 1687 | E1000_READ_REG(hw, ICR); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1688 | |
| 1689 | /* If MWI was previously enabled, reenable it. */ |
| 1690 | if (hw->mac_type == e1000_82542_rev2_0) { |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 1691 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1692 | } |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1693 | if (hw->mac_type != e1000_igb) |
| 1694 | E1000_WRITE_REG(hw, PBA, pba); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1695 | } |
| 1696 | |
| 1697 | /****************************************************************************** |
| 1698 | * |
| 1699 | * Initialize a number of hardware-dependent bits |
| 1700 | * |
| 1701 | * hw: Struct containing variables accessed by shared code |
| 1702 | * |
| 1703 | * This function contains hardware limitation workarounds for PCI-E adapters |
| 1704 | * |
| 1705 | *****************************************************************************/ |
| 1706 | static void |
| 1707 | e1000_initialize_hardware_bits(struct e1000_hw *hw) |
| 1708 | { |
| 1709 | if ((hw->mac_type >= e1000_82571) && |
| 1710 | (!hw->initialize_hw_bits_disable)) { |
| 1711 | /* Settings common to all PCI-express silicon */ |
| 1712 | uint32_t reg_ctrl, reg_ctrl_ext; |
| 1713 | uint32_t reg_tarc0, reg_tarc1; |
| 1714 | uint32_t reg_tctl; |
| 1715 | uint32_t reg_txdctl, reg_txdctl1; |
| 1716 | |
| 1717 | /* link autonegotiation/sync workarounds */ |
| 1718 | reg_tarc0 = E1000_READ_REG(hw, TARC0); |
| 1719 | reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
| 1720 | |
| 1721 | /* Enable not-done TX descriptor counting */ |
| 1722 | reg_txdctl = E1000_READ_REG(hw, TXDCTL); |
| 1723 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC; |
| 1724 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); |
| 1725 | |
| 1726 | reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); |
| 1727 | reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; |
| 1728 | E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); |
| 1729 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1730 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1731 | switch (hw->mac_type) { |
Andre Przywara | 4b307c1 | 2016-11-16 00:50:07 +0000 | [diff] [blame] | 1732 | case e1000_igb: /* IGB is cool */ |
| 1733 | return; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1734 | case e1000_82571: |
| 1735 | case e1000_82572: |
| 1736 | /* Clear PHY TX compatible mode bits */ |
| 1737 | reg_tarc1 = E1000_READ_REG(hw, TARC1); |
| 1738 | reg_tarc1 &= ~((1 << 30)|(1 << 29)); |
| 1739 | |
| 1740 | /* link autonegotiation/sync workarounds */ |
| 1741 | reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); |
| 1742 | |
| 1743 | /* TX ring control fixes */ |
| 1744 | reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); |
| 1745 | |
| 1746 | /* Multiple read bit is reversed polarity */ |
| 1747 | reg_tctl = E1000_READ_REG(hw, TCTL); |
| 1748 | if (reg_tctl & E1000_TCTL_MULR) |
| 1749 | reg_tarc1 &= ~(1 << 28); |
| 1750 | else |
| 1751 | reg_tarc1 |= (1 << 28); |
| 1752 | |
| 1753 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
| 1754 | break; |
| 1755 | case e1000_82573: |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 1756 | case e1000_82574: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1757 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 1758 | reg_ctrl_ext &= ~(1 << 23); |
| 1759 | reg_ctrl_ext |= (1 << 22); |
| 1760 | |
| 1761 | /* TX byte count fix */ |
| 1762 | reg_ctrl = E1000_READ_REG(hw, CTRL); |
| 1763 | reg_ctrl &= ~(1 << 29); |
| 1764 | |
| 1765 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); |
| 1766 | E1000_WRITE_REG(hw, CTRL, reg_ctrl); |
| 1767 | break; |
| 1768 | case e1000_80003es2lan: |
| 1769 | /* improve small packet performace for fiber/serdes */ |
| 1770 | if ((hw->media_type == e1000_media_type_fiber) |
| 1771 | || (hw->media_type == |
| 1772 | e1000_media_type_internal_serdes)) { |
| 1773 | reg_tarc0 &= ~(1 << 20); |
| 1774 | } |
| 1775 | |
| 1776 | /* Multiple read bit is reversed polarity */ |
| 1777 | reg_tctl = E1000_READ_REG(hw, TCTL); |
| 1778 | reg_tarc1 = E1000_READ_REG(hw, TARC1); |
| 1779 | if (reg_tctl & E1000_TCTL_MULR) |
| 1780 | reg_tarc1 &= ~(1 << 28); |
| 1781 | else |
| 1782 | reg_tarc1 |= (1 << 28); |
| 1783 | |
| 1784 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
| 1785 | break; |
| 1786 | case e1000_ich8lan: |
| 1787 | /* Reduce concurrent DMA requests to 3 from 4 */ |
| 1788 | if ((hw->revision_id < 3) || |
| 1789 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && |
| 1790 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) |
| 1791 | reg_tarc0 |= ((1 << 29)|(1 << 28)); |
| 1792 | |
| 1793 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 1794 | reg_ctrl_ext |= (1 << 22); |
| 1795 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); |
| 1796 | |
| 1797 | /* workaround TX hang with TSO=on */ |
| 1798 | reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); |
| 1799 | |
| 1800 | /* Multiple read bit is reversed polarity */ |
| 1801 | reg_tctl = E1000_READ_REG(hw, TCTL); |
| 1802 | reg_tarc1 = E1000_READ_REG(hw, TARC1); |
| 1803 | if (reg_tctl & E1000_TCTL_MULR) |
| 1804 | reg_tarc1 &= ~(1 << 28); |
| 1805 | else |
| 1806 | reg_tarc1 |= (1 << 28); |
| 1807 | |
| 1808 | /* workaround TX hang with TSO=on */ |
| 1809 | reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); |
| 1810 | |
| 1811 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
| 1812 | break; |
| 1813 | default: |
| 1814 | break; |
| 1815 | } |
| 1816 | |
| 1817 | E1000_WRITE_REG(hw, TARC0, reg_tarc0); |
| 1818 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1819 | } |
| 1820 | |
| 1821 | /****************************************************************************** |
| 1822 | * Performs basic configuration of the adapter. |
| 1823 | * |
| 1824 | * hw - Struct containing variables accessed by shared code |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1825 | * |
| 1826 | * Assumes that the controller has previously been reset and is in a |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1827 | * post-reset uninitialized state. Initializes the receive address registers, |
| 1828 | * multicast table, and VLAN filter table. Calls routines to setup link |
| 1829 | * configuration and flow control settings. Clears all on-chip counters. Leaves |
| 1830 | * the transmit and receive units disabled and uninitialized. |
| 1831 | *****************************************************************************/ |
| 1832 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1833 | e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1834 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1835 | uint32_t ctrl; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1836 | uint32_t i; |
| 1837 | int32_t ret_val; |
| 1838 | uint16_t pcix_cmd_word; |
| 1839 | uint16_t pcix_stat_hi_word; |
| 1840 | uint16_t cmd_mmrbc; |
| 1841 | uint16_t stat_mmrbc; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1842 | uint32_t mta_size; |
| 1843 | uint32_t reg_data; |
| 1844 | uint32_t ctrl_ext; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1845 | DEBUGFUNC(); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1846 | /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ |
| 1847 | if ((hw->mac_type == e1000_ich8lan) && |
| 1848 | ((hw->revision_id < 3) || |
| 1849 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && |
| 1850 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { |
| 1851 | reg_data = E1000_READ_REG(hw, STATUS); |
| 1852 | reg_data &= ~0x80000000; |
| 1853 | E1000_WRITE_REG(hw, STATUS, reg_data); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1854 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1855 | /* Do not need initialize Identification LED */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1856 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1857 | /* Set the media type and TBI compatibility */ |
| 1858 | e1000_set_media_type(hw); |
| 1859 | |
| 1860 | /* Must be called after e1000_set_media_type |
| 1861 | * because media_type is used */ |
| 1862 | e1000_initialize_hardware_bits(hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1863 | |
| 1864 | /* Disabling VLAN filtering. */ |
| 1865 | DEBUGOUT("Initializing the IEEE VLAN\n"); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1866 | /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
| 1867 | if (hw->mac_type != e1000_ich8lan) { |
| 1868 | if (hw->mac_type < e1000_82545_rev_3) |
| 1869 | E1000_WRITE_REG(hw, VET, 0); |
| 1870 | e1000_clear_vfta(hw); |
| 1871 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1872 | |
| 1873 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
| 1874 | if (hw->mac_type == e1000_82542_rev2_0) { |
| 1875 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 1876 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, |
| 1877 | hw-> |
| 1878 | pci_cmd_word & ~PCI_COMMAND_INVALIDATE); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1879 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
| 1880 | E1000_WRITE_FLUSH(hw); |
| 1881 | mdelay(5); |
| 1882 | } |
| 1883 | |
| 1884 | /* Setup the receive address. This involves initializing all of the Receive |
| 1885 | * Address Registers (RARs 0 - 15). |
| 1886 | */ |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1887 | e1000_init_rx_addrs(hw, enetaddr); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1888 | |
| 1889 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
| 1890 | if (hw->mac_type == e1000_82542_rev2_0) { |
| 1891 | E1000_WRITE_REG(hw, RCTL, 0); |
| 1892 | E1000_WRITE_FLUSH(hw); |
| 1893 | mdelay(1); |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 1894 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1895 | } |
| 1896 | |
| 1897 | /* Zero out the Multicast HASH table */ |
| 1898 | DEBUGOUT("Zeroing the MTA\n"); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1899 | mta_size = E1000_MC_TBL_SIZE; |
| 1900 | if (hw->mac_type == e1000_ich8lan) |
| 1901 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN; |
| 1902 | for (i = 0; i < mta_size; i++) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1903 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1904 | /* use write flush to prevent Memory Write Block (MWB) from |
| 1905 | * occuring when accessing our register space */ |
| 1906 | E1000_WRITE_FLUSH(hw); |
| 1907 | } |
Bin Meng | 1ba7e95 | 2015-11-16 01:19:16 -0800 | [diff] [blame] | 1908 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1909 | switch (hw->mac_type) { |
| 1910 | case e1000_82545_rev_3: |
| 1911 | case e1000_82546_rev_3: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1912 | case e1000_igb: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1913 | break; |
| 1914 | default: |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1915 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1916 | if (hw->bus_type == e1000_bus_type_pcix) { |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 1917 | dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, |
| 1918 | &pcix_cmd_word); |
| 1919 | dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, |
| 1920 | &pcix_stat_hi_word); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1921 | cmd_mmrbc = |
| 1922 | (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> |
| 1923 | PCIX_COMMAND_MMRBC_SHIFT; |
| 1924 | stat_mmrbc = |
| 1925 | (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> |
| 1926 | PCIX_STATUS_HI_MMRBC_SHIFT; |
| 1927 | if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) |
| 1928 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; |
| 1929 | if (cmd_mmrbc > stat_mmrbc) { |
| 1930 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; |
| 1931 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 1932 | dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, |
| 1933 | pcix_cmd_word); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1934 | } |
| 1935 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1936 | break; |
| 1937 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1938 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1939 | /* More time needed for PHY to initialize */ |
| 1940 | if (hw->mac_type == e1000_ich8lan) |
| 1941 | mdelay(15); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 1942 | if (hw->mac_type == e1000_igb) |
| 1943 | mdelay(15); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1944 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1945 | /* Call a subroutine to configure the link and setup flow control. */ |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 1946 | ret_val = e1000_setup_link(hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1947 | |
| 1948 | /* Set the transmit descriptor write-back policy */ |
| 1949 | if (hw->mac_type > e1000_82544) { |
| 1950 | ctrl = E1000_READ_REG(hw, TXDCTL); |
| 1951 | ctrl = |
| 1952 | (ctrl & ~E1000_TXDCTL_WTHRESH) | |
| 1953 | E1000_TXDCTL_FULL_TX_DESC_WB; |
| 1954 | E1000_WRITE_REG(hw, TXDCTL, ctrl); |
| 1955 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1956 | |
Ruchika Gupta | ed1f72f | 2012-04-19 02:27:11 +0000 | [diff] [blame] | 1957 | /* Set the receive descriptor write back policy */ |
Ruchika Gupta | ed1f72f | 2012-04-19 02:27:11 +0000 | [diff] [blame] | 1958 | if (hw->mac_type >= e1000_82571) { |
| 1959 | ctrl = E1000_READ_REG(hw, RXDCTL); |
| 1960 | ctrl = |
| 1961 | (ctrl & ~E1000_RXDCTL_WTHRESH) | |
| 1962 | E1000_RXDCTL_FULL_RX_DESC_WB; |
| 1963 | E1000_WRITE_REG(hw, RXDCTL, ctrl); |
| 1964 | } |
| 1965 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1966 | switch (hw->mac_type) { |
| 1967 | default: |
| 1968 | break; |
| 1969 | case e1000_80003es2lan: |
| 1970 | /* Enable retransmit on late collisions */ |
| 1971 | reg_data = E1000_READ_REG(hw, TCTL); |
| 1972 | reg_data |= E1000_TCTL_RTLC; |
| 1973 | E1000_WRITE_REG(hw, TCTL, reg_data); |
| 1974 | |
| 1975 | /* Configure Gigabit Carry Extend Padding */ |
| 1976 | reg_data = E1000_READ_REG(hw, TCTL_EXT); |
| 1977 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; |
| 1978 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; |
| 1979 | E1000_WRITE_REG(hw, TCTL_EXT, reg_data); |
| 1980 | |
| 1981 | /* Configure Transmit Inter-Packet Gap */ |
| 1982 | reg_data = E1000_READ_REG(hw, TIPG); |
| 1983 | reg_data &= ~E1000_TIPG_IPGT_MASK; |
| 1984 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
| 1985 | E1000_WRITE_REG(hw, TIPG, reg_data); |
| 1986 | |
| 1987 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); |
| 1988 | reg_data &= ~0x00100000; |
| 1989 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); |
| 1990 | /* Fall through */ |
| 1991 | case e1000_82571: |
| 1992 | case e1000_82572: |
| 1993 | case e1000_ich8lan: |
| 1994 | ctrl = E1000_READ_REG(hw, TXDCTL1); |
| 1995 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) |
| 1996 | | E1000_TXDCTL_FULL_TX_DESC_WB; |
| 1997 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); |
| 1998 | break; |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 1999 | case e1000_82573: |
| 2000 | case e1000_82574: |
| 2001 | reg_data = E1000_READ_REG(hw, GCR); |
| 2002 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
| 2003 | E1000_WRITE_REG(hw, GCR, reg_data); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2004 | case e1000_igb: |
| 2005 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2006 | } |
| 2007 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2008 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
| 2009 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
| 2010 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 2011 | /* Relaxed ordering must be disabled to avoid a parity |
| 2012 | * error crash in a PCI slot. */ |
| 2013 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
| 2014 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 2015 | } |
| 2016 | |
| 2017 | return ret_val; |
| 2018 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2019 | |
| 2020 | /****************************************************************************** |
| 2021 | * Configures flow control and link settings. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2022 | * |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2023 | * hw - Struct containing variables accessed by shared code |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2024 | * |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2025 | * Determines which flow control settings to use. Calls the apropriate media- |
| 2026 | * specific link configuration function. Configures the flow control settings. |
| 2027 | * Assuming the adapter has a valid link partner, a valid link should be |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2028 | * established. Assumes the hardware has previously been reset and the |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2029 | * transmitter and receiver are not enabled. |
| 2030 | *****************************************************************************/ |
| 2031 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 2032 | e1000_setup_link(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2033 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2034 | int32_t ret_val; |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2035 | #ifndef CONFIG_E1000_NO_NVM |
| 2036 | uint32_t ctrl_ext; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2037 | uint16_t eeprom_data; |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2038 | #endif |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2039 | |
| 2040 | DEBUGFUNC(); |
| 2041 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2042 | /* In the case of the phy reset being blocked, we already have a link. |
| 2043 | * We do not have to set it up again. */ |
| 2044 | if (e1000_check_phy_reset_block(hw)) |
| 2045 | return E1000_SUCCESS; |
| 2046 | |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2047 | #ifndef CONFIG_E1000_NO_NVM |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2048 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
| 2049 | * that determine the hardware's default PAUSE (flow control) mode, |
| 2050 | * a bit that determines whether the HW defaults to enabling or |
| 2051 | * disabling auto-negotiation, and the direction of the |
| 2052 | * SW defined pins. If there is no SW over-ride of the flow |
| 2053 | * control setting, then the variable hw->fc will |
| 2054 | * be initialized based on a value in the EEPROM. |
| 2055 | */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2056 | if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, |
| 2057 | &eeprom_data) < 0) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2058 | DEBUGOUT("EEPROM Read Error\n"); |
| 2059 | return -E1000_ERR_EEPROM; |
| 2060 | } |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2061 | #endif |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2062 | if (hw->fc == e1000_fc_default) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2063 | switch (hw->mac_type) { |
| 2064 | case e1000_ich8lan: |
| 2065 | case e1000_82573: |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 2066 | case e1000_82574: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2067 | case e1000_igb: |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2068 | hw->fc = e1000_fc_full; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2069 | break; |
| 2070 | default: |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2071 | #ifndef CONFIG_E1000_NO_NVM |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2072 | ret_val = e1000_read_eeprom(hw, |
| 2073 | EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); |
| 2074 | if (ret_val) { |
| 2075 | DEBUGOUT("EEPROM Read Error\n"); |
| 2076 | return -E1000_ERR_EEPROM; |
| 2077 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2078 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
| 2079 | hw->fc = e1000_fc_none; |
| 2080 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
| 2081 | EEPROM_WORD0F_ASM_DIR) |
| 2082 | hw->fc = e1000_fc_tx_pause; |
| 2083 | else |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2084 | #endif |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2085 | hw->fc = e1000_fc_full; |
| 2086 | break; |
| 2087 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2088 | } |
| 2089 | |
| 2090 | /* We want to save off the original Flow Control configuration just |
| 2091 | * in case we get disconnected and then reconnected into a different |
| 2092 | * hub or switch with different Flow Control capabilities. |
| 2093 | */ |
| 2094 | if (hw->mac_type == e1000_82542_rev2_0) |
| 2095 | hw->fc &= (~e1000_fc_tx_pause); |
| 2096 | |
| 2097 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
| 2098 | hw->fc &= (~e1000_fc_rx_pause); |
| 2099 | |
| 2100 | hw->original_fc = hw->fc; |
| 2101 | |
| 2102 | DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); |
| 2103 | |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2104 | #ifndef CONFIG_E1000_NO_NVM |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2105 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
| 2106 | * polarity value for the SW controlled pins, and setup the |
| 2107 | * Extended Device Control reg with that info. |
| 2108 | * This is needed because one of the SW controlled pins is used for |
| 2109 | * signal detection. So this should be done before e1000_setup_pcs_link() |
| 2110 | * or e1000_phy_setup() is called. |
| 2111 | */ |
| 2112 | if (hw->mac_type == e1000_82543) { |
| 2113 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
| 2114 | SWDPIO__EXT_SHIFT); |
| 2115 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 2116 | } |
Rojhalat Ibrahim | bbcd2b0 | 2013-10-07 18:30:39 +0200 | [diff] [blame] | 2117 | #endif |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2118 | |
| 2119 | /* Call the necessary subroutine to configure the link. */ |
| 2120 | ret_val = (hw->media_type == e1000_media_type_fiber) ? |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 2121 | e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2122 | if (ret_val < 0) { |
| 2123 | return ret_val; |
| 2124 | } |
| 2125 | |
| 2126 | /* Initialize the flow control address, type, and PAUSE timer |
| 2127 | * registers to their default values. This is done even if flow |
| 2128 | * control is disabled, because it does not hurt anything to |
| 2129 | * initialize these registers. |
| 2130 | */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2131 | DEBUGOUT("Initializing the Flow Control address, type" |
| 2132 | "and timer regs\n"); |
| 2133 | |
| 2134 | /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ |
| 2135 | if (hw->mac_type != e1000_ich8lan) { |
| 2136 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); |
| 2137 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 2138 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 2139 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2140 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2141 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
| 2142 | |
| 2143 | /* Set the flow control receive threshold registers. Normally, |
| 2144 | * these registers will be set to a default threshold that may be |
| 2145 | * adjusted later by the driver's runtime code. However, if the |
| 2146 | * ability to transmit pause frames in not enabled, then these |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2147 | * registers will be set to 0. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2148 | */ |
| 2149 | if (!(hw->fc & e1000_fc_tx_pause)) { |
| 2150 | E1000_WRITE_REG(hw, FCRTL, 0); |
| 2151 | E1000_WRITE_REG(hw, FCRTH, 0); |
| 2152 | } else { |
| 2153 | /* We need to set up the Receive Threshold high and low water marks |
| 2154 | * as well as (optionally) enabling the transmission of XON frames. |
| 2155 | */ |
| 2156 | if (hw->fc_send_xon) { |
| 2157 | E1000_WRITE_REG(hw, FCRTL, |
| 2158 | (hw->fc_low_water | E1000_FCRTL_XONE)); |
| 2159 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
| 2160 | } else { |
| 2161 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); |
| 2162 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
| 2163 | } |
| 2164 | } |
| 2165 | return ret_val; |
| 2166 | } |
| 2167 | |
| 2168 | /****************************************************************************** |
| 2169 | * Sets up link for a fiber based adapter |
| 2170 | * |
| 2171 | * hw - Struct containing variables accessed by shared code |
| 2172 | * |
| 2173 | * Manipulates Physical Coding Sublayer functions in order to configure |
| 2174 | * link. Assumes the hardware has been previously reset and the transmitter |
| 2175 | * and receiver are not enabled. |
| 2176 | *****************************************************************************/ |
| 2177 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 2178 | e1000_setup_fiber_link(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2179 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2180 | uint32_t ctrl; |
| 2181 | uint32_t status; |
| 2182 | uint32_t txcw = 0; |
| 2183 | uint32_t i; |
| 2184 | uint32_t signal; |
| 2185 | int32_t ret_val; |
| 2186 | |
| 2187 | DEBUGFUNC(); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2188 | /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be |
| 2189 | * set when the optics detect a signal. On older adapters, it will be |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2190 | * cleared when there is a signal |
| 2191 | */ |
| 2192 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2193 | if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) |
| 2194 | signal = E1000_CTRL_SWDPIN1; |
| 2195 | else |
| 2196 | signal = 0; |
| 2197 | |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 2198 | printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2199 | ctrl); |
| 2200 | /* Take the link out of reset */ |
| 2201 | ctrl &= ~(E1000_CTRL_LRST); |
| 2202 | |
| 2203 | e1000_config_collision_dist(hw); |
| 2204 | |
| 2205 | /* Check for a software override of the flow control settings, and setup |
| 2206 | * the device accordingly. If auto-negotiation is enabled, then software |
| 2207 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
| 2208 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2209 | * auto-negotiation is disabled, then software will have to manually |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2210 | * configure the two flow control enable bits in the CTRL register. |
| 2211 | * |
| 2212 | * The possible values of the "fc" parameter are: |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 2213 | * 0: Flow control is completely disabled |
| 2214 | * 1: Rx flow control is enabled (we can receive pause frames, but |
| 2215 | * not send pause frames). |
| 2216 | * 2: Tx flow control is enabled (we can send pause frames but we do |
| 2217 | * not support receiving pause frames). |
| 2218 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2219 | */ |
| 2220 | switch (hw->fc) { |
| 2221 | case e1000_fc_none: |
| 2222 | /* Flow control is completely disabled by a software over-ride. */ |
| 2223 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
| 2224 | break; |
| 2225 | case e1000_fc_rx_pause: |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2226 | /* RX Flow control is enabled and TX Flow control is disabled by a |
| 2227 | * software over-ride. Since there really isn't a way to advertise |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2228 | * that we are capable of RX Pause ONLY, we will advertise that we |
| 2229 | * support both symmetric and asymmetric RX PAUSE. Later, we will |
| 2230 | * disable the adapter's ability to send PAUSE frames. |
| 2231 | */ |
| 2232 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 2233 | break; |
| 2234 | case e1000_fc_tx_pause: |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2235 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2236 | * software over-ride. |
| 2237 | */ |
| 2238 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
| 2239 | break; |
| 2240 | case e1000_fc_full: |
| 2241 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
| 2242 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 2243 | break; |
| 2244 | default: |
| 2245 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 2246 | return -E1000_ERR_CONFIG; |
| 2247 | break; |
| 2248 | } |
| 2249 | |
| 2250 | /* Since auto-negotiation is enabled, take the link out of reset (the link |
| 2251 | * will be in reset, because we previously reset the chip). This will |
| 2252 | * restart auto-negotiation. If auto-neogtiation is successful then the |
| 2253 | * link-up status bit will be set and the flow control enable bits (RFCE |
| 2254 | * and TFCE) will be set according to their negotiated value. |
| 2255 | */ |
| 2256 | DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); |
| 2257 | |
| 2258 | E1000_WRITE_REG(hw, TXCW, txcw); |
| 2259 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2260 | E1000_WRITE_FLUSH(hw); |
| 2261 | |
| 2262 | hw->txcw = txcw; |
| 2263 | mdelay(1); |
| 2264 | |
| 2265 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2266 | * indication in the Device Status Register. Time-out if a link isn't |
| 2267 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2268 | * less than 500 milliseconds even if the other end is doing it in SW). |
| 2269 | */ |
| 2270 | if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
| 2271 | DEBUGOUT("Looking for Link\n"); |
| 2272 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
| 2273 | mdelay(10); |
| 2274 | status = E1000_READ_REG(hw, STATUS); |
| 2275 | if (status & E1000_STATUS_LU) |
| 2276 | break; |
| 2277 | } |
| 2278 | if (i == (LINK_UP_TIMEOUT / 10)) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2279 | /* AutoNeg failed to achieve a link, so we'll call |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2280 | * e1000_check_for_link. This routine will force the link up if we |
| 2281 | * detect a signal. This will allow us to communicate with |
| 2282 | * non-autonegotiating link partners. |
| 2283 | */ |
| 2284 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
| 2285 | hw->autoneg_failed = 1; |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 2286 | ret_val = e1000_check_for_link(hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2287 | if (ret_val < 0) { |
| 2288 | DEBUGOUT("Error while checking for link\n"); |
| 2289 | return ret_val; |
| 2290 | } |
| 2291 | hw->autoneg_failed = 0; |
| 2292 | } else { |
| 2293 | hw->autoneg_failed = 0; |
| 2294 | DEBUGOUT("Valid Link Found\n"); |
| 2295 | } |
| 2296 | } else { |
| 2297 | DEBUGOUT("No Signal Detected\n"); |
| 2298 | return -E1000_ERR_NOLINK; |
| 2299 | } |
| 2300 | return 0; |
| 2301 | } |
| 2302 | |
| 2303 | /****************************************************************************** |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2304 | * Make sure we have a valid PHY and change PHY mode before link setup. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2305 | * |
| 2306 | * hw - Struct containing variables accessed by shared code |
| 2307 | ******************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2308 | static int32_t |
| 2309 | e1000_copper_link_preconfig(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2310 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2311 | uint32_t ctrl; |
| 2312 | int32_t ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2313 | uint16_t phy_data; |
| 2314 | |
| 2315 | DEBUGFUNC(); |
| 2316 | |
| 2317 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2318 | /* With 82543, we need to force speed and duplex on the MAC equal to what |
| 2319 | * the PHY speed and duplex configuration is. In addition, we need to |
| 2320 | * perform a hardware reset on the PHY to take it out of reset. |
| 2321 | */ |
| 2322 | if (hw->mac_type > e1000_82543) { |
| 2323 | ctrl |= E1000_CTRL_SLU; |
| 2324 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 2325 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2326 | } else { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2327 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
| 2328 | | E1000_CTRL_SLU); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2329 | E1000_WRITE_REG(hw, CTRL, ctrl); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2330 | ret_val = e1000_phy_hw_reset(hw); |
| 2331 | if (ret_val) |
| 2332 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2333 | } |
| 2334 | |
| 2335 | /* Make sure we have a valid PHY */ |
| 2336 | ret_val = e1000_detect_gig_phy(hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2337 | if (ret_val) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2338 | DEBUGOUT("Error, did not detect valid phy.\n"); |
| 2339 | return ret_val; |
| 2340 | } |
Minghuan Lian | 674bcd5 | 2015-03-19 09:43:51 -0700 | [diff] [blame] | 2341 | DEBUGOUT("Phy ID = %x\n", hw->phy_id); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2342 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2343 | /* Set PHY to class A mode (if necessary) */ |
| 2344 | ret_val = e1000_set_phy_mode(hw); |
| 2345 | if (ret_val) |
| 2346 | return ret_val; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2347 | if ((hw->mac_type == e1000_82545_rev_3) || |
| 2348 | (hw->mac_type == e1000_82546_rev_3)) { |
| 2349 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, |
| 2350 | &phy_data); |
| 2351 | phy_data |= 0x00000008; |
| 2352 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, |
| 2353 | phy_data); |
| 2354 | } |
| 2355 | |
| 2356 | if (hw->mac_type <= e1000_82543 || |
| 2357 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || |
| 2358 | hw->mac_type == e1000_82541_rev_2 |
| 2359 | || hw->mac_type == e1000_82547_rev_2) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2360 | hw->phy_reset_disable = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2361 | |
| 2362 | return E1000_SUCCESS; |
| 2363 | } |
| 2364 | |
| 2365 | /***************************************************************************** |
| 2366 | * |
| 2367 | * This function sets the lplu state according to the active flag. When |
| 2368 | * activating lplu this function also disables smart speed and vise versa. |
| 2369 | * lplu will not be activated unless the device autonegotiation advertisment |
| 2370 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 2371 | * hw: Struct containing variables accessed by shared code |
| 2372 | * active - true to enable lplu false to disable lplu. |
| 2373 | * |
| 2374 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 2375 | * E1000_SUCCESS at any other case. |
| 2376 | * |
| 2377 | ****************************************************************************/ |
| 2378 | |
| 2379 | static int32_t |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2380 | e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2381 | { |
| 2382 | uint32_t phy_ctrl = 0; |
| 2383 | int32_t ret_val; |
| 2384 | uint16_t phy_data; |
| 2385 | DEBUGFUNC(); |
| 2386 | |
| 2387 | if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 |
| 2388 | && hw->phy_type != e1000_phy_igp_3) |
| 2389 | return E1000_SUCCESS; |
| 2390 | |
| 2391 | /* During driver activity LPLU should not be used or it will attain link |
| 2392 | * from the lowest speeds starting from 10Mbps. The capability is used |
| 2393 | * for Dx transitions and states */ |
| 2394 | if (hw->mac_type == e1000_82541_rev_2 |
| 2395 | || hw->mac_type == e1000_82547_rev_2) { |
| 2396 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 2397 | &phy_data); |
| 2398 | if (ret_val) |
| 2399 | return ret_val; |
| 2400 | } else if (hw->mac_type == e1000_ich8lan) { |
| 2401 | /* MAC writes into PHY register based on the state transition |
| 2402 | * and start auto-negotiation. SW driver can overwrite the |
| 2403 | * settings in CSR PHY power control E1000_PHY_CTRL register. */ |
| 2404 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
| 2405 | } else { |
| 2406 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
| 2407 | &phy_data); |
| 2408 | if (ret_val) |
| 2409 | return ret_val; |
| 2410 | } |
| 2411 | |
| 2412 | if (!active) { |
| 2413 | if (hw->mac_type == e1000_82541_rev_2 || |
| 2414 | hw->mac_type == e1000_82547_rev_2) { |
| 2415 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
| 2416 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 2417 | phy_data); |
| 2418 | if (ret_val) |
| 2419 | return ret_val; |
| 2420 | } else { |
| 2421 | if (hw->mac_type == e1000_ich8lan) { |
| 2422 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
| 2423 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
| 2424 | } else { |
| 2425 | phy_data &= ~IGP02E1000_PM_D3_LPLU; |
| 2426 | ret_val = e1000_write_phy_reg(hw, |
| 2427 | IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 2428 | if (ret_val) |
| 2429 | return ret_val; |
| 2430 | } |
| 2431 | } |
| 2432 | |
| 2433 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
| 2434 | * Dx states where the power conservation is most important. During |
| 2435 | * driver activity we should enable SmartSpeed, so performance is |
| 2436 | * maintained. */ |
| 2437 | if (hw->smart_speed == e1000_smart_speed_on) { |
| 2438 | ret_val = e1000_read_phy_reg(hw, |
| 2439 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
| 2440 | if (ret_val) |
| 2441 | return ret_val; |
| 2442 | |
| 2443 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 2444 | ret_val = e1000_write_phy_reg(hw, |
| 2445 | IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 2446 | if (ret_val) |
| 2447 | return ret_val; |
| 2448 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
| 2449 | ret_val = e1000_read_phy_reg(hw, |
| 2450 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
| 2451 | if (ret_val) |
| 2452 | return ret_val; |
| 2453 | |
| 2454 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 2455 | ret_val = e1000_write_phy_reg(hw, |
| 2456 | IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 2457 | if (ret_val) |
| 2458 | return ret_val; |
| 2459 | } |
| 2460 | |
| 2461 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) |
| 2462 | || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || |
| 2463 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { |
| 2464 | |
| 2465 | if (hw->mac_type == e1000_82541_rev_2 || |
| 2466 | hw->mac_type == e1000_82547_rev_2) { |
| 2467 | phy_data |= IGP01E1000_GMII_FLEX_SPD; |
| 2468 | ret_val = e1000_write_phy_reg(hw, |
| 2469 | IGP01E1000_GMII_FIFO, phy_data); |
| 2470 | if (ret_val) |
| 2471 | return ret_val; |
| 2472 | } else { |
| 2473 | if (hw->mac_type == e1000_ich8lan) { |
| 2474 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; |
| 2475 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
| 2476 | } else { |
| 2477 | phy_data |= IGP02E1000_PM_D3_LPLU; |
| 2478 | ret_val = e1000_write_phy_reg(hw, |
| 2479 | IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 2480 | if (ret_val) |
| 2481 | return ret_val; |
| 2482 | } |
| 2483 | } |
| 2484 | |
| 2485 | /* When LPLU is enabled we should disable SmartSpeed */ |
| 2486 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 2487 | &phy_data); |
| 2488 | if (ret_val) |
| 2489 | return ret_val; |
| 2490 | |
| 2491 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 2492 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 2493 | phy_data); |
| 2494 | if (ret_val) |
| 2495 | return ret_val; |
| 2496 | } |
| 2497 | return E1000_SUCCESS; |
| 2498 | } |
| 2499 | |
| 2500 | /***************************************************************************** |
| 2501 | * |
| 2502 | * This function sets the lplu d0 state according to the active flag. When |
| 2503 | * activating lplu this function also disables smart speed and vise versa. |
| 2504 | * lplu will not be activated unless the device autonegotiation advertisment |
| 2505 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 2506 | * hw: Struct containing variables accessed by shared code |
| 2507 | * active - true to enable lplu false to disable lplu. |
| 2508 | * |
| 2509 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 2510 | * E1000_SUCCESS at any other case. |
| 2511 | * |
| 2512 | ****************************************************************************/ |
| 2513 | |
| 2514 | static int32_t |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2515 | e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2516 | { |
| 2517 | uint32_t phy_ctrl = 0; |
| 2518 | int32_t ret_val; |
| 2519 | uint16_t phy_data; |
| 2520 | DEBUGFUNC(); |
| 2521 | |
| 2522 | if (hw->mac_type <= e1000_82547_rev_2) |
| 2523 | return E1000_SUCCESS; |
| 2524 | |
| 2525 | if (hw->mac_type == e1000_ich8lan) { |
| 2526 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2527 | } else if (hw->mac_type == e1000_igb) { |
| 2528 | phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2529 | } else { |
| 2530 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
| 2531 | &phy_data); |
| 2532 | if (ret_val) |
| 2533 | return ret_val; |
| 2534 | } |
| 2535 | |
| 2536 | if (!active) { |
| 2537 | if (hw->mac_type == e1000_ich8lan) { |
| 2538 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
| 2539 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2540 | } else if (hw->mac_type == e1000_igb) { |
| 2541 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
| 2542 | E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2543 | } else { |
| 2544 | phy_data &= ~IGP02E1000_PM_D0_LPLU; |
| 2545 | ret_val = e1000_write_phy_reg(hw, |
| 2546 | IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 2547 | if (ret_val) |
| 2548 | return ret_val; |
| 2549 | } |
| 2550 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2551 | if (hw->mac_type == e1000_igb) |
| 2552 | return E1000_SUCCESS; |
| 2553 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2554 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
| 2555 | * Dx states where the power conservation is most important. During |
| 2556 | * driver activity we should enable SmartSpeed, so performance is |
| 2557 | * maintained. */ |
| 2558 | if (hw->smart_speed == e1000_smart_speed_on) { |
| 2559 | ret_val = e1000_read_phy_reg(hw, |
| 2560 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
| 2561 | if (ret_val) |
| 2562 | return ret_val; |
| 2563 | |
| 2564 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 2565 | ret_val = e1000_write_phy_reg(hw, |
| 2566 | IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 2567 | if (ret_val) |
| 2568 | return ret_val; |
| 2569 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
| 2570 | ret_val = e1000_read_phy_reg(hw, |
| 2571 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
| 2572 | if (ret_val) |
| 2573 | return ret_val; |
| 2574 | |
| 2575 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 2576 | ret_val = e1000_write_phy_reg(hw, |
| 2577 | IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 2578 | if (ret_val) |
| 2579 | return ret_val; |
| 2580 | } |
| 2581 | |
| 2582 | |
| 2583 | } else { |
| 2584 | |
| 2585 | if (hw->mac_type == e1000_ich8lan) { |
| 2586 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
| 2587 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2588 | } else if (hw->mac_type == e1000_igb) { |
| 2589 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
| 2590 | E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2591 | } else { |
| 2592 | phy_data |= IGP02E1000_PM_D0_LPLU; |
| 2593 | ret_val = e1000_write_phy_reg(hw, |
| 2594 | IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 2595 | if (ret_val) |
| 2596 | return ret_val; |
| 2597 | } |
| 2598 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2599 | if (hw->mac_type == e1000_igb) |
| 2600 | return E1000_SUCCESS; |
| 2601 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2602 | /* When LPLU is enabled we should disable SmartSpeed */ |
| 2603 | ret_val = e1000_read_phy_reg(hw, |
| 2604 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
| 2605 | if (ret_val) |
| 2606 | return ret_val; |
| 2607 | |
| 2608 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 2609 | ret_val = e1000_write_phy_reg(hw, |
| 2610 | IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 2611 | if (ret_val) |
| 2612 | return ret_val; |
| 2613 | |
| 2614 | } |
| 2615 | return E1000_SUCCESS; |
| 2616 | } |
| 2617 | |
| 2618 | /******************************************************************** |
| 2619 | * Copper link setup for e1000_phy_igp series. |
| 2620 | * |
| 2621 | * hw - Struct containing variables accessed by shared code |
| 2622 | *********************************************************************/ |
| 2623 | static int32_t |
| 2624 | e1000_copper_link_igp_setup(struct e1000_hw *hw) |
| 2625 | { |
| 2626 | uint32_t led_ctrl; |
| 2627 | int32_t ret_val; |
| 2628 | uint16_t phy_data; |
| 2629 | |
Timur Tabi | edc45b5 | 2009-08-17 15:55:38 -0500 | [diff] [blame] | 2630 | DEBUGFUNC(); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2631 | |
| 2632 | if (hw->phy_reset_disable) |
| 2633 | return E1000_SUCCESS; |
| 2634 | |
| 2635 | ret_val = e1000_phy_reset(hw); |
| 2636 | if (ret_val) { |
| 2637 | DEBUGOUT("Error Resetting the PHY\n"); |
| 2638 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2639 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2640 | |
| 2641 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
| 2642 | mdelay(15); |
| 2643 | if (hw->mac_type != e1000_ich8lan) { |
| 2644 | /* Configure activity LED after PHY reset */ |
| 2645 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 2646 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 2647 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 2648 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
| 2649 | } |
| 2650 | |
| 2651 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
| 2652 | if (hw->phy_type == e1000_phy_igp) { |
| 2653 | /* disable lplu d3 during driver init */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2654 | ret_val = e1000_set_d3_lplu_state(hw, false); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2655 | if (ret_val) { |
| 2656 | DEBUGOUT("Error Disabling LPLU D3\n"); |
| 2657 | return ret_val; |
| 2658 | } |
| 2659 | } |
| 2660 | |
| 2661 | /* disable lplu d0 during driver init */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2662 | ret_val = e1000_set_d0_lplu_state(hw, false); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2663 | if (ret_val) { |
| 2664 | DEBUGOUT("Error Disabling LPLU D0\n"); |
| 2665 | return ret_val; |
| 2666 | } |
| 2667 | /* Configure mdi-mdix settings */ |
| 2668 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
| 2669 | if (ret_val) |
| 2670 | return ret_val; |
| 2671 | |
| 2672 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
| 2673 | hw->dsp_config_state = e1000_dsp_config_disabled; |
| 2674 | /* Force MDI for earlier revs of the IGP PHY */ |
| 2675 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
| 2676 | | IGP01E1000_PSCR_FORCE_MDI_MDIX); |
| 2677 | hw->mdix = 1; |
| 2678 | |
| 2679 | } else { |
| 2680 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 2681 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 2682 | |
| 2683 | switch (hw->mdix) { |
| 2684 | case 1: |
| 2685 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 2686 | break; |
| 2687 | case 2: |
| 2688 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 2689 | break; |
| 2690 | case 0: |
| 2691 | default: |
| 2692 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
| 2693 | break; |
| 2694 | } |
| 2695 | } |
| 2696 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
| 2697 | if (ret_val) |
| 2698 | return ret_val; |
| 2699 | |
| 2700 | /* set auto-master slave resolution settings */ |
| 2701 | if (hw->autoneg) { |
| 2702 | e1000_ms_type phy_ms_setting = hw->master_slave; |
| 2703 | |
| 2704 | if (hw->ffe_config_state == e1000_ffe_config_active) |
| 2705 | hw->ffe_config_state = e1000_ffe_config_enabled; |
| 2706 | |
| 2707 | if (hw->dsp_config_state == e1000_dsp_config_activated) |
| 2708 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 2709 | |
| 2710 | /* when autonegotiation advertisment is only 1000Mbps then we |
| 2711 | * should disable SmartSpeed and enable Auto MasterSlave |
| 2712 | * resolution as hardware default. */ |
| 2713 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
| 2714 | /* Disable SmartSpeed */ |
| 2715 | ret_val = e1000_read_phy_reg(hw, |
| 2716 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
| 2717 | if (ret_val) |
| 2718 | return ret_val; |
| 2719 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 2720 | ret_val = e1000_write_phy_reg(hw, |
| 2721 | IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 2722 | if (ret_val) |
| 2723 | return ret_val; |
| 2724 | /* Set auto Master/Slave resolution process */ |
| 2725 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, |
| 2726 | &phy_data); |
| 2727 | if (ret_val) |
| 2728 | return ret_val; |
| 2729 | phy_data &= ~CR_1000T_MS_ENABLE; |
| 2730 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, |
| 2731 | phy_data); |
| 2732 | if (ret_val) |
| 2733 | return ret_val; |
| 2734 | } |
| 2735 | |
| 2736 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
| 2737 | if (ret_val) |
| 2738 | return ret_val; |
| 2739 | |
| 2740 | /* load defaults for future use */ |
| 2741 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
| 2742 | ((phy_data & CR_1000T_MS_VALUE) ? |
| 2743 | e1000_ms_force_master : |
| 2744 | e1000_ms_force_slave) : |
| 2745 | e1000_ms_auto; |
| 2746 | |
| 2747 | switch (phy_ms_setting) { |
| 2748 | case e1000_ms_force_master: |
| 2749 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
| 2750 | break; |
| 2751 | case e1000_ms_force_slave: |
| 2752 | phy_data |= CR_1000T_MS_ENABLE; |
| 2753 | phy_data &= ~(CR_1000T_MS_VALUE); |
| 2754 | break; |
| 2755 | case e1000_ms_auto: |
| 2756 | phy_data &= ~CR_1000T_MS_ENABLE; |
| 2757 | default: |
| 2758 | break; |
| 2759 | } |
| 2760 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
| 2761 | if (ret_val) |
| 2762 | return ret_val; |
| 2763 | } |
| 2764 | |
| 2765 | return E1000_SUCCESS; |
| 2766 | } |
| 2767 | |
| 2768 | /***************************************************************************** |
| 2769 | * This function checks the mode of the firmware. |
| 2770 | * |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2771 | * returns - true when the mode is IAMT or false. |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2772 | ****************************************************************************/ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2773 | bool |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2774 | e1000_check_mng_mode(struct e1000_hw *hw) |
| 2775 | { |
| 2776 | uint32_t fwsm; |
| 2777 | DEBUGFUNC(); |
| 2778 | |
| 2779 | fwsm = E1000_READ_REG(hw, FWSM); |
| 2780 | |
| 2781 | if (hw->mac_type == e1000_ich8lan) { |
| 2782 | if ((fwsm & E1000_FWSM_MODE_MASK) == |
| 2783 | (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2784 | return true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2785 | } else if ((fwsm & E1000_FWSM_MODE_MASK) == |
| 2786 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2787 | return true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2788 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2789 | return false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2790 | } |
| 2791 | |
| 2792 | static int32_t |
| 2793 | e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) |
| 2794 | { |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 2795 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2796 | uint32_t reg_val; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2797 | DEBUGFUNC(); |
| 2798 | |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 2799 | if (e1000_is_second_port(hw)) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2800 | swfw = E1000_SWFW_PHY1_SM; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 2801 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2802 | if (e1000_swfw_sync_acquire(hw, swfw)) |
| 2803 | return -E1000_ERR_SWFW_SYNC; |
| 2804 | |
| 2805 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) |
| 2806 | & E1000_KUMCTRLSTA_OFFSET) | data; |
| 2807 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
| 2808 | udelay(2); |
| 2809 | |
| 2810 | return E1000_SUCCESS; |
| 2811 | } |
| 2812 | |
| 2813 | static int32_t |
| 2814 | e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) |
| 2815 | { |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 2816 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2817 | uint32_t reg_val; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2818 | DEBUGFUNC(); |
| 2819 | |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 2820 | if (e1000_is_second_port(hw)) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2821 | swfw = E1000_SWFW_PHY1_SM; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 2822 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2823 | if (e1000_swfw_sync_acquire(hw, swfw)) { |
| 2824 | debug("%s[%i]\n", __func__, __LINE__); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2825 | return -E1000_ERR_SWFW_SYNC; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 2826 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2827 | |
| 2828 | /* Write register address */ |
| 2829 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
| 2830 | E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; |
| 2831 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
| 2832 | udelay(2); |
| 2833 | |
| 2834 | /* Read the data returned */ |
| 2835 | reg_val = E1000_READ_REG(hw, KUMCTRLSTA); |
| 2836 | *data = (uint16_t)reg_val; |
| 2837 | |
| 2838 | return E1000_SUCCESS; |
| 2839 | } |
| 2840 | |
| 2841 | /******************************************************************** |
| 2842 | * Copper link setup for e1000_phy_gg82563 series. |
| 2843 | * |
| 2844 | * hw - Struct containing variables accessed by shared code |
| 2845 | *********************************************************************/ |
| 2846 | static int32_t |
| 2847 | e1000_copper_link_ggp_setup(struct e1000_hw *hw) |
| 2848 | { |
| 2849 | int32_t ret_val; |
| 2850 | uint16_t phy_data; |
| 2851 | uint32_t reg_data; |
| 2852 | |
| 2853 | DEBUGFUNC(); |
| 2854 | |
| 2855 | if (!hw->phy_reset_disable) { |
| 2856 | /* Enable CRS on TX for half-duplex operation. */ |
| 2857 | ret_val = e1000_read_phy_reg(hw, |
| 2858 | GG82563_PHY_MAC_SPEC_CTRL, &phy_data); |
| 2859 | if (ret_val) |
| 2860 | return ret_val; |
| 2861 | |
| 2862 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
| 2863 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ |
| 2864 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; |
| 2865 | |
| 2866 | ret_val = e1000_write_phy_reg(hw, |
| 2867 | GG82563_PHY_MAC_SPEC_CTRL, phy_data); |
| 2868 | if (ret_val) |
| 2869 | return ret_val; |
| 2870 | |
| 2871 | /* Options: |
| 2872 | * MDI/MDI-X = 0 (default) |
| 2873 | * 0 - Auto for all speeds |
| 2874 | * 1 - MDI mode |
| 2875 | * 2 - MDI-X mode |
| 2876 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 2877 | */ |
| 2878 | ret_val = e1000_read_phy_reg(hw, |
| 2879 | GG82563_PHY_SPEC_CTRL, &phy_data); |
| 2880 | if (ret_val) |
| 2881 | return ret_val; |
| 2882 | |
| 2883 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; |
| 2884 | |
| 2885 | switch (hw->mdix) { |
| 2886 | case 1: |
| 2887 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; |
| 2888 | break; |
| 2889 | case 2: |
| 2890 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; |
| 2891 | break; |
| 2892 | case 0: |
| 2893 | default: |
| 2894 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; |
| 2895 | break; |
| 2896 | } |
| 2897 | |
| 2898 | /* Options: |
| 2899 | * disable_polarity_correction = 0 (default) |
| 2900 | * Automatic Correction for Reversed Cable Polarity |
| 2901 | * 0 - Disabled |
| 2902 | * 1 - Enabled |
| 2903 | */ |
| 2904 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
| 2905 | ret_val = e1000_write_phy_reg(hw, |
| 2906 | GG82563_PHY_SPEC_CTRL, phy_data); |
| 2907 | |
| 2908 | if (ret_val) |
| 2909 | return ret_val; |
| 2910 | |
| 2911 | /* SW Reset the PHY so all changes take effect */ |
| 2912 | ret_val = e1000_phy_reset(hw); |
| 2913 | if (ret_val) { |
| 2914 | DEBUGOUT("Error Resetting the PHY\n"); |
| 2915 | return ret_val; |
| 2916 | } |
| 2917 | } /* phy_reset_disable */ |
| 2918 | |
| 2919 | if (hw->mac_type == e1000_80003es2lan) { |
| 2920 | /* Bypass RX and TX FIFO's */ |
| 2921 | ret_val = e1000_write_kmrn_reg(hw, |
| 2922 | E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, |
| 2923 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
| 2924 | | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); |
| 2925 | if (ret_val) |
| 2926 | return ret_val; |
| 2927 | |
| 2928 | ret_val = e1000_read_phy_reg(hw, |
| 2929 | GG82563_PHY_SPEC_CTRL_2, &phy_data); |
| 2930 | if (ret_val) |
| 2931 | return ret_val; |
| 2932 | |
| 2933 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; |
| 2934 | ret_val = e1000_write_phy_reg(hw, |
| 2935 | GG82563_PHY_SPEC_CTRL_2, phy_data); |
| 2936 | |
| 2937 | if (ret_val) |
| 2938 | return ret_val; |
| 2939 | |
| 2940 | reg_data = E1000_READ_REG(hw, CTRL_EXT); |
| 2941 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); |
| 2942 | E1000_WRITE_REG(hw, CTRL_EXT, reg_data); |
| 2943 | |
| 2944 | ret_val = e1000_read_phy_reg(hw, |
| 2945 | GG82563_PHY_PWR_MGMT_CTRL, &phy_data); |
| 2946 | if (ret_val) |
| 2947 | return ret_val; |
| 2948 | |
| 2949 | /* Do not init these registers when the HW is in IAMT mode, since the |
| 2950 | * firmware will have already initialized them. We only initialize |
| 2951 | * them if the HW is not in IAMT mode. |
| 2952 | */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 2953 | if (e1000_check_mng_mode(hw) == false) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2954 | /* Enable Electrical Idle on the PHY */ |
| 2955 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; |
| 2956 | ret_val = e1000_write_phy_reg(hw, |
| 2957 | GG82563_PHY_PWR_MGMT_CTRL, phy_data); |
| 2958 | if (ret_val) |
| 2959 | return ret_val; |
| 2960 | |
| 2961 | ret_val = e1000_read_phy_reg(hw, |
| 2962 | GG82563_PHY_KMRN_MODE_CTRL, &phy_data); |
| 2963 | if (ret_val) |
| 2964 | return ret_val; |
| 2965 | |
| 2966 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
| 2967 | ret_val = e1000_write_phy_reg(hw, |
| 2968 | GG82563_PHY_KMRN_MODE_CTRL, phy_data); |
| 2969 | |
| 2970 | if (ret_val) |
| 2971 | return ret_val; |
| 2972 | } |
| 2973 | |
| 2974 | /* Workaround: Disable padding in Kumeran interface in the MAC |
| 2975 | * and in the PHY to avoid CRC errors. |
| 2976 | */ |
| 2977 | ret_val = e1000_read_phy_reg(hw, |
| 2978 | GG82563_PHY_INBAND_CTRL, &phy_data); |
| 2979 | if (ret_val) |
| 2980 | return ret_val; |
| 2981 | phy_data |= GG82563_ICR_DIS_PADDING; |
| 2982 | ret_val = e1000_write_phy_reg(hw, |
| 2983 | GG82563_PHY_INBAND_CTRL, phy_data); |
| 2984 | if (ret_val) |
| 2985 | return ret_val; |
| 2986 | } |
| 2987 | return E1000_SUCCESS; |
| 2988 | } |
| 2989 | |
| 2990 | /******************************************************************** |
| 2991 | * Copper link setup for e1000_phy_m88 series. |
| 2992 | * |
| 2993 | * hw - Struct containing variables accessed by shared code |
| 2994 | *********************************************************************/ |
| 2995 | static int32_t |
| 2996 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
| 2997 | { |
| 2998 | int32_t ret_val; |
| 2999 | uint16_t phy_data; |
| 3000 | |
| 3001 | DEBUGFUNC(); |
| 3002 | |
| 3003 | if (hw->phy_reset_disable) |
| 3004 | return E1000_SUCCESS; |
| 3005 | |
| 3006 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
| 3007 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 3008 | if (ret_val) |
| 3009 | return ret_val; |
| 3010 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3011 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 3012 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3013 | /* Options: |
| 3014 | * MDI/MDI-X = 0 (default) |
| 3015 | * 0 - Auto for all speeds |
| 3016 | * 1 - MDI mode |
| 3017 | * 2 - MDI-X mode |
| 3018 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 3019 | */ |
| 3020 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3021 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3022 | switch (hw->mdix) { |
| 3023 | case 1: |
| 3024 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
| 3025 | break; |
| 3026 | case 2: |
| 3027 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
| 3028 | break; |
| 3029 | case 3: |
| 3030 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
| 3031 | break; |
| 3032 | case 0: |
| 3033 | default: |
| 3034 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
| 3035 | break; |
| 3036 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3037 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3038 | /* Options: |
| 3039 | * disable_polarity_correction = 0 (default) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3040 | * Automatic Correction for Reversed Cable Polarity |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3041 | * 0 - Disabled |
| 3042 | * 1 - Enabled |
| 3043 | */ |
| 3044 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3045 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 3046 | if (ret_val) |
| 3047 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3048 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3049 | if (hw->phy_revision < M88E1011_I_REV_4) { |
| 3050 | /* Force TX_CLK in the Extended PHY Specific Control Register |
| 3051 | * to 25MHz clock. |
| 3052 | */ |
| 3053 | ret_val = e1000_read_phy_reg(hw, |
| 3054 | M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 3055 | if (ret_val) |
| 3056 | return ret_val; |
| 3057 | |
| 3058 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 3059 | |
| 3060 | if ((hw->phy_revision == E1000_REVISION_2) && |
| 3061 | (hw->phy_id == M88E1111_I_PHY_ID)) { |
| 3062 | /* Vidalia Phy, set the downshift counter to 5x */ |
| 3063 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); |
| 3064 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
| 3065 | ret_val = e1000_write_phy_reg(hw, |
| 3066 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 3067 | if (ret_val) |
| 3068 | return ret_val; |
| 3069 | } else { |
| 3070 | /* Configure Master and Slave downshift values */ |
| 3071 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
| 3072 | | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
| 3073 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
| 3074 | | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
| 3075 | ret_val = e1000_write_phy_reg(hw, |
| 3076 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 3077 | if (ret_val) |
| 3078 | return ret_val; |
| 3079 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3080 | } |
| 3081 | |
| 3082 | /* SW Reset the PHY so all changes take effect */ |
| 3083 | ret_val = e1000_phy_reset(hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3084 | if (ret_val) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3085 | DEBUGOUT("Error Resetting the PHY\n"); |
| 3086 | return ret_val; |
| 3087 | } |
| 3088 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3089 | return E1000_SUCCESS; |
| 3090 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3091 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3092 | /******************************************************************** |
| 3093 | * Setup auto-negotiation and flow control advertisements, |
| 3094 | * and then perform auto-negotiation. |
| 3095 | * |
| 3096 | * hw - Struct containing variables accessed by shared code |
| 3097 | *********************************************************************/ |
| 3098 | static int32_t |
| 3099 | e1000_copper_link_autoneg(struct e1000_hw *hw) |
| 3100 | { |
| 3101 | int32_t ret_val; |
| 3102 | uint16_t phy_data; |
| 3103 | |
| 3104 | DEBUGFUNC(); |
| 3105 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3106 | /* Perform some bounds checking on the hw->autoneg_advertised |
| 3107 | * parameter. If this variable is zero, then set it to the default. |
| 3108 | */ |
| 3109 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 3110 | |
| 3111 | /* If autoneg_advertised is zero, we assume it was not defaulted |
| 3112 | * by the calling code so we set to advertise full capability. |
| 3113 | */ |
| 3114 | if (hw->autoneg_advertised == 0) |
| 3115 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 3116 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3117 | /* IFE phy only supports 10/100 */ |
| 3118 | if (hw->phy_type == e1000_phy_ife) |
| 3119 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; |
| 3120 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3121 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
| 3122 | ret_val = e1000_phy_setup_autoneg(hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3123 | if (ret_val) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3124 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
| 3125 | return ret_val; |
| 3126 | } |
| 3127 | DEBUGOUT("Restarting Auto-Neg\n"); |
| 3128 | |
| 3129 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
| 3130 | * the Auto Neg Restart bit in the PHY control register. |
| 3131 | */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3132 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
| 3133 | if (ret_val) |
| 3134 | return ret_val; |
| 3135 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3136 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3137 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
| 3138 | if (ret_val) |
| 3139 | return ret_val; |
| 3140 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3141 | /* Does the user want to wait for Auto-Neg to complete here, or |
| 3142 | * check at a later time (for example, callback routine). |
| 3143 | */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3144 | /* If we do not wait for autonegtation to complete I |
| 3145 | * do not see a valid link status. |
| 3146 | * wait_autoneg_complete = 1 . |
| 3147 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3148 | if (hw->wait_autoneg_complete) { |
| 3149 | ret_val = e1000_wait_autoneg(hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3150 | if (ret_val) { |
| 3151 | DEBUGOUT("Error while waiting for autoneg" |
| 3152 | "to complete\n"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3153 | return ret_val; |
| 3154 | } |
| 3155 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3156 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 3157 | hw->get_link_status = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3158 | |
| 3159 | return E1000_SUCCESS; |
| 3160 | } |
| 3161 | |
| 3162 | /****************************************************************************** |
| 3163 | * Config the MAC and the PHY after link is up. |
| 3164 | * 1) Set up the MAC to the current PHY speed/duplex |
| 3165 | * if we are on 82543. If we |
| 3166 | * are on newer silicon, we only need to configure |
| 3167 | * collision distance in the Transmit Control Register. |
| 3168 | * 2) Set up flow control on the MAC to that established with |
| 3169 | * the link partner. |
| 3170 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
| 3171 | * |
| 3172 | * hw - Struct containing variables accessed by shared code |
| 3173 | ******************************************************************************/ |
| 3174 | static int32_t |
| 3175 | e1000_copper_link_postconfig(struct e1000_hw *hw) |
| 3176 | { |
| 3177 | int32_t ret_val; |
| 3178 | DEBUGFUNC(); |
| 3179 | |
| 3180 | if (hw->mac_type >= e1000_82544) { |
| 3181 | e1000_config_collision_dist(hw); |
| 3182 | } else { |
| 3183 | ret_val = e1000_config_mac_to_phy(hw); |
| 3184 | if (ret_val) { |
| 3185 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
| 3186 | return ret_val; |
| 3187 | } |
| 3188 | } |
| 3189 | ret_val = e1000_config_fc_after_link_up(hw); |
| 3190 | if (ret_val) { |
| 3191 | DEBUGOUT("Error Configuring Flow Control\n"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3192 | return ret_val; |
| 3193 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3194 | return E1000_SUCCESS; |
| 3195 | } |
| 3196 | |
| 3197 | /****************************************************************************** |
| 3198 | * Detects which PHY is present and setup the speed and duplex |
| 3199 | * |
| 3200 | * hw - Struct containing variables accessed by shared code |
| 3201 | ******************************************************************************/ |
| 3202 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 3203 | e1000_setup_copper_link(struct e1000_hw *hw) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3204 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3205 | int32_t ret_val; |
| 3206 | uint16_t i; |
| 3207 | uint16_t phy_data; |
| 3208 | uint16_t reg_data; |
| 3209 | |
| 3210 | DEBUGFUNC(); |
| 3211 | |
| 3212 | switch (hw->mac_type) { |
| 3213 | case e1000_80003es2lan: |
| 3214 | case e1000_ich8lan: |
| 3215 | /* Set the mac to wait the maximum time between each |
| 3216 | * iteration and increase the max iterations when |
| 3217 | * polling the phy; this fixes erroneous timeouts at 10Mbps. */ |
| 3218 | ret_val = e1000_write_kmrn_reg(hw, |
| 3219 | GG82563_REG(0x34, 4), 0xFFFF); |
| 3220 | if (ret_val) |
| 3221 | return ret_val; |
| 3222 | ret_val = e1000_read_kmrn_reg(hw, |
| 3223 | GG82563_REG(0x34, 9), ®_data); |
| 3224 | if (ret_val) |
| 3225 | return ret_val; |
| 3226 | reg_data |= 0x3F; |
| 3227 | ret_val = e1000_write_kmrn_reg(hw, |
| 3228 | GG82563_REG(0x34, 9), reg_data); |
| 3229 | if (ret_val) |
| 3230 | return ret_val; |
| 3231 | default: |
| 3232 | break; |
| 3233 | } |
| 3234 | |
| 3235 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
| 3236 | ret_val = e1000_copper_link_preconfig(hw); |
| 3237 | if (ret_val) |
| 3238 | return ret_val; |
| 3239 | switch (hw->mac_type) { |
| 3240 | case e1000_80003es2lan: |
| 3241 | /* Kumeran registers are written-only */ |
| 3242 | reg_data = |
| 3243 | E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; |
| 3244 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; |
| 3245 | ret_val = e1000_write_kmrn_reg(hw, |
| 3246 | E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); |
| 3247 | if (ret_val) |
| 3248 | return ret_val; |
| 3249 | break; |
| 3250 | default: |
| 3251 | break; |
| 3252 | } |
| 3253 | |
| 3254 | if (hw->phy_type == e1000_phy_igp || |
| 3255 | hw->phy_type == e1000_phy_igp_3 || |
| 3256 | hw->phy_type == e1000_phy_igp_2) { |
| 3257 | ret_val = e1000_copper_link_igp_setup(hw); |
| 3258 | if (ret_val) |
| 3259 | return ret_val; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 3260 | } else if (hw->phy_type == e1000_phy_m88 || |
| 3261 | hw->phy_type == e1000_phy_igb) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3262 | ret_val = e1000_copper_link_mgp_setup(hw); |
| 3263 | if (ret_val) |
| 3264 | return ret_val; |
| 3265 | } else if (hw->phy_type == e1000_phy_gg82563) { |
| 3266 | ret_val = e1000_copper_link_ggp_setup(hw); |
| 3267 | if (ret_val) |
| 3268 | return ret_val; |
| 3269 | } |
| 3270 | |
| 3271 | /* always auto */ |
| 3272 | /* Setup autoneg and flow control advertisement |
| 3273 | * and perform autonegotiation */ |
| 3274 | ret_val = e1000_copper_link_autoneg(hw); |
| 3275 | if (ret_val) |
| 3276 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3277 | |
| 3278 | /* Check link status. Wait up to 100 microseconds for link to become |
| 3279 | * valid. |
| 3280 | */ |
| 3281 | for (i = 0; i < 10; i++) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3282 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 3283 | if (ret_val) |
| 3284 | return ret_val; |
| 3285 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 3286 | if (ret_val) |
| 3287 | return ret_val; |
| 3288 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3289 | if (phy_data & MII_SR_LINK_STATUS) { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3290 | /* Config the MAC and PHY after link is up */ |
| 3291 | ret_val = e1000_copper_link_postconfig(hw); |
| 3292 | if (ret_val) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3293 | return ret_val; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3294 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3295 | DEBUGOUT("Valid link established!!!\n"); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3296 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3297 | } |
| 3298 | udelay(10); |
| 3299 | } |
| 3300 | |
| 3301 | DEBUGOUT("Unable to establish link!!!\n"); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3302 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3303 | } |
| 3304 | |
| 3305 | /****************************************************************************** |
| 3306 | * Configures PHY autoneg and flow control advertisement settings |
| 3307 | * |
| 3308 | * hw - Struct containing variables accessed by shared code |
| 3309 | ******************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3310 | int32_t |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3311 | e1000_phy_setup_autoneg(struct e1000_hw *hw) |
| 3312 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3313 | int32_t ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3314 | uint16_t mii_autoneg_adv_reg; |
| 3315 | uint16_t mii_1000t_ctrl_reg; |
| 3316 | |
| 3317 | DEBUGFUNC(); |
| 3318 | |
| 3319 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3320 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
| 3321 | if (ret_val) |
| 3322 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3323 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3324 | if (hw->phy_type != e1000_phy_ife) { |
| 3325 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
| 3326 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, |
| 3327 | &mii_1000t_ctrl_reg); |
| 3328 | if (ret_val) |
| 3329 | return ret_val; |
| 3330 | } else |
| 3331 | mii_1000t_ctrl_reg = 0; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3332 | |
| 3333 | /* Need to parse both autoneg_advertised and fc and set up |
| 3334 | * the appropriate PHY registers. First we will parse for |
| 3335 | * autoneg_advertised software override. Since we can advertise |
| 3336 | * a plethora of combinations, we need to check each bit |
| 3337 | * individually. |
| 3338 | */ |
| 3339 | |
| 3340 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
| 3341 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3342 | * the 1000Base-T Control Register (Address 9). |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3343 | */ |
| 3344 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
| 3345 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
| 3346 | |
| 3347 | DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); |
| 3348 | |
| 3349 | /* Do we want to advertise 10 Mb Half Duplex? */ |
| 3350 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { |
| 3351 | DEBUGOUT("Advertise 10mb Half duplex\n"); |
| 3352 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
| 3353 | } |
| 3354 | |
| 3355 | /* Do we want to advertise 10 Mb Full Duplex? */ |
| 3356 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
| 3357 | DEBUGOUT("Advertise 10mb Full duplex\n"); |
| 3358 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
| 3359 | } |
| 3360 | |
| 3361 | /* Do we want to advertise 100 Mb Half Duplex? */ |
| 3362 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
| 3363 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
| 3364 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
| 3365 | } |
| 3366 | |
| 3367 | /* Do we want to advertise 100 Mb Full Duplex? */ |
| 3368 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { |
| 3369 | DEBUGOUT("Advertise 100mb Full duplex\n"); |
| 3370 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
| 3371 | } |
| 3372 | |
| 3373 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
| 3374 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
| 3375 | DEBUGOUT |
| 3376 | ("Advertise 1000mb Half duplex requested, request denied!\n"); |
| 3377 | } |
| 3378 | |
| 3379 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
| 3380 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
| 3381 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
| 3382 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
| 3383 | } |
| 3384 | |
| 3385 | /* Check for a software override of the flow control settings, and |
| 3386 | * setup the PHY advertisement registers accordingly. If |
| 3387 | * auto-negotiation is enabled, then software will have to set the |
| 3388 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
| 3389 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. |
| 3390 | * |
| 3391 | * The possible values of the "fc" parameter are: |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3392 | * 0: Flow control is completely disabled |
| 3393 | * 1: Rx flow control is enabled (we can receive pause frames |
| 3394 | * but not send pause frames). |
| 3395 | * 2: Tx flow control is enabled (we can send pause frames |
| 3396 | * but we do not support receiving pause frames). |
| 3397 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3398 | * other: No software override. The flow control configuration |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3399 | * in the EEPROM is used. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3400 | */ |
| 3401 | switch (hw->fc) { |
| 3402 | case e1000_fc_none: /* 0 */ |
| 3403 | /* Flow control (RX & TX) is completely disabled by a |
| 3404 | * software over-ride. |
| 3405 | */ |
| 3406 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 3407 | break; |
| 3408 | case e1000_fc_rx_pause: /* 1 */ |
| 3409 | /* RX Flow control is enabled, and TX Flow control is |
| 3410 | * disabled, by a software over-ride. |
| 3411 | */ |
| 3412 | /* Since there really isn't a way to advertise that we are |
| 3413 | * capable of RX Pause ONLY, we will advertise that we |
| 3414 | * support both symmetric and asymmetric RX PAUSE. Later |
| 3415 | * (in e1000_config_fc_after_link_up) we will disable the |
| 3416 | *hw's ability to send PAUSE frames. |
| 3417 | */ |
| 3418 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 3419 | break; |
| 3420 | case e1000_fc_tx_pause: /* 2 */ |
| 3421 | /* TX Flow control is enabled, and RX Flow control is |
| 3422 | * disabled, by a software over-ride. |
| 3423 | */ |
| 3424 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
| 3425 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
| 3426 | break; |
| 3427 | case e1000_fc_full: /* 3 */ |
| 3428 | /* Flow control (both RX and TX) is enabled by a software |
| 3429 | * over-ride. |
| 3430 | */ |
| 3431 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 3432 | break; |
| 3433 | default: |
| 3434 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 3435 | return -E1000_ERR_CONFIG; |
| 3436 | } |
| 3437 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3438 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
| 3439 | if (ret_val) |
| 3440 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3441 | |
| 3442 | DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
| 3443 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3444 | if (hw->phy_type != e1000_phy_ife) { |
| 3445 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, |
| 3446 | mii_1000t_ctrl_reg); |
| 3447 | if (ret_val) |
| 3448 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3449 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3450 | |
| 3451 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3452 | } |
| 3453 | |
| 3454 | /****************************************************************************** |
| 3455 | * Sets the collision distance in the Transmit Control register |
| 3456 | * |
| 3457 | * hw - Struct containing variables accessed by shared code |
| 3458 | * |
| 3459 | * Link should have been established previously. Reads the speed and duplex |
| 3460 | * information from the Device Status register. |
| 3461 | ******************************************************************************/ |
| 3462 | static void |
| 3463 | e1000_config_collision_dist(struct e1000_hw *hw) |
| 3464 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3465 | uint32_t tctl, coll_dist; |
| 3466 | |
| 3467 | DEBUGFUNC(); |
| 3468 | |
| 3469 | if (hw->mac_type < e1000_82543) |
| 3470 | coll_dist = E1000_COLLISION_DISTANCE_82542; |
| 3471 | else |
| 3472 | coll_dist = E1000_COLLISION_DISTANCE; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3473 | |
| 3474 | tctl = E1000_READ_REG(hw, TCTL); |
| 3475 | |
| 3476 | tctl &= ~E1000_TCTL_COLD; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3477 | tctl |= coll_dist << E1000_COLD_SHIFT; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3478 | |
| 3479 | E1000_WRITE_REG(hw, TCTL, tctl); |
| 3480 | E1000_WRITE_FLUSH(hw); |
| 3481 | } |
| 3482 | |
| 3483 | /****************************************************************************** |
| 3484 | * Sets MAC speed and duplex settings to reflect the those in the PHY |
| 3485 | * |
| 3486 | * hw - Struct containing variables accessed by shared code |
| 3487 | * mii_reg - data to write to the MII control register |
| 3488 | * |
| 3489 | * The contents of the PHY register containing the needed information need to |
| 3490 | * be passed in. |
| 3491 | ******************************************************************************/ |
| 3492 | static int |
| 3493 | e1000_config_mac_to_phy(struct e1000_hw *hw) |
| 3494 | { |
| 3495 | uint32_t ctrl; |
| 3496 | uint16_t phy_data; |
| 3497 | |
| 3498 | DEBUGFUNC(); |
| 3499 | |
| 3500 | /* Read the Device Control Register and set the bits to Force Speed |
| 3501 | * and Duplex. |
| 3502 | */ |
| 3503 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3504 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 3505 | ctrl &= ~(E1000_CTRL_ILOS); |
| 3506 | ctrl |= (E1000_CTRL_SPD_SEL); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3507 | |
| 3508 | /* Set up duplex in the Device Control and Transmit Control |
| 3509 | * registers depending on negotiated values. |
| 3510 | */ |
| 3511 | if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { |
| 3512 | DEBUGOUT("PHY Read Error\n"); |
| 3513 | return -E1000_ERR_PHY; |
| 3514 | } |
| 3515 | if (phy_data & M88E1000_PSSR_DPLX) |
| 3516 | ctrl |= E1000_CTRL_FD; |
| 3517 | else |
| 3518 | ctrl &= ~E1000_CTRL_FD; |
| 3519 | |
| 3520 | e1000_config_collision_dist(hw); |
| 3521 | |
| 3522 | /* Set up speed in the Device Control register depending on |
| 3523 | * negotiated values. |
| 3524 | */ |
| 3525 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
| 3526 | ctrl |= E1000_CTRL_SPD_1000; |
| 3527 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
| 3528 | ctrl |= E1000_CTRL_SPD_100; |
| 3529 | /* Write the configured values back to the Device Control Reg. */ |
| 3530 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3531 | return 0; |
| 3532 | } |
| 3533 | |
| 3534 | /****************************************************************************** |
| 3535 | * Forces the MAC's flow control settings. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 3536 | * |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3537 | * hw - Struct containing variables accessed by shared code |
| 3538 | * |
| 3539 | * Sets the TFCE and RFCE bits in the device control register to reflect |
| 3540 | * the adapter settings. TFCE and RFCE need to be explicitly set by |
| 3541 | * software when a Copper PHY is used because autonegotiation is managed |
| 3542 | * by the PHY rather than the MAC. Software must also configure these |
| 3543 | * bits when link is forced on a fiber connection. |
| 3544 | *****************************************************************************/ |
| 3545 | static int |
| 3546 | e1000_force_mac_fc(struct e1000_hw *hw) |
| 3547 | { |
| 3548 | uint32_t ctrl; |
| 3549 | |
| 3550 | DEBUGFUNC(); |
| 3551 | |
| 3552 | /* Get the current configuration of the Device Control Register */ |
| 3553 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3554 | |
| 3555 | /* Because we didn't get link via the internal auto-negotiation |
| 3556 | * mechanism (we either forced link or we got link via PHY |
| 3557 | * auto-neg), we have to manually enable/disable transmit an |
| 3558 | * receive flow control. |
| 3559 | * |
| 3560 | * The "Case" statement below enables/disable flow control |
| 3561 | * according to the "hw->fc" parameter. |
| 3562 | * |
| 3563 | * The possible values of the "fc" parameter are: |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3564 | * 0: Flow control is completely disabled |
| 3565 | * 1: Rx flow control is enabled (we can receive pause |
| 3566 | * frames but not send pause frames). |
| 3567 | * 2: Tx flow control is enabled (we can send pause frames |
| 3568 | * frames but we do not receive pause frames). |
| 3569 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3570 | * other: No other values should be possible at this point. |
| 3571 | */ |
| 3572 | |
| 3573 | switch (hw->fc) { |
| 3574 | case e1000_fc_none: |
| 3575 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 3576 | break; |
| 3577 | case e1000_fc_rx_pause: |
| 3578 | ctrl &= (~E1000_CTRL_TFCE); |
| 3579 | ctrl |= E1000_CTRL_RFCE; |
| 3580 | break; |
| 3581 | case e1000_fc_tx_pause: |
| 3582 | ctrl &= (~E1000_CTRL_RFCE); |
| 3583 | ctrl |= E1000_CTRL_TFCE; |
| 3584 | break; |
| 3585 | case e1000_fc_full: |
| 3586 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 3587 | break; |
| 3588 | default: |
| 3589 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 3590 | return -E1000_ERR_CONFIG; |
| 3591 | } |
| 3592 | |
| 3593 | /* Disable TX Flow Control for 82542 (rev 2.0) */ |
| 3594 | if (hw->mac_type == e1000_82542_rev2_0) |
| 3595 | ctrl &= (~E1000_CTRL_TFCE); |
| 3596 | |
| 3597 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3598 | return 0; |
| 3599 | } |
| 3600 | |
| 3601 | /****************************************************************************** |
| 3602 | * Configures flow control settings after link is established |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 3603 | * |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3604 | * hw - Struct containing variables accessed by shared code |
| 3605 | * |
| 3606 | * Should be called immediately after a valid link has been established. |
| 3607 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
| 3608 | * and autonegotiation is enabled, the MAC flow control settings will be set |
| 3609 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
| 3610 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. |
| 3611 | *****************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3612 | static int32_t |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3613 | e1000_config_fc_after_link_up(struct e1000_hw *hw) |
| 3614 | { |
| 3615 | int32_t ret_val; |
| 3616 | uint16_t mii_status_reg; |
| 3617 | uint16_t mii_nway_adv_reg; |
| 3618 | uint16_t mii_nway_lp_ability_reg; |
| 3619 | uint16_t speed; |
| 3620 | uint16_t duplex; |
| 3621 | |
| 3622 | DEBUGFUNC(); |
| 3623 | |
| 3624 | /* Check for the case where we have fiber media and auto-neg failed |
| 3625 | * so we had to force link. In this case, we need to force the |
| 3626 | * configuration of the MAC to match the "fc" parameter. |
| 3627 | */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3628 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) |
| 3629 | || ((hw->media_type == e1000_media_type_internal_serdes) |
| 3630 | && (hw->autoneg_failed)) |
| 3631 | || ((hw->media_type == e1000_media_type_copper) |
| 3632 | && (!hw->autoneg))) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3633 | ret_val = e1000_force_mac_fc(hw); |
| 3634 | if (ret_val < 0) { |
| 3635 | DEBUGOUT("Error forcing flow control settings\n"); |
| 3636 | return ret_val; |
| 3637 | } |
| 3638 | } |
| 3639 | |
| 3640 | /* Check for the case where we have copper media and auto-neg is |
| 3641 | * enabled. In this case, we need to check and see if Auto-Neg |
| 3642 | * has completed, and if so, how the PHY and link partner has |
| 3643 | * flow control configured. |
| 3644 | */ |
| 3645 | if (hw->media_type == e1000_media_type_copper) { |
| 3646 | /* Read the MII Status Register and check to see if AutoNeg |
| 3647 | * has completed. We read this twice because this reg has |
| 3648 | * some "sticky" (latched) bits. |
| 3649 | */ |
| 3650 | if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { |
Minghuan Lian | 674bcd5 | 2015-03-19 09:43:51 -0700 | [diff] [blame] | 3651 | DEBUGOUT("PHY Read Error\n"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3652 | return -E1000_ERR_PHY; |
| 3653 | } |
| 3654 | if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { |
Minghuan Lian | 674bcd5 | 2015-03-19 09:43:51 -0700 | [diff] [blame] | 3655 | DEBUGOUT("PHY Read Error\n"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3656 | return -E1000_ERR_PHY; |
| 3657 | } |
| 3658 | |
| 3659 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
| 3660 | /* The AutoNeg process has completed, so we now need to |
| 3661 | * read both the Auto Negotiation Advertisement Register |
| 3662 | * (Address 4) and the Auto_Negotiation Base Page Ability |
| 3663 | * Register (Address 5) to determine how flow control was |
| 3664 | * negotiated. |
| 3665 | */ |
| 3666 | if (e1000_read_phy_reg |
| 3667 | (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { |
| 3668 | DEBUGOUT("PHY Read Error\n"); |
| 3669 | return -E1000_ERR_PHY; |
| 3670 | } |
| 3671 | if (e1000_read_phy_reg |
| 3672 | (hw, PHY_LP_ABILITY, |
| 3673 | &mii_nway_lp_ability_reg) < 0) { |
| 3674 | DEBUGOUT("PHY Read Error\n"); |
| 3675 | return -E1000_ERR_PHY; |
| 3676 | } |
| 3677 | |
| 3678 | /* Two bits in the Auto Negotiation Advertisement Register |
| 3679 | * (Address 4) and two bits in the Auto Negotiation Base |
| 3680 | * Page Ability Register (Address 5) determine flow control |
| 3681 | * for both the PHY and the link partner. The following |
| 3682 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 3683 | * 1999, describes these PAUSE resolution bits and how flow |
| 3684 | * control is determined based upon these settings. |
| 3685 | * NOTE: DC = Don't Care |
| 3686 | * |
| 3687 | * LOCAL DEVICE | LINK PARTNER |
| 3688 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 3689 | *-------|---------|-------|---------|-------------------- |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3690 | * 0 | 0 | DC | DC | e1000_fc_none |
| 3691 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 3692 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 3693 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 3694 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 3695 | * 1 | DC | 1 | DC | e1000_fc_full |
| 3696 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 3697 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3698 | * |
| 3699 | */ |
| 3700 | /* Are both PAUSE bits set to 1? If so, this implies |
| 3701 | * Symmetric Flow Control is enabled at both ends. The |
| 3702 | * ASM_DIR bits are irrelevant per the spec. |
| 3703 | * |
| 3704 | * For Symmetric Flow Control: |
| 3705 | * |
| 3706 | * LOCAL DEVICE | LINK PARTNER |
| 3707 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 3708 | *-------|---------|-------|---------|-------------------- |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3709 | * 1 | DC | 1 | DC | e1000_fc_full |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3710 | * |
| 3711 | */ |
| 3712 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 3713 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
| 3714 | /* Now we need to check if the user selected RX ONLY |
| 3715 | * of pause frames. In this case, we had to advertise |
| 3716 | * FULL flow control because we could not advertise RX |
| 3717 | * ONLY. Hence, we must now check to see if we need to |
| 3718 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 3719 | */ |
| 3720 | if (hw->original_fc == e1000_fc_full) { |
| 3721 | hw->fc = e1000_fc_full; |
| 3722 | DEBUGOUT("Flow Control = FULL.\r\n"); |
| 3723 | } else { |
| 3724 | hw->fc = e1000_fc_rx_pause; |
| 3725 | DEBUGOUT |
| 3726 | ("Flow Control = RX PAUSE frames only.\r\n"); |
| 3727 | } |
| 3728 | } |
| 3729 | /* For receiving PAUSE frames ONLY. |
| 3730 | * |
| 3731 | * LOCAL DEVICE | LINK PARTNER |
| 3732 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 3733 | *-------|---------|-------|---------|-------------------- |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3734 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3735 | * |
| 3736 | */ |
| 3737 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 3738 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 3739 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 3740 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
| 3741 | { |
| 3742 | hw->fc = e1000_fc_tx_pause; |
| 3743 | DEBUGOUT |
| 3744 | ("Flow Control = TX PAUSE frames only.\r\n"); |
| 3745 | } |
| 3746 | /* For transmitting PAUSE frames ONLY. |
| 3747 | * |
| 3748 | * LOCAL DEVICE | LINK PARTNER |
| 3749 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 3750 | *-------|---------|-------|---------|-------------------- |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3751 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3752 | * |
| 3753 | */ |
| 3754 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 3755 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 3756 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 3757 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
| 3758 | { |
| 3759 | hw->fc = e1000_fc_rx_pause; |
| 3760 | DEBUGOUT |
| 3761 | ("Flow Control = RX PAUSE frames only.\r\n"); |
| 3762 | } |
| 3763 | /* Per the IEEE spec, at this point flow control should be |
| 3764 | * disabled. However, we want to consider that we could |
| 3765 | * be connected to a legacy switch that doesn't advertise |
| 3766 | * desired flow control, but can be forced on the link |
| 3767 | * partner. So if we advertised no flow control, that is |
| 3768 | * what we will resolve to. If we advertised some kind of |
| 3769 | * receive capability (Rx Pause Only or Full Flow Control) |
| 3770 | * and the link partner advertised none, we will configure |
| 3771 | * ourselves to enable Rx Flow Control only. We can do |
| 3772 | * this safely for two reasons: If the link partner really |
| 3773 | * didn't want flow control enabled, and we enable Rx, no |
| 3774 | * harm done since we won't be receiving any PAUSE frames |
| 3775 | * anyway. If the intent on the link partner was to have |
| 3776 | * flow control enabled, then by us enabling RX only, we |
| 3777 | * can at least receive pause frames and process them. |
| 3778 | * This is a good idea because in most cases, since we are |
| 3779 | * predominantly a server NIC, more times than not we will |
| 3780 | * be asked to delay transmission of packets than asking |
| 3781 | * our link partner to pause transmission of frames. |
| 3782 | */ |
| 3783 | else if (hw->original_fc == e1000_fc_none || |
| 3784 | hw->original_fc == e1000_fc_tx_pause) { |
| 3785 | hw->fc = e1000_fc_none; |
| 3786 | DEBUGOUT("Flow Control = NONE.\r\n"); |
| 3787 | } else { |
| 3788 | hw->fc = e1000_fc_rx_pause; |
| 3789 | DEBUGOUT |
| 3790 | ("Flow Control = RX PAUSE frames only.\r\n"); |
| 3791 | } |
| 3792 | |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3793 | /* Now we need to do one last check... If we auto- |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3794 | * negotiated to HALF DUPLEX, flow control should not be |
| 3795 | * enabled per IEEE 802.3 spec. |
| 3796 | */ |
| 3797 | e1000_get_speed_and_duplex(hw, &speed, &duplex); |
| 3798 | |
| 3799 | if (duplex == HALF_DUPLEX) |
| 3800 | hw->fc = e1000_fc_none; |
| 3801 | |
| 3802 | /* Now we call a subroutine to actually force the MAC |
| 3803 | * controller to use the correct flow control settings. |
| 3804 | */ |
| 3805 | ret_val = e1000_force_mac_fc(hw); |
| 3806 | if (ret_val < 0) { |
| 3807 | DEBUGOUT |
| 3808 | ("Error forcing flow control settings\n"); |
| 3809 | return ret_val; |
| 3810 | } |
| 3811 | } else { |
| 3812 | DEBUGOUT |
| 3813 | ("Copper PHY and Auto Neg has not completed.\r\n"); |
| 3814 | } |
| 3815 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 3816 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3817 | } |
| 3818 | |
| 3819 | /****************************************************************************** |
| 3820 | * Checks to see if the link status of the hardware has changed. |
| 3821 | * |
| 3822 | * hw - Struct containing variables accessed by shared code |
| 3823 | * |
| 3824 | * Called by any function that needs to check the link status of the adapter. |
| 3825 | *****************************************************************************/ |
| 3826 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 3827 | e1000_check_for_link(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3828 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3829 | uint32_t rxcw; |
| 3830 | uint32_t ctrl; |
| 3831 | uint32_t status; |
| 3832 | uint32_t rctl; |
| 3833 | uint32_t signal; |
| 3834 | int32_t ret_val; |
| 3835 | uint16_t phy_data; |
| 3836 | uint16_t lp_capability; |
| 3837 | |
| 3838 | DEBUGFUNC(); |
| 3839 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 3840 | /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be |
| 3841 | * set when the optics detect a signal. On older adapters, it will be |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3842 | * cleared when there is a signal |
| 3843 | */ |
| 3844 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3845 | if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) |
| 3846 | signal = E1000_CTRL_SWDPIN1; |
| 3847 | else |
| 3848 | signal = 0; |
| 3849 | |
| 3850 | status = E1000_READ_REG(hw, STATUS); |
| 3851 | rxcw = E1000_READ_REG(hw, RXCW); |
| 3852 | DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); |
| 3853 | |
| 3854 | /* If we have a copper PHY then we only want to go out to the PHY |
| 3855 | * registers to see if Auto-Neg has completed and/or if our link |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3856 | * status has changed. The get_link_status flag will be set if we |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3857 | * receive a Link Status Change interrupt or we have Rx Sequence |
| 3858 | * Errors. |
| 3859 | */ |
| 3860 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
| 3861 | /* First we want to see if the MII Status Register reports |
| 3862 | * link. If so, then we want to get the current speed/duplex |
| 3863 | * of the PHY. |
| 3864 | * Read the register twice since the link bit is sticky. |
| 3865 | */ |
| 3866 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { |
| 3867 | DEBUGOUT("PHY Read Error\n"); |
| 3868 | return -E1000_ERR_PHY; |
| 3869 | } |
| 3870 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { |
| 3871 | DEBUGOUT("PHY Read Error\n"); |
| 3872 | return -E1000_ERR_PHY; |
| 3873 | } |
| 3874 | |
| 3875 | if (phy_data & MII_SR_LINK_STATUS) { |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 3876 | hw->get_link_status = false; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3877 | } else { |
| 3878 | /* No link detected */ |
| 3879 | return -E1000_ERR_NOLINK; |
| 3880 | } |
| 3881 | |
| 3882 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
| 3883 | * have Si on board that is 82544 or newer, Auto |
| 3884 | * Speed Detection takes care of MAC speed/duplex |
| 3885 | * configuration. So we only need to configure Collision |
| 3886 | * Distance in the MAC. Otherwise, we need to force |
| 3887 | * speed/duplex on the MAC to the current PHY speed/duplex |
| 3888 | * settings. |
| 3889 | */ |
| 3890 | if (hw->mac_type >= e1000_82544) |
| 3891 | e1000_config_collision_dist(hw); |
| 3892 | else { |
| 3893 | ret_val = e1000_config_mac_to_phy(hw); |
| 3894 | if (ret_val < 0) { |
| 3895 | DEBUGOUT |
| 3896 | ("Error configuring MAC to PHY settings\n"); |
| 3897 | return ret_val; |
| 3898 | } |
| 3899 | } |
| 3900 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 3901 | /* Configure Flow Control now that Auto-Neg has completed. First, we |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3902 | * need to restore the desired flow control settings because we may |
| 3903 | * have had to re-autoneg with a different link partner. |
| 3904 | */ |
| 3905 | ret_val = e1000_config_fc_after_link_up(hw); |
| 3906 | if (ret_val < 0) { |
| 3907 | DEBUGOUT("Error configuring flow control\n"); |
| 3908 | return ret_val; |
| 3909 | } |
| 3910 | |
| 3911 | /* At this point we know that we are on copper and we have |
| 3912 | * auto-negotiated link. These are conditions for checking the link |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 3913 | * parter capability register. We use the link partner capability to |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3914 | * determine if TBI Compatibility needs to be turned on or off. If |
| 3915 | * the link partner advertises any speed in addition to Gigabit, then |
| 3916 | * we assume that they are GMII-based, and TBI compatibility is not |
| 3917 | * needed. If no other speeds are advertised, we assume the link |
| 3918 | * partner is TBI-based, and we turn on TBI Compatibility. |
| 3919 | */ |
| 3920 | if (hw->tbi_compatibility_en) { |
| 3921 | if (e1000_read_phy_reg |
| 3922 | (hw, PHY_LP_ABILITY, &lp_capability) < 0) { |
| 3923 | DEBUGOUT("PHY Read Error\n"); |
| 3924 | return -E1000_ERR_PHY; |
| 3925 | } |
| 3926 | if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | |
| 3927 | NWAY_LPAR_10T_FD_CAPS | |
| 3928 | NWAY_LPAR_100TX_HD_CAPS | |
| 3929 | NWAY_LPAR_100TX_FD_CAPS | |
| 3930 | NWAY_LPAR_100T4_CAPS)) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 3931 | /* If our link partner advertises anything in addition to |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3932 | * gigabit, we do not need to enable TBI compatibility. |
| 3933 | */ |
| 3934 | if (hw->tbi_compatibility_on) { |
| 3935 | /* If we previously were in the mode, turn it off. */ |
| 3936 | rctl = E1000_READ_REG(hw, RCTL); |
| 3937 | rctl &= ~E1000_RCTL_SBP; |
| 3938 | E1000_WRITE_REG(hw, RCTL, rctl); |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 3939 | hw->tbi_compatibility_on = false; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3940 | } |
| 3941 | } else { |
| 3942 | /* If TBI compatibility is was previously off, turn it on. For |
| 3943 | * compatibility with a TBI link partner, we will store bad |
| 3944 | * packets. Some frames have an additional byte on the end and |
| 3945 | * will look like CRC errors to to the hardware. |
| 3946 | */ |
| 3947 | if (!hw->tbi_compatibility_on) { |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 3948 | hw->tbi_compatibility_on = true; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 3949 | rctl = E1000_READ_REG(hw, RCTL); |
| 3950 | rctl |= E1000_RCTL_SBP; |
| 3951 | E1000_WRITE_REG(hw, RCTL, rctl); |
| 3952 | } |
| 3953 | } |
| 3954 | } |
| 3955 | } |
| 3956 | /* If we don't have link (auto-negotiation failed or link partner cannot |
| 3957 | * auto-negotiate), the cable is plugged in (we have signal), and our |
| 3958 | * link partner is not trying to auto-negotiate with us (we are receiving |
| 3959 | * idles or data), we need to force link up. We also need to give |
| 3960 | * auto-negotiation time to complete, in case the cable was just plugged |
| 3961 | * in. The autoneg_failed flag does this. |
| 3962 | */ |
| 3963 | else if ((hw->media_type == e1000_media_type_fiber) && |
| 3964 | (!(status & E1000_STATUS_LU)) && |
| 3965 | ((ctrl & E1000_CTRL_SWDPIN1) == signal) && |
| 3966 | (!(rxcw & E1000_RXCW_C))) { |
| 3967 | if (hw->autoneg_failed == 0) { |
| 3968 | hw->autoneg_failed = 1; |
| 3969 | return 0; |
| 3970 | } |
| 3971 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); |
| 3972 | |
| 3973 | /* Disable auto-negotiation in the TXCW register */ |
| 3974 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
| 3975 | |
| 3976 | /* Force link-up and also force full-duplex. */ |
| 3977 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3978 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
| 3979 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3980 | |
| 3981 | /* Configure Flow Control after forcing link up. */ |
| 3982 | ret_val = e1000_config_fc_after_link_up(hw); |
| 3983 | if (ret_val < 0) { |
| 3984 | DEBUGOUT("Error configuring flow control\n"); |
| 3985 | return ret_val; |
| 3986 | } |
| 3987 | } |
| 3988 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable |
| 3989 | * auto-negotiation in the TXCW register and disable forced link in the |
| 3990 | * Device Control register in an attempt to auto-negotiate with our link |
| 3991 | * partner. |
| 3992 | */ |
| 3993 | else if ((hw->media_type == e1000_media_type_fiber) && |
| 3994 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
| 3995 | DEBUGOUT |
| 3996 | ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); |
| 3997 | E1000_WRITE_REG(hw, TXCW, hw->txcw); |
| 3998 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); |
| 3999 | } |
| 4000 | return 0; |
| 4001 | } |
| 4002 | |
| 4003 | /****************************************************************************** |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4004 | * Configure the MAC-to-PHY interface for 10/100Mbps |
| 4005 | * |
| 4006 | * hw - Struct containing variables accessed by shared code |
| 4007 | ******************************************************************************/ |
| 4008 | static int32_t |
| 4009 | e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) |
| 4010 | { |
| 4011 | int32_t ret_val = E1000_SUCCESS; |
| 4012 | uint32_t tipg; |
| 4013 | uint16_t reg_data; |
| 4014 | |
| 4015 | DEBUGFUNC(); |
| 4016 | |
| 4017 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; |
| 4018 | ret_val = e1000_write_kmrn_reg(hw, |
| 4019 | E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); |
| 4020 | if (ret_val) |
| 4021 | return ret_val; |
| 4022 | |
| 4023 | /* Configure Transmit Inter-Packet Gap */ |
| 4024 | tipg = E1000_READ_REG(hw, TIPG); |
| 4025 | tipg &= ~E1000_TIPG_IPGT_MASK; |
| 4026 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; |
| 4027 | E1000_WRITE_REG(hw, TIPG, tipg); |
| 4028 | |
| 4029 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
| 4030 | |
| 4031 | if (ret_val) |
| 4032 | return ret_val; |
| 4033 | |
| 4034 | if (duplex == HALF_DUPLEX) |
| 4035 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; |
| 4036 | else |
| 4037 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
| 4038 | |
| 4039 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
| 4040 | |
| 4041 | return ret_val; |
| 4042 | } |
| 4043 | |
| 4044 | static int32_t |
| 4045 | e1000_configure_kmrn_for_1000(struct e1000_hw *hw) |
| 4046 | { |
| 4047 | int32_t ret_val = E1000_SUCCESS; |
| 4048 | uint16_t reg_data; |
| 4049 | uint32_t tipg; |
| 4050 | |
| 4051 | DEBUGFUNC(); |
| 4052 | |
| 4053 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; |
| 4054 | ret_val = e1000_write_kmrn_reg(hw, |
| 4055 | E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); |
| 4056 | if (ret_val) |
| 4057 | return ret_val; |
| 4058 | |
| 4059 | /* Configure Transmit Inter-Packet Gap */ |
| 4060 | tipg = E1000_READ_REG(hw, TIPG); |
| 4061 | tipg &= ~E1000_TIPG_IPGT_MASK; |
| 4062 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
| 4063 | E1000_WRITE_REG(hw, TIPG, tipg); |
| 4064 | |
| 4065 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
| 4066 | |
| 4067 | if (ret_val) |
| 4068 | return ret_val; |
| 4069 | |
| 4070 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
| 4071 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
| 4072 | |
| 4073 | return ret_val; |
| 4074 | } |
| 4075 | |
| 4076 | /****************************************************************************** |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4077 | * Detects the current speed and duplex settings of the hardware. |
| 4078 | * |
| 4079 | * hw - Struct containing variables accessed by shared code |
| 4080 | * speed - Speed of the connection |
| 4081 | * duplex - Duplex setting of the connection |
| 4082 | *****************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4083 | static int |
| 4084 | e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, |
| 4085 | uint16_t *duplex) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4086 | { |
| 4087 | uint32_t status; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4088 | int32_t ret_val; |
| 4089 | uint16_t phy_data; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4090 | |
| 4091 | DEBUGFUNC(); |
| 4092 | |
| 4093 | if (hw->mac_type >= e1000_82543) { |
| 4094 | status = E1000_READ_REG(hw, STATUS); |
| 4095 | if (status & E1000_STATUS_SPEED_1000) { |
| 4096 | *speed = SPEED_1000; |
| 4097 | DEBUGOUT("1000 Mbs, "); |
| 4098 | } else if (status & E1000_STATUS_SPEED_100) { |
| 4099 | *speed = SPEED_100; |
| 4100 | DEBUGOUT("100 Mbs, "); |
| 4101 | } else { |
| 4102 | *speed = SPEED_10; |
| 4103 | DEBUGOUT("10 Mbs, "); |
| 4104 | } |
| 4105 | |
| 4106 | if (status & E1000_STATUS_FD) { |
| 4107 | *duplex = FULL_DUPLEX; |
| 4108 | DEBUGOUT("Full Duplex\r\n"); |
| 4109 | } else { |
| 4110 | *duplex = HALF_DUPLEX; |
| 4111 | DEBUGOUT(" Half Duplex\r\n"); |
| 4112 | } |
| 4113 | } else { |
| 4114 | DEBUGOUT("1000 Mbs, Full Duplex\r\n"); |
| 4115 | *speed = SPEED_1000; |
| 4116 | *duplex = FULL_DUPLEX; |
| 4117 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4118 | |
| 4119 | /* IGP01 PHY may advertise full duplex operation after speed downgrade |
| 4120 | * even if it is operating at half duplex. Here we set the duplex |
| 4121 | * settings to match the duplex in the link partner's capabilities. |
| 4122 | */ |
| 4123 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
| 4124 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
| 4125 | if (ret_val) |
| 4126 | return ret_val; |
| 4127 | |
| 4128 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
| 4129 | *duplex = HALF_DUPLEX; |
| 4130 | else { |
| 4131 | ret_val = e1000_read_phy_reg(hw, |
| 4132 | PHY_LP_ABILITY, &phy_data); |
| 4133 | if (ret_val) |
| 4134 | return ret_val; |
| 4135 | if ((*speed == SPEED_100 && |
| 4136 | !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) |
| 4137 | || (*speed == SPEED_10 |
| 4138 | && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
| 4139 | *duplex = HALF_DUPLEX; |
| 4140 | } |
| 4141 | } |
| 4142 | |
| 4143 | if ((hw->mac_type == e1000_80003es2lan) && |
| 4144 | (hw->media_type == e1000_media_type_copper)) { |
| 4145 | if (*speed == SPEED_1000) |
| 4146 | ret_val = e1000_configure_kmrn_for_1000(hw); |
| 4147 | else |
| 4148 | ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); |
| 4149 | if (ret_val) |
| 4150 | return ret_val; |
| 4151 | } |
| 4152 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4153 | } |
| 4154 | |
| 4155 | /****************************************************************************** |
| 4156 | * Blocks until autoneg completes or times out (~4.5 seconds) |
| 4157 | * |
| 4158 | * hw - Struct containing variables accessed by shared code |
| 4159 | ******************************************************************************/ |
| 4160 | static int |
| 4161 | e1000_wait_autoneg(struct e1000_hw *hw) |
| 4162 | { |
| 4163 | uint16_t i; |
| 4164 | uint16_t phy_data; |
| 4165 | |
| 4166 | DEBUGFUNC(); |
| 4167 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
| 4168 | |
Stefan Roese | 497c731 | 2015-08-11 17:12:44 +0200 | [diff] [blame] | 4169 | /* We will wait for autoneg to complete or timeout to expire. */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4170 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
| 4171 | /* Read the MII Status Register and wait for Auto-Neg |
| 4172 | * Complete bit to be set. |
| 4173 | */ |
| 4174 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { |
| 4175 | DEBUGOUT("PHY Read Error\n"); |
| 4176 | return -E1000_ERR_PHY; |
| 4177 | } |
| 4178 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { |
| 4179 | DEBUGOUT("PHY Read Error\n"); |
| 4180 | return -E1000_ERR_PHY; |
| 4181 | } |
| 4182 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
| 4183 | DEBUGOUT("Auto-Neg complete.\n"); |
| 4184 | return 0; |
| 4185 | } |
| 4186 | mdelay(100); |
| 4187 | } |
| 4188 | DEBUGOUT("Auto-Neg timedout.\n"); |
| 4189 | return -E1000_ERR_TIMEOUT; |
| 4190 | } |
| 4191 | |
| 4192 | /****************************************************************************** |
| 4193 | * Raises the Management Data Clock |
| 4194 | * |
| 4195 | * hw - Struct containing variables accessed by shared code |
| 4196 | * ctrl - Device control register's current value |
| 4197 | ******************************************************************************/ |
| 4198 | static void |
| 4199 | e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) |
| 4200 | { |
| 4201 | /* Raise the clock input to the Management Data Clock (by setting the MDC |
| 4202 | * bit), and then delay 2 microseconds. |
| 4203 | */ |
| 4204 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); |
| 4205 | E1000_WRITE_FLUSH(hw); |
| 4206 | udelay(2); |
| 4207 | } |
| 4208 | |
| 4209 | /****************************************************************************** |
| 4210 | * Lowers the Management Data Clock |
| 4211 | * |
| 4212 | * hw - Struct containing variables accessed by shared code |
| 4213 | * ctrl - Device control register's current value |
| 4214 | ******************************************************************************/ |
| 4215 | static void |
| 4216 | e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) |
| 4217 | { |
| 4218 | /* Lower the clock input to the Management Data Clock (by clearing the MDC |
| 4219 | * bit), and then delay 2 microseconds. |
| 4220 | */ |
| 4221 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
| 4222 | E1000_WRITE_FLUSH(hw); |
| 4223 | udelay(2); |
| 4224 | } |
| 4225 | |
| 4226 | /****************************************************************************** |
| 4227 | * Shifts data bits out to the PHY |
| 4228 | * |
| 4229 | * hw - Struct containing variables accessed by shared code |
| 4230 | * data - Data to send out to the PHY |
| 4231 | * count - Number of bits to shift out |
| 4232 | * |
| 4233 | * Bits are shifted out in MSB to LSB order. |
| 4234 | ******************************************************************************/ |
| 4235 | static void |
| 4236 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) |
| 4237 | { |
| 4238 | uint32_t ctrl; |
| 4239 | uint32_t mask; |
| 4240 | |
| 4241 | /* We need to shift "count" number of bits out to the PHY. So, the value |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 4242 | * in the "data" parameter will be shifted out to the PHY one bit at a |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4243 | * time. In order to do this, "data" must be broken down into bits. |
| 4244 | */ |
| 4245 | mask = 0x01; |
| 4246 | mask <<= (count - 1); |
| 4247 | |
| 4248 | ctrl = E1000_READ_REG(hw, CTRL); |
| 4249 | |
| 4250 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
| 4251 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
| 4252 | |
| 4253 | while (mask) { |
| 4254 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
| 4255 | * then raising and lowering the Management Data Clock. A "0" is |
| 4256 | * shifted out to the PHY by setting the MDIO bit to "0" and then |
| 4257 | * raising and lowering the clock. |
| 4258 | */ |
| 4259 | if (data & mask) |
| 4260 | ctrl |= E1000_CTRL_MDIO; |
| 4261 | else |
| 4262 | ctrl &= ~E1000_CTRL_MDIO; |
| 4263 | |
| 4264 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 4265 | E1000_WRITE_FLUSH(hw); |
| 4266 | |
| 4267 | udelay(2); |
| 4268 | |
| 4269 | e1000_raise_mdi_clk(hw, &ctrl); |
| 4270 | e1000_lower_mdi_clk(hw, &ctrl); |
| 4271 | |
| 4272 | mask = mask >> 1; |
| 4273 | } |
| 4274 | } |
| 4275 | |
| 4276 | /****************************************************************************** |
| 4277 | * Shifts data bits in from the PHY |
| 4278 | * |
| 4279 | * hw - Struct containing variables accessed by shared code |
| 4280 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 4281 | * Bits are shifted in in MSB to LSB order. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4282 | ******************************************************************************/ |
| 4283 | static uint16_t |
| 4284 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
| 4285 | { |
| 4286 | uint32_t ctrl; |
| 4287 | uint16_t data = 0; |
| 4288 | uint8_t i; |
| 4289 | |
| 4290 | /* In order to read a register from the PHY, we need to shift in a total |
| 4291 | * of 18 bits from the PHY. The first two bit (turnaround) times are used |
| 4292 | * to avoid contention on the MDIO pin when a read operation is performed. |
| 4293 | * These two bits are ignored by us and thrown away. Bits are "shifted in" |
| 4294 | * by raising the input to the Management Data Clock (setting the MDC bit), |
| 4295 | * and then reading the value of the MDIO bit. |
| 4296 | */ |
| 4297 | ctrl = E1000_READ_REG(hw, CTRL); |
| 4298 | |
| 4299 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
| 4300 | ctrl &= ~E1000_CTRL_MDIO_DIR; |
| 4301 | ctrl &= ~E1000_CTRL_MDIO; |
| 4302 | |
| 4303 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 4304 | E1000_WRITE_FLUSH(hw); |
| 4305 | |
| 4306 | /* Raise and Lower the clock before reading in the data. This accounts for |
| 4307 | * the turnaround bits. The first clock occurred when we clocked out the |
| 4308 | * last bit of the Register Address. |
| 4309 | */ |
| 4310 | e1000_raise_mdi_clk(hw, &ctrl); |
| 4311 | e1000_lower_mdi_clk(hw, &ctrl); |
| 4312 | |
| 4313 | for (data = 0, i = 0; i < 16; i++) { |
| 4314 | data = data << 1; |
| 4315 | e1000_raise_mdi_clk(hw, &ctrl); |
| 4316 | ctrl = E1000_READ_REG(hw, CTRL); |
| 4317 | /* Check to see if we shifted in a "1". */ |
| 4318 | if (ctrl & E1000_CTRL_MDIO) |
| 4319 | data |= 1; |
| 4320 | e1000_lower_mdi_clk(hw, &ctrl); |
| 4321 | } |
| 4322 | |
| 4323 | e1000_raise_mdi_clk(hw, &ctrl); |
| 4324 | e1000_lower_mdi_clk(hw, &ctrl); |
| 4325 | |
| 4326 | return data; |
| 4327 | } |
| 4328 | |
| 4329 | /***************************************************************************** |
| 4330 | * Reads the value from a PHY register |
| 4331 | * |
| 4332 | * hw - Struct containing variables accessed by shared code |
| 4333 | * reg_addr - address of the PHY register to read |
| 4334 | ******************************************************************************/ |
| 4335 | static int |
| 4336 | e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) |
| 4337 | { |
| 4338 | uint32_t i; |
| 4339 | uint32_t mdic = 0; |
| 4340 | const uint32_t phy_addr = 1; |
| 4341 | |
| 4342 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
| 4343 | DEBUGOUT("PHY Address %d is out of range\n", reg_addr); |
| 4344 | return -E1000_ERR_PARAM; |
| 4345 | } |
| 4346 | |
| 4347 | if (hw->mac_type > e1000_82543) { |
| 4348 | /* Set up Op-code, Phy Address, and register address in the MDI |
| 4349 | * Control register. The MAC will take care of interfacing with the |
| 4350 | * PHY to retrieve the desired data. |
| 4351 | */ |
| 4352 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
| 4353 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
| 4354 | (E1000_MDIC_OP_READ)); |
| 4355 | |
| 4356 | E1000_WRITE_REG(hw, MDIC, mdic); |
| 4357 | |
| 4358 | /* Poll the ready bit to see if the MDI read completed */ |
| 4359 | for (i = 0; i < 64; i++) { |
| 4360 | udelay(10); |
| 4361 | mdic = E1000_READ_REG(hw, MDIC); |
| 4362 | if (mdic & E1000_MDIC_READY) |
| 4363 | break; |
| 4364 | } |
| 4365 | if (!(mdic & E1000_MDIC_READY)) { |
| 4366 | DEBUGOUT("MDI Read did not complete\n"); |
| 4367 | return -E1000_ERR_PHY; |
| 4368 | } |
| 4369 | if (mdic & E1000_MDIC_ERROR) { |
| 4370 | DEBUGOUT("MDI Error\n"); |
| 4371 | return -E1000_ERR_PHY; |
| 4372 | } |
| 4373 | *phy_data = (uint16_t) mdic; |
| 4374 | } else { |
| 4375 | /* We must first send a preamble through the MDIO pin to signal the |
| 4376 | * beginning of an MII instruction. This is done by sending 32 |
| 4377 | * consecutive "1" bits. |
| 4378 | */ |
| 4379 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
| 4380 | |
| 4381 | /* Now combine the next few fields that are required for a read |
| 4382 | * operation. We use this method instead of calling the |
| 4383 | * e1000_shift_out_mdi_bits routine five different times. The format of |
| 4384 | * a MII read instruction consists of a shift out of 14 bits and is |
| 4385 | * defined as follows: |
| 4386 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
| 4387 | * followed by a shift in of 18 bits. This first two bits shifted in |
| 4388 | * are TurnAround bits used to avoid contention on the MDIO pin when a |
| 4389 | * READ operation is performed. These two bits are thrown away |
| 4390 | * followed by a shift in of 16 bits which contains the desired data. |
| 4391 | */ |
| 4392 | mdic = ((reg_addr) | (phy_addr << 5) | |
| 4393 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
| 4394 | |
| 4395 | e1000_shift_out_mdi_bits(hw, mdic, 14); |
| 4396 | |
| 4397 | /* Now that we've shifted out the read command to the MII, we need to |
| 4398 | * "shift in" the 16-bit value (18 total bits) of the requested PHY |
| 4399 | * register address. |
| 4400 | */ |
| 4401 | *phy_data = e1000_shift_in_mdi_bits(hw); |
| 4402 | } |
| 4403 | return 0; |
| 4404 | } |
| 4405 | |
| 4406 | /****************************************************************************** |
| 4407 | * Writes a value to a PHY register |
| 4408 | * |
| 4409 | * hw - Struct containing variables accessed by shared code |
| 4410 | * reg_addr - address of the PHY register to write |
| 4411 | * data - data to write to the PHY |
| 4412 | ******************************************************************************/ |
| 4413 | static int |
| 4414 | e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) |
| 4415 | { |
| 4416 | uint32_t i; |
| 4417 | uint32_t mdic = 0; |
| 4418 | const uint32_t phy_addr = 1; |
| 4419 | |
| 4420 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
| 4421 | DEBUGOUT("PHY Address %d is out of range\n", reg_addr); |
| 4422 | return -E1000_ERR_PARAM; |
| 4423 | } |
| 4424 | |
| 4425 | if (hw->mac_type > e1000_82543) { |
| 4426 | /* Set up Op-code, Phy Address, register address, and data intended |
| 4427 | * for the PHY register in the MDI Control register. The MAC will take |
| 4428 | * care of interfacing with the PHY to send the desired data. |
| 4429 | */ |
| 4430 | mdic = (((uint32_t) phy_data) | |
| 4431 | (reg_addr << E1000_MDIC_REG_SHIFT) | |
| 4432 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
| 4433 | (E1000_MDIC_OP_WRITE)); |
| 4434 | |
| 4435 | E1000_WRITE_REG(hw, MDIC, mdic); |
| 4436 | |
| 4437 | /* Poll the ready bit to see if the MDI read completed */ |
| 4438 | for (i = 0; i < 64; i++) { |
| 4439 | udelay(10); |
| 4440 | mdic = E1000_READ_REG(hw, MDIC); |
| 4441 | if (mdic & E1000_MDIC_READY) |
| 4442 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4443 | } |
| 4444 | if (!(mdic & E1000_MDIC_READY)) { |
| 4445 | DEBUGOUT("MDI Write did not complete\n"); |
| 4446 | return -E1000_ERR_PHY; |
| 4447 | } |
| 4448 | } else { |
| 4449 | /* We'll need to use the SW defined pins to shift the write command |
| 4450 | * out to the PHY. We first send a preamble to the PHY to signal the |
| 4451 | * beginning of the MII instruction. This is done by sending 32 |
| 4452 | * consecutive "1" bits. |
| 4453 | */ |
| 4454 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
| 4455 | |
| 4456 | /* Now combine the remaining required fields that will indicate a |
| 4457 | * write operation. We use this method instead of calling the |
| 4458 | * e1000_shift_out_mdi_bits routine for each field in the command. The |
| 4459 | * format of a MII write instruction is as follows: |
| 4460 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. |
| 4461 | */ |
| 4462 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
| 4463 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
| 4464 | mdic <<= 16; |
| 4465 | mdic |= (uint32_t) phy_data; |
| 4466 | |
| 4467 | e1000_shift_out_mdi_bits(hw, mdic, 32); |
| 4468 | } |
| 4469 | return 0; |
| 4470 | } |
| 4471 | |
| 4472 | /****************************************************************************** |
| 4473 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. |
| 4474 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to |
| 4475 | * the caller to figure out how to deal with it. |
| 4476 | * |
| 4477 | * hw - Struct containing variables accessed by shared code |
| 4478 | * |
| 4479 | * returns: - E1000_BLK_PHY_RESET |
| 4480 | * E1000_SUCCESS |
| 4481 | * |
| 4482 | *****************************************************************************/ |
| 4483 | int32_t |
| 4484 | e1000_check_phy_reset_block(struct e1000_hw *hw) |
| 4485 | { |
| 4486 | uint32_t manc = 0; |
| 4487 | uint32_t fwsm = 0; |
| 4488 | |
| 4489 | if (hw->mac_type == e1000_ich8lan) { |
| 4490 | fwsm = E1000_READ_REG(hw, FWSM); |
| 4491 | return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS |
| 4492 | : E1000_BLK_PHY_RESET; |
| 4493 | } |
| 4494 | |
| 4495 | if (hw->mac_type > e1000_82547_rev_2) |
| 4496 | manc = E1000_READ_REG(hw, MANC); |
| 4497 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
| 4498 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |
| 4499 | } |
| 4500 | |
| 4501 | /*************************************************************************** |
| 4502 | * Checks if the PHY configuration is done |
| 4503 | * |
| 4504 | * hw: Struct containing variables accessed by shared code |
| 4505 | * |
| 4506 | * returns: - E1000_ERR_RESET if fail to reset MAC |
| 4507 | * E1000_SUCCESS at any other case. |
| 4508 | * |
| 4509 | ***************************************************************************/ |
| 4510 | static int32_t |
| 4511 | e1000_get_phy_cfg_done(struct e1000_hw *hw) |
| 4512 | { |
| 4513 | int32_t timeout = PHY_CFG_TIMEOUT; |
| 4514 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; |
| 4515 | |
| 4516 | DEBUGFUNC(); |
| 4517 | |
| 4518 | switch (hw->mac_type) { |
| 4519 | default: |
| 4520 | mdelay(10); |
| 4521 | break; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 4522 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4523 | case e1000_80003es2lan: |
| 4524 | /* Separate *_CFG_DONE_* bit for each port */ |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 4525 | if (e1000_is_second_port(hw)) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4526 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 4527 | /* Fall Through */ |
| 4528 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4529 | case e1000_82571: |
| 4530 | case e1000_82572: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 4531 | case e1000_igb: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4532 | while (timeout) { |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 4533 | if (hw->mac_type == e1000_igb) { |
| 4534 | if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) |
| 4535 | break; |
| 4536 | } else { |
| 4537 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
| 4538 | break; |
| 4539 | } |
| 4540 | mdelay(1); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4541 | timeout--; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4542 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4543 | if (!timeout) { |
| 4544 | DEBUGOUT("MNG configuration cycle has not " |
| 4545 | "completed.\n"); |
| 4546 | return -E1000_ERR_RESET; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4547 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4548 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4549 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4550 | |
| 4551 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4552 | } |
| 4553 | |
| 4554 | /****************************************************************************** |
| 4555 | * Returns the PHY to the power-on reset state |
| 4556 | * |
| 4557 | * hw - Struct containing variables accessed by shared code |
| 4558 | ******************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4559 | int32_t |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4560 | e1000_phy_hw_reset(struct e1000_hw *hw) |
| 4561 | { |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 4562 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4563 | uint32_t ctrl, ctrl_ext; |
| 4564 | uint32_t led_ctrl; |
| 4565 | int32_t ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4566 | |
| 4567 | DEBUGFUNC(); |
| 4568 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4569 | /* In the case of the phy reset being blocked, it's not an error, we |
| 4570 | * simply return success without performing the reset. */ |
| 4571 | ret_val = e1000_check_phy_reset_block(hw); |
| 4572 | if (ret_val) |
| 4573 | return E1000_SUCCESS; |
| 4574 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4575 | DEBUGOUT("Resetting Phy...\n"); |
| 4576 | |
| 4577 | if (hw->mac_type > e1000_82543) { |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 4578 | if (e1000_is_second_port(hw)) |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4579 | swfw = E1000_SWFW_PHY1_SM; |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 4580 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4581 | if (e1000_swfw_sync_acquire(hw, swfw)) { |
| 4582 | DEBUGOUT("Unable to acquire swfw sync\n"); |
| 4583 | return -E1000_ERR_SWFW_SYNC; |
| 4584 | } |
Kyle Moffett | 7376f8d | 2010-09-13 05:52:22 +0000 | [diff] [blame] | 4585 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4586 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
| 4587 | * bit. Then, take it out of reset. |
| 4588 | */ |
| 4589 | ctrl = E1000_READ_REG(hw, CTRL); |
| 4590 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); |
| 4591 | E1000_WRITE_FLUSH(hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4592 | |
| 4593 | if (hw->mac_type < e1000_82571) |
| 4594 | udelay(10); |
| 4595 | else |
| 4596 | udelay(100); |
| 4597 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4598 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 4599 | E1000_WRITE_FLUSH(hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4600 | |
| 4601 | if (hw->mac_type >= e1000_82571) |
| 4602 | mdelay(10); |
Tim Harvey | dca3565 | 2015-05-19 10:01:19 -0700 | [diff] [blame] | 4603 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4604 | } else { |
| 4605 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
| 4606 | * bit to put the PHY into reset. Then, take it out of reset. |
| 4607 | */ |
| 4608 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 4609 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
| 4610 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
| 4611 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 4612 | E1000_WRITE_FLUSH(hw); |
| 4613 | mdelay(10); |
| 4614 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
| 4615 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 4616 | E1000_WRITE_FLUSH(hw); |
| 4617 | } |
| 4618 | udelay(150); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4619 | |
| 4620 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
| 4621 | /* Configure activity LED after PHY reset */ |
| 4622 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 4623 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 4624 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 4625 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
| 4626 | } |
| 4627 | |
Tim Harvey | 5cb59ec | 2015-05-19 10:01:18 -0700 | [diff] [blame] | 4628 | e1000_swfw_sync_release(hw, swfw); |
| 4629 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4630 | /* Wait for FW to finish PHY configuration. */ |
| 4631 | ret_val = e1000_get_phy_cfg_done(hw); |
| 4632 | if (ret_val != E1000_SUCCESS) |
| 4633 | return ret_val; |
| 4634 | |
| 4635 | return ret_val; |
| 4636 | } |
| 4637 | |
| 4638 | /****************************************************************************** |
| 4639 | * IGP phy init script - initializes the GbE PHY |
| 4640 | * |
| 4641 | * hw - Struct containing variables accessed by shared code |
| 4642 | *****************************************************************************/ |
| 4643 | static void |
| 4644 | e1000_phy_init_script(struct e1000_hw *hw) |
| 4645 | { |
| 4646 | uint32_t ret_val; |
| 4647 | uint16_t phy_saved_data; |
| 4648 | DEBUGFUNC(); |
| 4649 | |
| 4650 | if (hw->phy_init_script) { |
| 4651 | mdelay(20); |
| 4652 | |
| 4653 | /* Save off the current value of register 0x2F5B to be |
| 4654 | * restored at the end of this routine. */ |
| 4655 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 4656 | |
| 4657 | /* Disabled the PHY transmitter */ |
| 4658 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 4659 | |
| 4660 | mdelay(20); |
| 4661 | |
| 4662 | e1000_write_phy_reg(hw, 0x0000, 0x0140); |
| 4663 | |
| 4664 | mdelay(5); |
| 4665 | |
| 4666 | switch (hw->mac_type) { |
| 4667 | case e1000_82541: |
| 4668 | case e1000_82547: |
| 4669 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); |
| 4670 | |
| 4671 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); |
| 4672 | |
| 4673 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); |
| 4674 | |
| 4675 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); |
| 4676 | |
| 4677 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); |
| 4678 | |
| 4679 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); |
| 4680 | |
| 4681 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); |
| 4682 | |
| 4683 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); |
| 4684 | |
| 4685 | e1000_write_phy_reg(hw, 0x2010, 0x0008); |
| 4686 | break; |
| 4687 | |
| 4688 | case e1000_82541_rev_2: |
| 4689 | case e1000_82547_rev_2: |
| 4690 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
| 4691 | break; |
| 4692 | default: |
| 4693 | break; |
| 4694 | } |
| 4695 | |
| 4696 | e1000_write_phy_reg(hw, 0x0000, 0x3300); |
| 4697 | |
| 4698 | mdelay(20); |
| 4699 | |
| 4700 | /* Now enable the transmitter */ |
Zang Roy-R61911 | e36d67c | 2011-11-06 22:22:36 +0000 | [diff] [blame] | 4701 | if (!ret_val) |
| 4702 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4703 | |
| 4704 | if (hw->mac_type == e1000_82547) { |
| 4705 | uint16_t fused, fine, coarse; |
| 4706 | |
| 4707 | /* Move to analog registers page */ |
| 4708 | e1000_read_phy_reg(hw, |
| 4709 | IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); |
| 4710 | |
| 4711 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
| 4712 | e1000_read_phy_reg(hw, |
| 4713 | IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
| 4714 | |
| 4715 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
| 4716 | coarse = fused |
| 4717 | & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
| 4718 | |
| 4719 | if (coarse > |
| 4720 | IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
| 4721 | coarse -= |
| 4722 | IGP01E1000_ANALOG_FUSE_COARSE_10; |
| 4723 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
| 4724 | } else if (coarse |
| 4725 | == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
| 4726 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
| 4727 | |
| 4728 | fused = (fused |
| 4729 | & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
| 4730 | (fine |
| 4731 | & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
| 4732 | (coarse |
| 4733 | & IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
| 4734 | |
| 4735 | e1000_write_phy_reg(hw, |
| 4736 | IGP01E1000_ANALOG_FUSE_CONTROL, fused); |
| 4737 | e1000_write_phy_reg(hw, |
| 4738 | IGP01E1000_ANALOG_FUSE_BYPASS, |
| 4739 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
| 4740 | } |
| 4741 | } |
| 4742 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4743 | } |
| 4744 | |
| 4745 | /****************************************************************************** |
| 4746 | * Resets the PHY |
| 4747 | * |
| 4748 | * hw - Struct containing variables accessed by shared code |
| 4749 | * |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4750 | * Sets bit 15 of the MII Control register |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4751 | ******************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4752 | int32_t |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4753 | e1000_phy_reset(struct e1000_hw *hw) |
| 4754 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4755 | int32_t ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4756 | uint16_t phy_data; |
| 4757 | |
| 4758 | DEBUGFUNC(); |
| 4759 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4760 | /* In the case of the phy reset being blocked, it's not an error, we |
| 4761 | * simply return success without performing the reset. */ |
| 4762 | ret_val = e1000_check_phy_reset_block(hw); |
| 4763 | if (ret_val) |
| 4764 | return E1000_SUCCESS; |
| 4765 | |
| 4766 | switch (hw->phy_type) { |
| 4767 | case e1000_phy_igp: |
| 4768 | case e1000_phy_igp_2: |
| 4769 | case e1000_phy_igp_3: |
| 4770 | case e1000_phy_ife: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 4771 | case e1000_phy_igb: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4772 | ret_val = e1000_phy_hw_reset(hw); |
| 4773 | if (ret_val) |
| 4774 | return ret_val; |
| 4775 | break; |
| 4776 | default: |
| 4777 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
| 4778 | if (ret_val) |
| 4779 | return ret_val; |
| 4780 | |
| 4781 | phy_data |= MII_CR_RESET; |
| 4782 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
| 4783 | if (ret_val) |
| 4784 | return ret_val; |
| 4785 | |
| 4786 | udelay(1); |
| 4787 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4788 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4789 | |
| 4790 | if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
| 4791 | e1000_phy_init_script(hw); |
| 4792 | |
| 4793 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4794 | } |
| 4795 | |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4796 | static int e1000_set_phy_type (struct e1000_hw *hw) |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4797 | { |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4798 | DEBUGFUNC (); |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4799 | |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4800 | if (hw->mac_type == e1000_undefined) |
| 4801 | return -E1000_ERR_PHY_TYPE; |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4802 | |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4803 | switch (hw->phy_id) { |
| 4804 | case M88E1000_E_PHY_ID: |
| 4805 | case M88E1000_I_PHY_ID: |
| 4806 | case M88E1011_I_PHY_ID: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4807 | case M88E1111_I_PHY_ID: |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4808 | hw->phy_type = e1000_phy_m88; |
| 4809 | break; |
| 4810 | case IGP01E1000_I_PHY_ID: |
| 4811 | if (hw->mac_type == e1000_82541 || |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4812 | hw->mac_type == e1000_82541_rev_2 || |
| 4813 | hw->mac_type == e1000_82547 || |
| 4814 | hw->mac_type == e1000_82547_rev_2) { |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4815 | hw->phy_type = e1000_phy_igp; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4816 | break; |
| 4817 | } |
| 4818 | case IGP03E1000_E_PHY_ID: |
| 4819 | hw->phy_type = e1000_phy_igp_3; |
| 4820 | break; |
| 4821 | case IFE_E_PHY_ID: |
| 4822 | case IFE_PLUS_E_PHY_ID: |
| 4823 | case IFE_C_E_PHY_ID: |
| 4824 | hw->phy_type = e1000_phy_ife; |
| 4825 | break; |
| 4826 | case GG82563_E_PHY_ID: |
| 4827 | if (hw->mac_type == e1000_80003es2lan) { |
| 4828 | hw->phy_type = e1000_phy_gg82563; |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4829 | break; |
| 4830 | } |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 4831 | case BME1000_E_PHY_ID: |
| 4832 | hw->phy_type = e1000_phy_bm; |
| 4833 | break; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 4834 | case I210_I_PHY_ID: |
| 4835 | hw->phy_type = e1000_phy_igb; |
| 4836 | break; |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4837 | /* Fall Through */ |
| 4838 | default: |
| 4839 | /* Should never have loaded on this device */ |
| 4840 | hw->phy_type = e1000_phy_undefined; |
| 4841 | return -E1000_ERR_PHY_TYPE; |
| 4842 | } |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4843 | |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 4844 | return E1000_SUCCESS; |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4845 | } |
| 4846 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4847 | /****************************************************************************** |
| 4848 | * Probes the expected PHY address for known PHY IDs |
| 4849 | * |
| 4850 | * hw - Struct containing variables accessed by shared code |
| 4851 | ******************************************************************************/ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4852 | static int32_t |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4853 | e1000_detect_gig_phy(struct e1000_hw *hw) |
| 4854 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4855 | int32_t phy_init_status, ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4856 | uint16_t phy_id_high, phy_id_low; |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4857 | bool match = false; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4858 | |
| 4859 | DEBUGFUNC(); |
| 4860 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4861 | /* The 82571 firmware may still be configuring the PHY. In this |
| 4862 | * case, we cannot access the PHY until the configuration is done. So |
| 4863 | * we explicitly set the PHY values. */ |
| 4864 | if (hw->mac_type == e1000_82571 || |
| 4865 | hw->mac_type == e1000_82572) { |
| 4866 | hw->phy_id = IGP01E1000_I_PHY_ID; |
| 4867 | hw->phy_type = e1000_phy_igp_2; |
| 4868 | return E1000_SUCCESS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4869 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4870 | |
| 4871 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a |
| 4872 | * work- around that forces PHY page 0 to be set or the reads fail. |
| 4873 | * The rest of the code in this routine uses e1000_read_phy_reg to |
| 4874 | * read the PHY ID. So for ESB-2 we need to have this set so our |
| 4875 | * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, |
| 4876 | * the routines below will figure this out as well. */ |
| 4877 | if (hw->mac_type == e1000_80003es2lan) |
| 4878 | hw->phy_type = e1000_phy_gg82563; |
| 4879 | |
| 4880 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
| 4881 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
| 4882 | if (ret_val) |
| 4883 | return ret_val; |
| 4884 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4885 | hw->phy_id = (uint32_t) (phy_id_high << 16); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4886 | udelay(20); |
| 4887 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
| 4888 | if (ret_val) |
| 4889 | return ret_val; |
| 4890 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4891 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4892 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4893 | |
| 4894 | switch (hw->mac_type) { |
| 4895 | case e1000_82543: |
| 4896 | if (hw->phy_id == M88E1000_E_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4897 | match = true; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4898 | break; |
| 4899 | case e1000_82544: |
| 4900 | if (hw->phy_id == M88E1000_I_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4901 | match = true; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4902 | break; |
| 4903 | case e1000_82540: |
| 4904 | case e1000_82545: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4905 | case e1000_82545_rev_3: |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4906 | case e1000_82546: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4907 | case e1000_82546_rev_3: |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4908 | if (hw->phy_id == M88E1011_I_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4909 | match = true; |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4910 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4911 | case e1000_82541: |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4912 | case e1000_82541_rev_2: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4913 | case e1000_82547: |
| 4914 | case e1000_82547_rev_2: |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4915 | if(hw->phy_id == IGP01E1000_I_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4916 | match = true; |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4917 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4918 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4919 | case e1000_82573: |
| 4920 | if (hw->phy_id == M88E1111_I_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4921 | match = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4922 | break; |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 4923 | case e1000_82574: |
| 4924 | if (hw->phy_id == BME1000_E_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4925 | match = true; |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 4926 | break; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4927 | case e1000_80003es2lan: |
| 4928 | if (hw->phy_id == GG82563_E_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4929 | match = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4930 | break; |
| 4931 | case e1000_ich8lan: |
| 4932 | if (hw->phy_id == IGP03E1000_E_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4933 | match = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4934 | if (hw->phy_id == IFE_E_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4935 | match = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4936 | if (hw->phy_id == IFE_PLUS_E_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4937 | match = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4938 | if (hw->phy_id == IFE_C_E_PHY_ID) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4939 | match = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4940 | break; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 4941 | case e1000_igb: |
| 4942 | if (hw->phy_id == I210_I_PHY_ID) |
| 4943 | match = true; |
| 4944 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4945 | default: |
| 4946 | DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); |
| 4947 | return -E1000_ERR_CONFIG; |
| 4948 | } |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 4949 | |
| 4950 | phy_init_status = e1000_set_phy_type(hw); |
| 4951 | |
| 4952 | if ((match) && (phy_init_status == E1000_SUCCESS)) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4953 | DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); |
| 4954 | return 0; |
| 4955 | } |
| 4956 | DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); |
| 4957 | return -E1000_ERR_PHY; |
| 4958 | } |
| 4959 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4960 | /***************************************************************************** |
| 4961 | * Set media type and TBI compatibility. |
| 4962 | * |
| 4963 | * hw - Struct containing variables accessed by shared code |
| 4964 | * **************************************************************************/ |
| 4965 | void |
| 4966 | e1000_set_media_type(struct e1000_hw *hw) |
| 4967 | { |
| 4968 | uint32_t status; |
| 4969 | |
| 4970 | DEBUGFUNC(); |
| 4971 | |
| 4972 | if (hw->mac_type != e1000_82543) { |
| 4973 | /* tbi_compatibility is only valid on 82543 */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 4974 | hw->tbi_compatibility_en = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4975 | } |
| 4976 | |
| 4977 | switch (hw->device_id) { |
| 4978 | case E1000_DEV_ID_82545GM_SERDES: |
| 4979 | case E1000_DEV_ID_82546GB_SERDES: |
| 4980 | case E1000_DEV_ID_82571EB_SERDES: |
| 4981 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
| 4982 | case E1000_DEV_ID_82571EB_SERDES_QUAD: |
| 4983 | case E1000_DEV_ID_82572EI_SERDES: |
| 4984 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
| 4985 | hw->media_type = e1000_media_type_internal_serdes; |
| 4986 | break; |
| 4987 | default: |
| 4988 | switch (hw->mac_type) { |
| 4989 | case e1000_82542_rev2_0: |
| 4990 | case e1000_82542_rev2_1: |
| 4991 | hw->media_type = e1000_media_type_fiber; |
| 4992 | break; |
| 4993 | case e1000_ich8lan: |
| 4994 | case e1000_82573: |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 4995 | case e1000_82574: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 4996 | case e1000_igb: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 4997 | /* The STATUS_TBIMODE bit is reserved or reused |
| 4998 | * for the this device. |
| 4999 | */ |
| 5000 | hw->media_type = e1000_media_type_copper; |
| 5001 | break; |
| 5002 | default: |
| 5003 | status = E1000_READ_REG(hw, STATUS); |
| 5004 | if (status & E1000_STATUS_TBIMODE) { |
| 5005 | hw->media_type = e1000_media_type_fiber; |
| 5006 | /* tbi_compatibility not valid on fiber */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 5007 | hw->tbi_compatibility_en = false; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5008 | } else { |
| 5009 | hw->media_type = e1000_media_type_copper; |
| 5010 | } |
| 5011 | break; |
| 5012 | } |
| 5013 | } |
| 5014 | } |
| 5015 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5016 | /** |
| 5017 | * e1000_sw_init - Initialize general software structures (struct e1000_adapter) |
| 5018 | * |
| 5019 | * e1000_sw_init initializes the Adapter private data structure. |
| 5020 | * Fields are initialized based on PCI device information and |
| 5021 | * OS network device settings (MTU size). |
| 5022 | **/ |
| 5023 | |
| 5024 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5025 | e1000_sw_init(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5026 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5027 | int result; |
| 5028 | |
| 5029 | /* PCI config space info */ |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 5030 | dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); |
| 5031 | dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); |
| 5032 | dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, |
| 5033 | &hw->subsystem_vendor_id); |
| 5034 | dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); |
| 5035 | |
| 5036 | dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); |
| 5037 | dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5038 | |
| 5039 | /* identify the MAC */ |
| 5040 | result = e1000_set_mac_type(hw); |
| 5041 | if (result) { |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5042 | E1000_ERR(hw, "Unknown MAC Type\n"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5043 | return result; |
| 5044 | } |
| 5045 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5046 | switch (hw->mac_type) { |
| 5047 | default: |
| 5048 | break; |
| 5049 | case e1000_82541: |
| 5050 | case e1000_82547: |
| 5051 | case e1000_82541_rev_2: |
| 5052 | case e1000_82547_rev_2: |
| 5053 | hw->phy_init_script = 1; |
| 5054 | break; |
| 5055 | } |
| 5056 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5057 | /* flow control settings */ |
| 5058 | hw->fc_high_water = E1000_FC_HIGH_THRESH; |
| 5059 | hw->fc_low_water = E1000_FC_LOW_THRESH; |
| 5060 | hw->fc_pause_time = E1000_FC_PAUSE_TIME; |
| 5061 | hw->fc_send_xon = 1; |
| 5062 | |
| 5063 | /* Media type - copper or fiber */ |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 5064 | hw->tbi_compatibility_en = true; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5065 | e1000_set_media_type(hw); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5066 | |
| 5067 | if (hw->mac_type >= e1000_82543) { |
| 5068 | uint32_t status = E1000_READ_REG(hw, STATUS); |
| 5069 | |
| 5070 | if (status & E1000_STATUS_TBIMODE) { |
| 5071 | DEBUGOUT("fiber interface\n"); |
| 5072 | hw->media_type = e1000_media_type_fiber; |
| 5073 | } else { |
| 5074 | DEBUGOUT("copper interface\n"); |
| 5075 | hw->media_type = e1000_media_type_copper; |
| 5076 | } |
| 5077 | } else { |
| 5078 | hw->media_type = e1000_media_type_fiber; |
| 5079 | } |
| 5080 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 5081 | hw->wait_autoneg_complete = true; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5082 | if (hw->mac_type < e1000_82543) |
| 5083 | hw->report_tx_early = 0; |
| 5084 | else |
| 5085 | hw->report_tx_early = 1; |
| 5086 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5087 | return E1000_SUCCESS; |
| 5088 | } |
| 5089 | |
| 5090 | void |
| 5091 | fill_rx(struct e1000_hw *hw) |
| 5092 | { |
| 5093 | struct e1000_rx_desc *rd; |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5094 | unsigned long flush_start, flush_end; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5095 | |
| 5096 | rx_last = rx_tail; |
| 5097 | rd = rx_base + rx_tail; |
| 5098 | rx_tail = (rx_tail + 1) % 8; |
| 5099 | memset(rd, 0, 16); |
Stefan Roese | e178994 | 2020-11-16 18:02:30 +0100 | [diff] [blame] | 5100 | rd->buffer_addr = cpu_to_le64(virt_to_phys(packet)); |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5101 | |
| 5102 | /* |
| 5103 | * Make sure there are no stale data in WB over this area, which |
| 5104 | * might get written into the memory while the e1000 also writes |
| 5105 | * into the same memory area. |
| 5106 | */ |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5107 | invalidate_dcache_range((unsigned long)packet, |
| 5108 | (unsigned long)packet + 4096); |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5109 | /* Dump the DMA descriptor into RAM. */ |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5110 | flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5111 | flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); |
| 5112 | flush_dcache_range(flush_start, flush_end); |
| 5113 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5114 | E1000_WRITE_REG(hw, RDT, rx_tail); |
| 5115 | } |
| 5116 | |
| 5117 | /** |
| 5118 | * e1000_configure_tx - Configure 8254x Transmit Unit after Reset |
| 5119 | * @adapter: board private structure |
| 5120 | * |
| 5121 | * Configure the Tx unit of the MAC after a reset. |
| 5122 | **/ |
| 5123 | |
| 5124 | static void |
| 5125 | e1000_configure_tx(struct e1000_hw *hw) |
| 5126 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5127 | unsigned long tctl; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5128 | unsigned long tipg, tarc; |
| 5129 | uint32_t ipgr1, ipgr2; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5130 | |
Stefan Roese | e178994 | 2020-11-16 18:02:30 +0100 | [diff] [blame] | 5131 | E1000_WRITE_REG(hw, TDBAL, lower_32_bits(virt_to_phys(tx_base))); |
| 5132 | E1000_WRITE_REG(hw, TDBAH, upper_32_bits(virt_to_phys(tx_base))); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5133 | |
| 5134 | E1000_WRITE_REG(hw, TDLEN, 128); |
| 5135 | |
| 5136 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
| 5137 | E1000_WRITE_REG(hw, TDH, 0); |
| 5138 | E1000_WRITE_REG(hw, TDT, 0); |
| 5139 | tx_tail = 0; |
| 5140 | |
| 5141 | /* Set the default values for the Tx Inter Packet Gap timer */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5142 | if (hw->mac_type <= e1000_82547_rev_2 && |
| 5143 | (hw->media_type == e1000_media_type_fiber || |
| 5144 | hw->media_type == e1000_media_type_internal_serdes)) |
| 5145 | tipg = DEFAULT_82543_TIPG_IPGT_FIBER; |
| 5146 | else |
| 5147 | tipg = DEFAULT_82543_TIPG_IPGT_COPPER; |
| 5148 | |
| 5149 | /* Set the default values for the Tx Inter Packet Gap timer */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5150 | switch (hw->mac_type) { |
| 5151 | case e1000_82542_rev2_0: |
| 5152 | case e1000_82542_rev2_1: |
| 5153 | tipg = DEFAULT_82542_TIPG_IPGT; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5154 | ipgr1 = DEFAULT_82542_TIPG_IPGR1; |
| 5155 | ipgr2 = DEFAULT_82542_TIPG_IPGR2; |
| 5156 | break; |
| 5157 | case e1000_80003es2lan: |
| 5158 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; |
| 5159 | ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5160 | break; |
| 5161 | default: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5162 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; |
| 5163 | ipgr2 = DEFAULT_82543_TIPG_IPGR2; |
| 5164 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5165 | } |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5166 | tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; |
| 5167 | tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5168 | E1000_WRITE_REG(hw, TIPG, tipg); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5169 | /* Program the Transmit Control Register */ |
| 5170 | tctl = E1000_READ_REG(hw, TCTL); |
| 5171 | tctl &= ~E1000_TCTL_CT; |
| 5172 | tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | |
| 5173 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5174 | |
| 5175 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { |
| 5176 | tarc = E1000_READ_REG(hw, TARC0); |
| 5177 | /* set the speed mode bit, we'll clear it if we're not at |
| 5178 | * gigabit link later */ |
| 5179 | /* git bit can be set to 1*/ |
| 5180 | } else if (hw->mac_type == e1000_80003es2lan) { |
| 5181 | tarc = E1000_READ_REG(hw, TARC0); |
| 5182 | tarc |= 1; |
| 5183 | E1000_WRITE_REG(hw, TARC0, tarc); |
| 5184 | tarc = E1000_READ_REG(hw, TARC1); |
| 5185 | tarc |= 1; |
| 5186 | E1000_WRITE_REG(hw, TARC1, tarc); |
| 5187 | } |
| 5188 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5189 | |
| 5190 | e1000_config_collision_dist(hw); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5191 | /* Setup Transmit Descriptor Settings for eop descriptor */ |
| 5192 | hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5193 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5194 | /* Need to set up RS bit */ |
| 5195 | if (hw->mac_type < e1000_82543) |
| 5196 | hw->txd_cmd |= E1000_TXD_CMD_RPS; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5197 | else |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5198 | hw->txd_cmd |= E1000_TXD_CMD_RS; |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 5199 | |
| 5200 | |
| 5201 | if (hw->mac_type == e1000_igb) { |
| 5202 | E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); |
| 5203 | |
| 5204 | uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); |
| 5205 | reg_txdctl |= 1 << 25; |
| 5206 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); |
| 5207 | mdelay(20); |
| 5208 | } |
| 5209 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5210 | E1000_WRITE_REG(hw, TCTL, tctl); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5211 | } |
| 5212 | |
| 5213 | /** |
| 5214 | * e1000_setup_rctl - configure the receive control register |
| 5215 | * @adapter: Board private structure |
| 5216 | **/ |
| 5217 | static void |
| 5218 | e1000_setup_rctl(struct e1000_hw *hw) |
| 5219 | { |
| 5220 | uint32_t rctl; |
| 5221 | |
| 5222 | rctl = E1000_READ_REG(hw, RCTL); |
| 5223 | |
| 5224 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); |
| 5225 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5226 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
| 5227 | | E1000_RCTL_RDMTS_HALF; /* | |
| 5228 | (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5229 | |
| 5230 | if (hw->tbi_compatibility_on == 1) |
| 5231 | rctl |= E1000_RCTL_SBP; |
| 5232 | else |
| 5233 | rctl &= ~E1000_RCTL_SBP; |
| 5234 | |
| 5235 | rctl &= ~(E1000_RCTL_SZ_4096); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5236 | rctl |= E1000_RCTL_SZ_2048; |
| 5237 | rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5238 | E1000_WRITE_REG(hw, RCTL, rctl); |
| 5239 | } |
| 5240 | |
| 5241 | /** |
| 5242 | * e1000_configure_rx - Configure 8254x Receive Unit after Reset |
| 5243 | * @adapter: board private structure |
| 5244 | * |
| 5245 | * Configure the Rx unit of the MAC after a reset. |
| 5246 | **/ |
| 5247 | static void |
| 5248 | e1000_configure_rx(struct e1000_hw *hw) |
| 5249 | { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5250 | unsigned long rctl, ctrl_ext; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5251 | rx_tail = 0; |
Bin Meng | d0ee7d0 | 2015-08-26 06:17:27 -0700 | [diff] [blame] | 5252 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5253 | /* make sure receives are disabled while setting up the descriptors */ |
| 5254 | rctl = E1000_READ_REG(hw, RCTL); |
| 5255 | E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5256 | if (hw->mac_type >= e1000_82540) { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5257 | /* Set the interrupt throttling rate. Value is calculated |
| 5258 | * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ |
Wolfgang Denk | 35f734f | 2008-04-13 09:59:26 -0700 | [diff] [blame] | 5259 | #define MAX_INTS_PER_SEC 8000 |
| 5260 | #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5261 | E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); |
| 5262 | } |
| 5263 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5264 | if (hw->mac_type >= e1000_82571) { |
| 5265 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 5266 | /* Reset delay timers after every interrupt */ |
| 5267 | ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; |
| 5268 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 5269 | E1000_WRITE_FLUSH(hw); |
| 5270 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5271 | /* Setup the Base and Length of the Rx Descriptor Ring */ |
Stefan Roese | e178994 | 2020-11-16 18:02:30 +0100 | [diff] [blame] | 5272 | E1000_WRITE_REG(hw, RDBAL, lower_32_bits(virt_to_phys(rx_base))); |
| 5273 | E1000_WRITE_REG(hw, RDBAH, upper_32_bits(virt_to_phys(rx_base))); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5274 | |
| 5275 | E1000_WRITE_REG(hw, RDLEN, 128); |
| 5276 | |
| 5277 | /* Setup the HW Rx Head and Tail Descriptor Pointers */ |
| 5278 | E1000_WRITE_REG(hw, RDH, 0); |
| 5279 | E1000_WRITE_REG(hw, RDT, 0); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5280 | /* Enable Receives */ |
| 5281 | |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 5282 | if (hw->mac_type == e1000_igb) { |
| 5283 | |
| 5284 | uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); |
| 5285 | reg_rxdctl |= 1 << 25; |
| 5286 | E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); |
| 5287 | mdelay(20); |
| 5288 | } |
| 5289 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5290 | E1000_WRITE_REG(hw, RCTL, rctl); |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 5291 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5292 | fill_rx(hw); |
| 5293 | } |
| 5294 | |
| 5295 | /************************************************************************** |
| 5296 | POLL - Wait for a frame |
| 5297 | ***************************************************************************/ |
| 5298 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5299 | _e1000_poll(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5300 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5301 | struct e1000_rx_desc *rd; |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5302 | unsigned long inval_start, inval_end; |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5303 | uint32_t len; |
| 5304 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5305 | /* return true if there's an ethernet packet ready to read */ |
| 5306 | rd = rx_base + rx_last; |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5307 | |
| 5308 | /* Re-load the descriptor from RAM. */ |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5309 | inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5310 | inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); |
| 5311 | invalidate_dcache_range(inval_start, inval_end); |
| 5312 | |
Miao Yan | 41a084a | 2015-12-21 02:07:02 -0800 | [diff] [blame] | 5313 | if (!(rd->status & E1000_RXD_STAT_DD)) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5314 | return 0; |
Minghuan Lian | 674bcd5 | 2015-03-19 09:43:51 -0700 | [diff] [blame] | 5315 | /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5316 | /* Packet received, make sure the data are re-loaded from RAM. */ |
Miao Yan | 41a084a | 2015-12-21 02:07:02 -0800 | [diff] [blame] | 5317 | len = le16_to_cpu(rd->length); |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5318 | invalidate_dcache_range((unsigned long)packet, |
| 5319 | (unsigned long)packet + |
| 5320 | roundup(len, ARCH_DMA_MINALIGN)); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5321 | return len; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5322 | } |
| 5323 | |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5324 | static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5325 | { |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5326 | void *nv_packet = (void *)txpacket; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5327 | struct e1000_tx_desc *txp; |
| 5328 | int i = 0; |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5329 | unsigned long flush_start, flush_end; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5330 | |
| 5331 | txp = tx_base + tx_tail; |
| 5332 | tx_tail = (tx_tail + 1) % 8; |
| 5333 | |
Stefan Roese | 0a1a329 | 2020-11-16 18:02:29 +0100 | [diff] [blame] | 5334 | txp->buffer_addr = cpu_to_le64(virt_to_phys(nv_packet)); |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5335 | txp->lower.data = cpu_to_le32(hw->txd_cmd | length); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5336 | txp->upper.data = 0; |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5337 | |
| 5338 | /* Dump the packet into RAM so e1000 can pick them. */ |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5339 | flush_dcache_range((unsigned long)nv_packet, |
| 5340 | (unsigned long)nv_packet + |
| 5341 | roundup(length, ARCH_DMA_MINALIGN)); |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5342 | /* Dump the descriptor into RAM as well. */ |
Minghuan Lian | e2e4b78 | 2015-01-22 13:21:54 +0800 | [diff] [blame] | 5343 | flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5344 | flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); |
| 5345 | flush_dcache_range(flush_start, flush_end); |
| 5346 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5347 | E1000_WRITE_REG(hw, TDT, tx_tail); |
| 5348 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5349 | E1000_WRITE_FLUSH(hw); |
Marek Vasut | 742c5c2 | 2014-08-08 07:41:38 -0700 | [diff] [blame] | 5350 | while (1) { |
| 5351 | invalidate_dcache_range(flush_start, flush_end); |
| 5352 | if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) |
| 5353 | break; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5354 | if (i++ > TOUT_LOOP) { |
| 5355 | DEBUGOUT("e1000: tx timeout\n"); |
| 5356 | return 0; |
| 5357 | } |
| 5358 | udelay(10); /* give the nic a chance to write to the register */ |
| 5359 | } |
| 5360 | return 1; |
| 5361 | } |
| 5362 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5363 | static void |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5364 | _e1000_disable(struct e1000_hw *hw) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5365 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5366 | /* Turn off the ethernet interface */ |
| 5367 | E1000_WRITE_REG(hw, RCTL, 0); |
| 5368 | E1000_WRITE_REG(hw, TCTL, 0); |
| 5369 | |
| 5370 | /* Clear the transmit ring */ |
| 5371 | E1000_WRITE_REG(hw, TDH, 0); |
| 5372 | E1000_WRITE_REG(hw, TDT, 0); |
| 5373 | |
| 5374 | /* Clear the receive ring */ |
| 5375 | E1000_WRITE_REG(hw, RDH, 0); |
| 5376 | E1000_WRITE_REG(hw, RDT, 0); |
| 5377 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5378 | mdelay(10); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5379 | } |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5380 | |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5381 | /*reset function*/ |
| 5382 | static inline int |
| 5383 | e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) |
| 5384 | { |
| 5385 | e1000_reset_hw(hw); |
| 5386 | if (hw->mac_type >= e1000_82544) |
| 5387 | E1000_WRITE_REG(hw, WUC, 0); |
| 5388 | |
| 5389 | return e1000_init_hw(hw, enetaddr); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5390 | } |
| 5391 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5392 | static int |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5393 | _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5394 | { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5395 | int ret_val = 0; |
| 5396 | |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5397 | ret_val = e1000_reset(hw, enetaddr); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5398 | if (ret_val < 0) { |
| 5399 | if ((ret_val == -E1000_ERR_NOLINK) || |
| 5400 | (ret_val == -E1000_ERR_TIMEOUT)) { |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5401 | E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5402 | } else { |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5403 | E1000_ERR(hw, "Hardware Initialization Failed\n"); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5404 | } |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5405 | return ret_val; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5406 | } |
| 5407 | e1000_configure_tx(hw); |
| 5408 | e1000_setup_rctl(hw); |
| 5409 | e1000_configure_rx(hw); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5410 | return 0; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 5411 | } |
| 5412 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5413 | /****************************************************************************** |
| 5414 | * Gets the current PCI bus type of hardware |
| 5415 | * |
| 5416 | * hw - Struct containing variables accessed by shared code |
| 5417 | *****************************************************************************/ |
| 5418 | void e1000_get_bus_type(struct e1000_hw *hw) |
| 5419 | { |
| 5420 | uint32_t status; |
| 5421 | |
| 5422 | switch (hw->mac_type) { |
| 5423 | case e1000_82542_rev2_0: |
| 5424 | case e1000_82542_rev2_1: |
| 5425 | hw->bus_type = e1000_bus_type_pci; |
| 5426 | break; |
| 5427 | case e1000_82571: |
| 5428 | case e1000_82572: |
| 5429 | case e1000_82573: |
Roy Zang | 181119b | 2011-01-21 11:29:38 +0800 | [diff] [blame] | 5430 | case e1000_82574: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5431 | case e1000_80003es2lan: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5432 | case e1000_ich8lan: |
Marek Vasut | 74a13c2 | 2014-08-08 07:41:39 -0700 | [diff] [blame] | 5433 | case e1000_igb: |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 5434 | hw->bus_type = e1000_bus_type_pci_express; |
| 5435 | break; |
| 5436 | default: |
| 5437 | status = E1000_READ_REG(hw, STATUS); |
| 5438 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
| 5439 | e1000_bus_type_pcix : e1000_bus_type_pci; |
| 5440 | break; |
| 5441 | } |
| 5442 | } |
| 5443 | |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 5444 | static int e1000_init_one(struct e1000_hw *hw, int cardnum, |
| 5445 | struct udevice *devno, unsigned char enetaddr[6]) |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5446 | { |
| 5447 | u32 val; |
| 5448 | |
| 5449 | /* Assign the passed-in values */ |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 5450 | hw->pdev = devno; |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5451 | hw->cardnum = cardnum; |
| 5452 | |
| 5453 | /* Print a debug message with the IO base address */ |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 5454 | dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5455 | E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); |
| 5456 | |
| 5457 | /* Try to enable I/O accesses and bus-mastering */ |
| 5458 | val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 5459 | dm_pci_write_config32(devno, PCI_COMMAND, val); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5460 | |
| 5461 | /* Make sure it worked */ |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 5462 | dm_pci_read_config32(devno, PCI_COMMAND, &val); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5463 | if (!(val & PCI_COMMAND_MEMORY)) { |
| 5464 | E1000_ERR(hw, "Can't enable I/O memory\n"); |
| 5465 | return -ENOSPC; |
| 5466 | } |
| 5467 | if (!(val & PCI_COMMAND_MASTER)) { |
| 5468 | E1000_ERR(hw, "Can't enable bus-mastering\n"); |
| 5469 | return -EPERM; |
| 5470 | } |
| 5471 | |
| 5472 | /* Are these variables needed? */ |
| 5473 | hw->fc = e1000_fc_default; |
| 5474 | hw->original_fc = e1000_fc_default; |
| 5475 | hw->autoneg_failed = 0; |
| 5476 | hw->autoneg = 1; |
| 5477 | hw->get_link_status = true; |
| 5478 | #ifndef CONFIG_E1000_NO_NVM |
| 5479 | hw->eeprom_semaphore_present = true; |
| 5480 | #endif |
Andrew Scull | 58c6102 | 2022-04-21 16:11:10 +0000 | [diff] [blame] | 5481 | hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0, |
Andrew Scull | 6520c82 | 2022-04-21 16:11:13 +0000 | [diff] [blame] | 5482 | PCI_REGION_TYPE, PCI_REGION_MEM); |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5483 | hw->mac_type = e1000_undefined; |
| 5484 | |
| 5485 | /* MAC and Phy settings */ |
| 5486 | if (e1000_sw_init(hw) < 0) { |
| 5487 | E1000_ERR(hw, "Software init failed\n"); |
| 5488 | return -EIO; |
| 5489 | } |
| 5490 | if (e1000_check_phy_reset_block(hw)) |
| 5491 | E1000_ERR(hw, "PHY Reset is blocked!\n"); |
| 5492 | |
| 5493 | /* Basic init was OK, reset the hardware and allow SPI access */ |
| 5494 | e1000_reset_hw(hw); |
| 5495 | |
| 5496 | #ifndef CONFIG_E1000_NO_NVM |
| 5497 | /* Validate the EEPROM and get chipset information */ |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5498 | if (e1000_init_eeprom_params(hw)) { |
| 5499 | E1000_ERR(hw, "EEPROM is invalid!\n"); |
| 5500 | return -EINVAL; |
| 5501 | } |
| 5502 | if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && |
| 5503 | e1000_validate_eeprom_checksum(hw)) |
| 5504 | return -ENXIO; |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5505 | e1000_read_mac_addr(hw, enetaddr); |
| 5506 | #endif |
| 5507 | e1000_get_bus_type(hw); |
| 5508 | |
| 5509 | #ifndef CONFIG_E1000_NO_NVM |
| 5510 | printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", |
| 5511 | enetaddr[0], enetaddr[1], enetaddr[2], |
| 5512 | enetaddr[3], enetaddr[4], enetaddr[5]); |
| 5513 | #else |
| 5514 | memset(enetaddr, 0, 6); |
| 5515 | printf("e1000: no NVM\n"); |
| 5516 | #endif |
| 5517 | |
| 5518 | return 0; |
| 5519 | } |
| 5520 | |
| 5521 | /* Put the name of a device in a string */ |
| 5522 | static void e1000_name(char *str, int cardnum) |
| 5523 | { |
| 5524 | sprintf(str, "e1000#%u", cardnum); |
| 5525 | } |
| 5526 | |
Ian Ray | 9635e2d | 2020-11-04 17:26:01 +0100 | [diff] [blame] | 5527 | static int e1000_write_hwaddr(struct udevice *dev) |
Hannu Lounento | 68d31f6 | 2018-01-10 20:31:26 +0100 | [diff] [blame] | 5528 | { |
| 5529 | #ifndef CONFIG_E1000_NO_NVM |
Hannu Lounento | 68d31f6 | 2018-01-10 20:31:26 +0100 | [diff] [blame] | 5530 | unsigned char current_mac[6]; |
Ian Ray | 9635e2d | 2020-11-04 17:26:01 +0100 | [diff] [blame] | 5531 | struct eth_pdata *plat = dev_get_plat(dev); |
| 5532 | struct e1000_hw *hw = dev_get_priv(dev); |
| 5533 | u8 *mac = plat->enetaddr; |
Hannu Lounento | 68d31f6 | 2018-01-10 20:31:26 +0100 | [diff] [blame] | 5534 | uint16_t data[3]; |
| 5535 | int ret_val, i; |
| 5536 | |
| 5537 | DEBUGOUT("%s: mac=%pM\n", __func__, mac); |
| 5538 | |
Tim Harvey | 893bd6e | 2021-04-16 13:25:09 -0700 | [diff] [blame] | 5539 | if ((hw->eeprom.type == e1000_eeprom_invm) && |
| 5540 | !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210)) |
| 5541 | return -ENOSYS; |
| 5542 | |
Hannu Lounento | 68d31f6 | 2018-01-10 20:31:26 +0100 | [diff] [blame] | 5543 | memset(current_mac, 0, 6); |
| 5544 | |
| 5545 | /* Read from EEPROM, not from registers, to make sure |
| 5546 | * the address is persistently configured |
| 5547 | */ |
| 5548 | ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac); |
| 5549 | DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac); |
| 5550 | |
| 5551 | /* Only write to EEPROM if the given address is different or |
| 5552 | * reading the current address failed |
| 5553 | */ |
| 5554 | if (!ret_val && memcmp(current_mac, mac, 6) == 0) |
| 5555 | return 0; |
| 5556 | |
| 5557 | for (i = 0; i < 3; ++i) |
| 5558 | data[i] = mac[i * 2 + 1] << 8 | mac[i * 2]; |
| 5559 | |
| 5560 | ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data); |
| 5561 | |
| 5562 | if (!ret_val) |
| 5563 | ret_val = e1000_update_eeprom_checksum_i210(hw); |
| 5564 | |
| 5565 | return ret_val; |
| 5566 | #else |
| 5567 | return 0; |
| 5568 | #endif |
| 5569 | } |
Kyle Moffett | 64b94dd | 2011-10-18 11:05:29 +0000 | [diff] [blame] | 5570 | |
| 5571 | #ifdef CONFIG_CMD_E1000 |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 5572 | static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc, |
| 5573 | char *const argv[]) |
Kyle Moffett | 64b94dd | 2011-10-18 11:05:29 +0000 | [diff] [blame] | 5574 | { |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5575 | unsigned char *mac = NULL; |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5576 | struct eth_pdata *plat; |
| 5577 | struct udevice *dev; |
| 5578 | char name[30]; |
| 5579 | int ret; |
Tom Rini | 90fc4ba | 2022-11-27 10:25:09 -0500 | [diff] [blame] | 5580 | #if defined(CONFIG_E1000_SPI) |
Kyle Moffett | 64b94dd | 2011-10-18 11:05:29 +0000 | [diff] [blame] | 5581 | struct e1000_hw *hw; |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5582 | #endif |
| 5583 | int cardnum; |
Kyle Moffett | 64b94dd | 2011-10-18 11:05:29 +0000 | [diff] [blame] | 5584 | |
| 5585 | if (argc < 3) { |
| 5586 | cmd_usage(cmdtp); |
| 5587 | return 1; |
| 5588 | } |
| 5589 | |
| 5590 | /* Make sure we can find the requested e1000 card */ |
Simon Glass | ff9b903 | 2021-07-24 09:03:30 -0600 | [diff] [blame] | 5591 | cardnum = dectoul(argv[1], NULL); |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5592 | e1000_name(name, cardnum); |
| 5593 | ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); |
| 5594 | if (!ret) { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 5595 | plat = dev_get_plat(dev); |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5596 | mac = plat->enetaddr; |
| 5597 | } |
Simon Glass | c53abc3 | 2015-08-19 09:33:39 -0600 | [diff] [blame] | 5598 | if (!mac) { |
Kyle Moffett | 64b94dd | 2011-10-18 11:05:29 +0000 | [diff] [blame] | 5599 | printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); |
| 5600 | return 1; |
| 5601 | } |
| 5602 | |
| 5603 | if (!strcmp(argv[2], "print-mac-address")) { |
Kyle Moffett | 64b94dd | 2011-10-18 11:05:29 +0000 | [diff] [blame] | 5604 | printf("%02x:%02x:%02x:%02x:%02x:%02x\n", |
| 5605 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); |
| 5606 | return 0; |
| 5607 | } |
| 5608 | |
| 5609 | #ifdef CONFIG_E1000_SPI |
Alban Bedel | c1255dd | 2016-08-03 11:31:03 +0200 | [diff] [blame] | 5610 | hw = dev_get_priv(dev); |
Kyle Moffett | 64b94dd | 2011-10-18 11:05:29 +0000 | [diff] [blame] | 5611 | /* Handle the "SPI" subcommand */ |
| 5612 | if (!strcmp(argv[2], "spi")) |
| 5613 | return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); |
| 5614 | #endif |
| 5615 | |
| 5616 | cmd_usage(cmdtp); |
| 5617 | return 1; |
| 5618 | } |
| 5619 | |
| 5620 | U_BOOT_CMD( |
| 5621 | e1000, 7, 0, do_e1000, |
| 5622 | "Intel e1000 controller management", |
| 5623 | /* */"<card#> print-mac-address\n" |
| 5624 | #ifdef CONFIG_E1000_SPI |
| 5625 | "e1000 <card#> spi show [<offset> [<length>]]\n" |
| 5626 | "e1000 <card#> spi dump <addr> <offset> <length>\n" |
| 5627 | "e1000 <card#> spi program <addr> <offset> <length>\n" |
| 5628 | "e1000 <card#> spi checksum [update]\n" |
| 5629 | #endif |
| 5630 | " - Manage the Intel E1000 PCI device" |
| 5631 | ); |
| 5632 | #endif /* not CONFIG_CMD_E1000 */ |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5633 | |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5634 | static int e1000_eth_start(struct udevice *dev) |
| 5635 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 5636 | struct eth_pdata *plat = dev_get_plat(dev); |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5637 | struct e1000_hw *hw = dev_get_priv(dev); |
| 5638 | |
| 5639 | return _e1000_init(hw, plat->enetaddr); |
| 5640 | } |
| 5641 | |
| 5642 | static void e1000_eth_stop(struct udevice *dev) |
| 5643 | { |
| 5644 | struct e1000_hw *hw = dev_get_priv(dev); |
| 5645 | |
| 5646 | _e1000_disable(hw); |
| 5647 | } |
| 5648 | |
| 5649 | static int e1000_eth_send(struct udevice *dev, void *packet, int length) |
| 5650 | { |
| 5651 | struct e1000_hw *hw = dev_get_priv(dev); |
| 5652 | int ret; |
| 5653 | |
| 5654 | ret = _e1000_transmit(hw, packet, length); |
| 5655 | |
| 5656 | return ret ? 0 : -ETIMEDOUT; |
| 5657 | } |
| 5658 | |
| 5659 | static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
| 5660 | { |
| 5661 | struct e1000_hw *hw = dev_get_priv(dev); |
| 5662 | int len; |
| 5663 | |
| 5664 | len = _e1000_poll(hw); |
| 5665 | if (len) |
| 5666 | *packetp = packet; |
| 5667 | |
| 5668 | return len ? len : -EAGAIN; |
| 5669 | } |
| 5670 | |
| 5671 | static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) |
| 5672 | { |
| 5673 | struct e1000_hw *hw = dev_get_priv(dev); |
| 5674 | |
| 5675 | fill_rx(hw); |
| 5676 | |
| 5677 | return 0; |
| 5678 | } |
| 5679 | |
| 5680 | static int e1000_eth_probe(struct udevice *dev) |
| 5681 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 5682 | struct eth_pdata *plat = dev_get_plat(dev); |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5683 | struct e1000_hw *hw = dev_get_priv(dev); |
| 5684 | int ret; |
| 5685 | |
| 5686 | hw->name = dev->name; |
Simon Glass | eaa1489 | 2015-11-29 13:17:47 -0700 | [diff] [blame] | 5687 | ret = e1000_init_one(hw, trailing_strtol(dev->name), |
Bin Meng | 83cf24c | 2016-02-02 05:58:01 -0800 | [diff] [blame] | 5688 | dev, plat->enetaddr); |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5689 | if (ret < 0) { |
| 5690 | printf(pr_fmt("failed to initialize card: %d\n"), ret); |
| 5691 | return ret; |
| 5692 | } |
| 5693 | |
| 5694 | return 0; |
| 5695 | } |
| 5696 | |
| 5697 | static int e1000_eth_bind(struct udevice *dev) |
| 5698 | { |
| 5699 | char name[20]; |
| 5700 | |
| 5701 | /* |
| 5702 | * A simple way to number the devices. When device tree is used this |
| 5703 | * is unnecessary, but when the device is just discovered on the PCI |
| 5704 | * bus we need a name. We could instead have the uclass figure out |
| 5705 | * which devices are different and number them. |
| 5706 | */ |
| 5707 | e1000_name(name, num_cards++); |
| 5708 | |
| 5709 | return device_set_name(dev, name); |
| 5710 | } |
| 5711 | |
| 5712 | static const struct eth_ops e1000_eth_ops = { |
| 5713 | .start = e1000_eth_start, |
| 5714 | .send = e1000_eth_send, |
| 5715 | .recv = e1000_eth_recv, |
| 5716 | .stop = e1000_eth_stop, |
| 5717 | .free_pkt = e1000_free_pkt, |
Ian Ray | 9635e2d | 2020-11-04 17:26:01 +0100 | [diff] [blame] | 5718 | .write_hwaddr = e1000_write_hwaddr, |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5719 | }; |
| 5720 | |
| 5721 | static const struct udevice_id e1000_eth_ids[] = { |
| 5722 | { .compatible = "intel,e1000" }, |
| 5723 | { } |
| 5724 | }; |
| 5725 | |
| 5726 | U_BOOT_DRIVER(eth_e1000) = { |
| 5727 | .name = "eth_e1000", |
| 5728 | .id = UCLASS_ETH, |
| 5729 | .of_match = e1000_eth_ids, |
| 5730 | .bind = e1000_eth_bind, |
| 5731 | .probe = e1000_eth_probe, |
| 5732 | .ops = &e1000_eth_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 5733 | .priv_auto = sizeof(struct e1000_hw), |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 5734 | .plat_auto = sizeof(struct eth_pdata), |
Simon Glass | 9f86b38 | 2015-08-19 09:33:40 -0600 | [diff] [blame] | 5735 | }; |
| 5736 | |
| 5737 | U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); |