blob: 4e7af95b41c44fe5290e37f67e291ae5063874a1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002
3#include <common.h>
Marek Vasut992af7d2020-07-08 06:31:54 +02004#include <asm/io.h>
Marek Vasut1d6c7382020-07-08 07:26:14 +02005#include <dm.h>
wdenkc6097192002-11-03 00:24:07 +00006#include <malloc.h>
7#include <net.h>
Ben Warren840f8a52008-08-31 10:45:44 -07008#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +00009#include <pci.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060011#include <linux/delay.h>
wdenkc6097192002-11-03 00:24:07 +000012
Marek Vasut091eea82020-04-19 04:05:44 +020013#define SROM_DLEVEL 0
wdenkc6097192002-11-03 00:24:07 +000014
Marek Vasut81d10f72020-04-19 03:09:26 +020015/* PCI Registers. */
16#define PCI_CFDA_PSM 0x43
wdenkc6097192002-11-03 00:24:07 +000017
18#define CFRV_RN 0x000000f0 /* Revision Number */
19
20#define WAKEUP 0x00 /* Power Saving Wakeup */
21#define SLEEP 0x80 /* Power Saving Sleep Mode */
22
Marek Vasut81d10f72020-04-19 03:09:26 +020023#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
wdenkc6097192002-11-03 00:24:07 +000024
Marek Vasut81d10f72020-04-19 03:09:26 +020025/* Ethernet chip registers. */
wdenkc6097192002-11-03 00:24:07 +000026#define DE4X5_BMR 0x000 /* Bus Mode Register */
27#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
28#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
29#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
30#define DE4X5_STS 0x028 /* Status Register */
31#define DE4X5_OMR 0x030 /* Operation Mode Register */
32#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
33#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
34
Marek Vasut81d10f72020-04-19 03:09:26 +020035/* Register bits. */
wdenkc6097192002-11-03 00:24:07 +000036#define BMR_SWR 0x00000001 /* Software Reset */
37#define STS_TS 0x00700000 /* Transmit Process State */
38#define STS_RS 0x000e0000 /* Receive Process State */
39#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
40#define OMR_SR 0x00000002 /* Start/Stop Receive */
41#define OMR_PS 0x00040000 /* Port Select */
42#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
43#define OMR_PM 0x00000080 /* Pass All Multicast */
44
Marek Vasut81d10f72020-04-19 03:09:26 +020045/* Descriptor bits. */
wdenkc6097192002-11-03 00:24:07 +000046#define R_OWN 0x80000000 /* Own Bit */
47#define RD_RER 0x02000000 /* Receive End Of Ring */
48#define RD_LS 0x00000100 /* Last Descriptor */
49#define RD_ES 0x00008000 /* Error Summary */
50#define TD_TER 0x02000000 /* Transmit End Of Ring */
51#define T_OWN 0x80000000 /* Own Bit */
52#define TD_LS 0x40000000 /* Last Segment */
53#define TD_FS 0x20000000 /* First Segment */
54#define TD_ES 0x00008000 /* Error Summary */
55#define TD_SET 0x08000000 /* Setup Packet */
56
57/* The EEPROM commands include the alway-set leading bit. */
58#define SROM_WRITE_CMD 5
59#define SROM_READ_CMD 6
60#define SROM_ERASE_CMD 7
61
Marek Vasut81d10f72020-04-19 03:09:26 +020062#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
wdenkc6097192002-11-03 00:24:07 +000063#define SROM_RD 0x00004000 /* Read from Boot ROM */
Marek Vasut81d10f72020-04-19 03:09:26 +020064#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
65#define EE_WRITE_0 0x4801
66#define EE_WRITE_1 0x4805
67#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
wdenkc6097192002-11-03 00:24:07 +000068#define SROM_SR 0x00000800 /* Select Serial ROM when set */
69
70#define DT_IN 0x00000004 /* Serial Data In */
71#define DT_CLK 0x00000002 /* Serial ROM Clock */
72#define DT_CS 0x00000001 /* Serial ROM Chip Select */
73
74#define POLL_DEMAND 1
75
Marek Vasut1d6c7382020-07-08 07:26:14 +020076#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
Marek Vasut75244fb2020-04-19 03:36:46 +020077
Marek Vasut5e2ad052020-04-19 04:00:49 +020078#define NUM_RX_DESC PKTBUFSRX
79#define NUM_TX_DESC 1 /* Number of TX descriptors */
80#define RX_BUFF_SZ PKTSIZE_ALIGN
81
82#define TOUT_LOOP 1000000
83
84#define SETUP_FRAME_LEN 192
85
86struct de4x5_desc {
87 volatile s32 status;
88 u32 des1;
89 u32 buf;
90 u32 next;
91};
92
Marek Vasuta3f89082020-07-08 06:42:07 +020093struct dc2114x_priv {
Marek Vasutf19db7f2020-07-08 07:01:32 +020094 struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
95 struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
96 int rx_new; /* RX descriptor ring pointer */
97 int tx_new; /* TX descriptor ring pointer */
98 char rx_ring_size;
99 char tx_ring_size;
Marek Vasut1d6c7382020-07-08 07:26:14 +0200100 struct udevice *devno;
Marek Vasuta3f89082020-07-08 06:42:07 +0200101 char *name;
102 void __iomem *iobase;
103 u8 *enetaddr;
104};
105
Marek Vasut5e2ad052020-04-19 04:00:49 +0200106/* RX and TX descriptor ring */
Marek Vasut25ada1f2020-07-08 06:46:09 +0200107static u32 dc2114x_inl(struct dc2114x_priv *priv, u32 addr)
Marek Vasut75244fb2020-04-19 03:36:46 +0200108{
Marek Vasut25ada1f2020-07-08 06:46:09 +0200109 return le32_to_cpu(readl(priv->iobase + addr));
Marek Vasut75244fb2020-04-19 03:36:46 +0200110}
111
Marek Vasut25ada1f2020-07-08 06:46:09 +0200112static void dc2114x_outl(struct dc2114x_priv *priv, u32 command, u32 addr)
Marek Vasut75244fb2020-04-19 03:36:46 +0200113{
Marek Vasut25ada1f2020-07-08 06:46:09 +0200114 writel(cpu_to_le32(command), priv->iobase + addr);
Marek Vasut75244fb2020-04-19 03:36:46 +0200115}
116
Marek Vasut25ada1f2020-07-08 06:46:09 +0200117static void reset_de4x5(struct dc2114x_priv *priv)
Marek Vasut75244fb2020-04-19 03:36:46 +0200118{
Marek Vasutf02b7012020-04-19 03:40:03 +0200119 u32 i;
Marek Vasut75244fb2020-04-19 03:36:46 +0200120
Marek Vasut25ada1f2020-07-08 06:46:09 +0200121 i = dc2114x_inl(priv, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200122 mdelay(1);
Marek Vasut25ada1f2020-07-08 06:46:09 +0200123 dc2114x_outl(priv, i | BMR_SWR, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200124 mdelay(1);
Marek Vasut25ada1f2020-07-08 06:46:09 +0200125 dc2114x_outl(priv, i, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200126 mdelay(1);
127
128 for (i = 0; i < 5; i++) {
Marek Vasut25ada1f2020-07-08 06:46:09 +0200129 dc2114x_inl(priv, DE4X5_BMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200130 mdelay(10);
131 }
132
133 mdelay(1);
wdenkc6097192002-11-03 00:24:07 +0000134}
135
Marek Vasut25ada1f2020-07-08 06:46:09 +0200136static void start_de4x5(struct dc2114x_priv *priv)
Marek Vasut75244fb2020-04-19 03:36:46 +0200137{
Marek Vasutf02b7012020-04-19 03:40:03 +0200138 u32 omr;
Marek Vasut75244fb2020-04-19 03:36:46 +0200139
Marek Vasut25ada1f2020-07-08 06:46:09 +0200140 omr = dc2114x_inl(priv, DE4X5_OMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200141 omr |= OMR_ST | OMR_SR;
Marek Vasut25ada1f2020-07-08 06:46:09 +0200142 dc2114x_outl(priv, omr, DE4X5_OMR); /* Enable the TX and/or RX */
wdenkc6097192002-11-03 00:24:07 +0000143}
144
Marek Vasut25ada1f2020-07-08 06:46:09 +0200145static void stop_de4x5(struct dc2114x_priv *priv)
Marek Vasut75244fb2020-04-19 03:36:46 +0200146{
Marek Vasutf02b7012020-04-19 03:40:03 +0200147 u32 omr;
Marek Vasut75244fb2020-04-19 03:36:46 +0200148
Marek Vasut25ada1f2020-07-08 06:46:09 +0200149 omr = dc2114x_inl(priv, DE4X5_OMR);
Marek Vasut75244fb2020-04-19 03:36:46 +0200150 omr &= ~(OMR_ST | OMR_SR);
Marek Vasut25ada1f2020-07-08 06:46:09 +0200151 dc2114x_outl(priv, omr, DE4X5_OMR); /* Disable the TX and/or RX */
wdenkc6097192002-11-03 00:24:07 +0000152}
153
Marek Vasut5e2ad052020-04-19 04:00:49 +0200154/* SROM Read and write routines. */
Marek Vasut25ada1f2020-07-08 06:46:09 +0200155static void sendto_srom(struct dc2114x_priv *priv, u_int command, u_long addr)
Marek Vasut5e2ad052020-04-19 04:00:49 +0200156{
Marek Vasut25ada1f2020-07-08 06:46:09 +0200157 dc2114x_outl(priv, command, addr);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200158 udelay(1);
159}
wdenkc6097192002-11-03 00:24:07 +0000160
Marek Vasut25ada1f2020-07-08 06:46:09 +0200161static int getfrom_srom(struct dc2114x_priv *priv, u_long addr)
Marek Vasut5e2ad052020-04-19 04:00:49 +0200162{
Marek Vasut25ada1f2020-07-08 06:46:09 +0200163 u32 tmp = dc2114x_inl(priv, addr);
wdenkc6097192002-11-03 00:24:07 +0000164
Marek Vasut5e2ad052020-04-19 04:00:49 +0200165 udelay(1);
166 return tmp;
167}
wdenkc6097192002-11-03 00:24:07 +0000168
Marek Vasut5e2ad052020-04-19 04:00:49 +0200169/* Note: this routine returns extra data bits for size detection. */
Marek Vasut25ada1f2020-07-08 06:46:09 +0200170static int do_read_eeprom(struct dc2114x_priv *priv, u_long ioaddr, int location,
Marek Vasut5e2ad052020-04-19 04:00:49 +0200171 int addr_len)
172{
173 int read_cmd = location | (SROM_READ_CMD << addr_len);
174 unsigned int retval = 0;
175 int i;
wdenkc6097192002-11-03 00:24:07 +0000176
Marek Vasut25ada1f2020-07-08 06:46:09 +0200177 sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
178 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000179
Marek Vasut091eea82020-04-19 04:05:44 +0200180 debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
wdenkc6097192002-11-03 00:24:07 +0000181
Marek Vasut5e2ad052020-04-19 04:00:49 +0200182 /* Shift the read command bits out. */
183 for (i = 4 + addr_len; i >= 0; i--) {
184 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
wdenkc6097192002-11-03 00:24:07 +0000185
Marek Vasut25ada1f2020-07-08 06:46:09 +0200186 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval,
Marek Vasut5e2ad052020-04-19 04:00:49 +0200187 ioaddr);
188 udelay(10);
Marek Vasut25ada1f2020-07-08 06:46:09 +0200189 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
Marek Vasut5e2ad052020-04-19 04:00:49 +0200190 ioaddr);
191 udelay(10);
Marek Vasut091eea82020-04-19 04:05:44 +0200192 debug_cond(SROM_DLEVEL >= 2, "%X",
Marek Vasut25ada1f2020-07-08 06:46:09 +0200193 getfrom_srom(priv, ioaddr) & 15);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200194 retval = (retval << 1) |
Marek Vasut25ada1f2020-07-08 06:46:09 +0200195 !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200196 }
wdenkc6097192002-11-03 00:24:07 +0000197
Marek Vasut25ada1f2020-07-08 06:46:09 +0200198 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000199
Marek Vasut25ada1f2020-07-08 06:46:09 +0200200 debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(priv, ioaddr) & 15);
wdenkc6097192002-11-03 00:24:07 +0000201
Marek Vasut5e2ad052020-04-19 04:00:49 +0200202 for (i = 16; i > 0; i--) {
Marek Vasut25ada1f2020-07-08 06:46:09 +0200203 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200204 udelay(10);
Marek Vasut091eea82020-04-19 04:05:44 +0200205 debug_cond(SROM_DLEVEL >= 2, "%X",
Marek Vasut25ada1f2020-07-08 06:46:09 +0200206 getfrom_srom(priv, ioaddr) & 15);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200207 retval = (retval << 1) |
Marek Vasut25ada1f2020-07-08 06:46:09 +0200208 !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
209 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200210 udelay(10);
211 }
wdenkc6097192002-11-03 00:24:07 +0000212
Marek Vasut5e2ad052020-04-19 04:00:49 +0200213 /* Terminate the EEPROM access. */
Marek Vasut25ada1f2020-07-08 06:46:09 +0200214 sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000215
Marek Vasut091eea82020-04-19 04:05:44 +0200216 debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
217 location, retval);
wdenkc6097192002-11-03 00:24:07 +0000218
Marek Vasut5e2ad052020-04-19 04:00:49 +0200219 return retval;
220}
wdenkc6097192002-11-03 00:24:07 +0000221
Marek Vasut5e2ad052020-04-19 04:00:49 +0200222/*
223 * This executes a generic EEPROM command, typically a write or write
224 * enable. It returns the data output from the EEPROM, and thus may
225 * also be used for reads.
226 */
Marek Vasut25ada1f2020-07-08 06:46:09 +0200227static int do_eeprom_cmd(struct dc2114x_priv *priv, u_long ioaddr, int cmd,
Marek Vasut5e2ad052020-04-19 04:00:49 +0200228 int cmd_len)
229{
230 unsigned int retval = 0;
wdenkc6097192002-11-03 00:24:07 +0000231
Marek Vasut091eea82020-04-19 04:05:44 +0200232 debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
wdenkc6097192002-11-03 00:24:07 +0000233
Marek Vasut25ada1f2020-07-08 06:46:09 +0200234 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000235
Marek Vasut5e2ad052020-04-19 04:00:49 +0200236 /* Shift the command bits out. */
237 do {
238 short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
wdenkc6097192002-11-03 00:24:07 +0000239
Marek Vasut25ada1f2020-07-08 06:46:09 +0200240 sendto_srom(priv, dataval, ioaddr);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200241 udelay(10);
Marek Vasut268cc5b2020-04-19 03:09:47 +0200242
Marek Vasut091eea82020-04-19 04:05:44 +0200243 debug_cond(SROM_DLEVEL >= 2, "%X",
Marek Vasut25ada1f2020-07-08 06:46:09 +0200244 getfrom_srom(priv, ioaddr) & 15);
Nobuhiro Iwamatsud45fa742010-10-19 14:03:40 +0900245
Marek Vasut25ada1f2020-07-08 06:46:09 +0200246 sendto_srom(priv, dataval | DT_CLK, ioaddr);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200247 udelay(10);
248 retval = (retval << 1) |
Marek Vasut25ada1f2020-07-08 06:46:09 +0200249 !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200250 } while (--cmd_len >= 0);
wdenk0260cd62004-01-02 15:01:32 +0000251
Marek Vasut25ada1f2020-07-08 06:46:09 +0200252 sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000253
Marek Vasut5e2ad052020-04-19 04:00:49 +0200254 /* Terminate the EEPROM access. */
Marek Vasut25ada1f2020-07-08 06:46:09 +0200255 sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
wdenkc6097192002-11-03 00:24:07 +0000256
Marek Vasut091eea82020-04-19 04:05:44 +0200257 debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
wdenkc6097192002-11-03 00:24:07 +0000258
Marek Vasut5e2ad052020-04-19 04:00:49 +0200259 return retval;
260}
Marek Vasut331e4ec2020-04-18 01:56:51 +0200261
Marek Vasut25ada1f2020-07-08 06:46:09 +0200262static int read_srom(struct dc2114x_priv *priv, u_long ioaddr, int index)
Marek Vasut5e2ad052020-04-19 04:00:49 +0200263{
264 int ee_addr_size;
wdenkc6097192002-11-03 00:24:07 +0000265
Marek Vasut25ada1f2020-07-08 06:46:09 +0200266 ee_addr_size = (do_read_eeprom(priv, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
wdenkc6097192002-11-03 00:24:07 +0000267
Marek Vasut25ada1f2020-07-08 06:46:09 +0200268 return do_eeprom_cmd(priv, ioaddr, 0xffff |
Marek Vasut5e2ad052020-04-19 04:00:49 +0200269 (((SROM_READ_CMD << ee_addr_size) | index) << 16),
270 3 + ee_addr_size + 16);
wdenkc6097192002-11-03 00:24:07 +0000271}
272
Marek Vasut29b9efc2020-07-08 07:20:14 +0200273static void send_setup_frame(struct dc2114x_priv *priv)
Marek Vasut5e2ad052020-04-19 04:00:49 +0200274{
275 char setup_frame[SETUP_FRAME_LEN];
276 char *pa = &setup_frame[0];
277 int i;
278
279 memset(pa, 0xff, SETUP_FRAME_LEN);
280
281 for (i = 0; i < ETH_ALEN; i++) {
Marek Vasut25ada1f2020-07-08 06:46:09 +0200282 *(pa + (i & 1)) = priv->enetaddr[i];
Marek Vasut5e2ad052020-04-19 04:00:49 +0200283 if (i & 0x01)
284 pa += 4;
wdenkc6097192002-11-03 00:24:07 +0000285 }
286
Marek Vasutf19db7f2020-07-08 07:01:32 +0200287 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
Marek Vasut5e2ad052020-04-19 04:00:49 +0200288 if (i < TOUT_LOOP)
289 continue;
wdenkc6097192002-11-03 00:24:07 +0000290
Marek Vasut25ada1f2020-07-08 06:46:09 +0200291 printf("%s: tx error buffer not ready\n", priv->name);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200292 return;
293 }
wdenkc6097192002-11-03 00:24:07 +0000294
Marek Vasutf19db7f2020-07-08 07:01:32 +0200295 priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutb8e0b472020-07-08 06:50:41 +0200296 (u32)&setup_frame[0]));
Marek Vasutf19db7f2020-07-08 07:01:32 +0200297 priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
298 priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
wdenkc6097192002-11-03 00:24:07 +0000299
Marek Vasut25ada1f2020-07-08 06:46:09 +0200300 dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
wdenkc6097192002-11-03 00:24:07 +0000301
Marek Vasutf19db7f2020-07-08 07:01:32 +0200302 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
Marek Vasut5e2ad052020-04-19 04:00:49 +0200303 if (i < TOUT_LOOP)
304 continue;
wdenkc6097192002-11-03 00:24:07 +0000305
Marek Vasut25ada1f2020-07-08 06:46:09 +0200306 printf("%s: tx buffer not ready\n", priv->name);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200307 return;
308 }
wdenkc6097192002-11-03 00:24:07 +0000309
Marek Vasutf19db7f2020-07-08 07:01:32 +0200310 if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) != 0x7FFFFFFF) {
Marek Vasut5e2ad052020-04-19 04:00:49 +0200311 printf("TX error status2 = 0x%08X\n",
Marek Vasutf19db7f2020-07-08 07:01:32 +0200312 le32_to_cpu(priv->tx_ring[priv->tx_new].status));
Marek Vasut5e2ad052020-04-19 04:00:49 +0200313 }
314
Marek Vasutf19db7f2020-07-08 07:01:32 +0200315 priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
wdenkc6097192002-11-03 00:24:07 +0000316}
317
Marek Vasut29b9efc2020-07-08 07:20:14 +0200318static int dc21x4x_send_common(struct dc2114x_priv *priv, void *packet, int length)
wdenkc6097192002-11-03 00:24:07 +0000319{
Marek Vasute3ffef32020-04-19 03:10:14 +0200320 int status = -1;
321 int i;
wdenkc6097192002-11-03 00:24:07 +0000322
323 if (length <= 0) {
Marek Vasut25ada1f2020-07-08 06:46:09 +0200324 printf("%s: bad packet size: %d\n", priv->name, length);
Marek Vasute3ffef32020-04-19 03:10:14 +0200325 goto done;
wdenkc6097192002-11-03 00:24:07 +0000326 }
327
Marek Vasutf19db7f2020-07-08 07:01:32 +0200328 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
Marek Vasute3ffef32020-04-19 03:10:14 +0200329 if (i < TOUT_LOOP)
330 continue;
331
Marek Vasut25ada1f2020-07-08 06:46:09 +0200332 printf("%s: tx error buffer not ready\n", priv->name);
Marek Vasute3ffef32020-04-19 03:10:14 +0200333 goto done;
wdenkc6097192002-11-03 00:24:07 +0000334 }
335
Marek Vasutf19db7f2020-07-08 07:01:32 +0200336 priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutb8e0b472020-07-08 06:50:41 +0200337 (u32)packet));
Marek Vasutf19db7f2020-07-08 07:01:32 +0200338 priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
339 priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
wdenkc6097192002-11-03 00:24:07 +0000340
Marek Vasut25ada1f2020-07-08 06:46:09 +0200341 dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
wdenkc6097192002-11-03 00:24:07 +0000342
Marek Vasutf19db7f2020-07-08 07:01:32 +0200343 for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
Marek Vasute3ffef32020-04-19 03:10:14 +0200344 if (i < TOUT_LOOP)
345 continue;
346
Marek Vasut25ada1f2020-07-08 06:46:09 +0200347 printf(".%s: tx buffer not ready\n", priv->name);
Marek Vasute3ffef32020-04-19 03:10:14 +0200348 goto done;
wdenkc6097192002-11-03 00:24:07 +0000349 }
350
Marek Vasutf19db7f2020-07-08 07:01:32 +0200351 if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) & TD_ES) {
352 priv->tx_ring[priv->tx_new].status = 0x0;
Marek Vasute3ffef32020-04-19 03:10:14 +0200353 goto done;
wdenkc6097192002-11-03 00:24:07 +0000354 }
355
356 status = length;
357
Marek Vasute3ffef32020-04-19 03:10:14 +0200358done:
Marek Vasutf19db7f2020-07-08 07:01:32 +0200359 priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
wdenkc6097192002-11-03 00:24:07 +0000360 return status;
361}
362
Marek Vasutdabf04f2020-07-08 07:12:58 +0200363static int dc21x4x_recv_check(struct dc2114x_priv *priv)
364{
365 int length = 0;
366 u32 status;
367
368 status = le32_to_cpu(priv->rx_ring[priv->rx_new].status);
369
370 if (status & R_OWN)
371 return 0;
372
373 if (status & RD_LS) {
374 /* Valid frame status. */
375 if (status & RD_ES) {
376 /* There was an error. */
377 printf("RX error status = 0x%08X\n", status);
378 return -EINVAL;
379 } else {
380 /* A valid frame received. */
381 length = (le32_to_cpu(priv->rx_ring[priv->rx_new].status)
382 >> 16);
383
384 return length;
385 }
386 }
387
388 return -EAGAIN;
389}
390
Marek Vasut29b9efc2020-07-08 07:20:14 +0200391static int dc21x4x_init_common(struct dc2114x_priv *priv)
wdenkc6097192002-11-03 00:24:07 +0000392{
Marek Vasut25ada1f2020-07-08 06:46:09 +0200393 int i;
wdenkc6097192002-11-03 00:24:07 +0000394
Marek Vasut25ada1f2020-07-08 06:46:09 +0200395 reset_de4x5(priv);
wdenkc6097192002-11-03 00:24:07 +0000396
Marek Vasut25ada1f2020-07-08 06:46:09 +0200397 if (dc2114x_inl(priv, DE4X5_STS) & (STS_TS | STS_RS)) {
Marek Vasut5e2ad052020-04-19 04:00:49 +0200398 printf("Error: Cannot reset ethernet controller.\n");
399 return -1;
400 }
wdenkc6097192002-11-03 00:24:07 +0000401
Marek Vasut25ada1f2020-07-08 06:46:09 +0200402 dc2114x_outl(priv, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
wdenkc6097192002-11-03 00:24:07 +0000403
Marek Vasut5e2ad052020-04-19 04:00:49 +0200404 for (i = 0; i < NUM_RX_DESC; i++) {
Marek Vasutf19db7f2020-07-08 07:01:32 +0200405 priv->rx_ring[i].status = cpu_to_le32(R_OWN);
406 priv->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
407 priv->rx_ring[i].buf = cpu_to_le32(phys_to_bus(priv->devno,
Marek Vasutb8e0b472020-07-08 06:50:41 +0200408 (u32)net_rx_packets[i]));
Marek Vasutf19db7f2020-07-08 07:01:32 +0200409 priv->rx_ring[i].next = 0;
wdenkc6097192002-11-03 00:24:07 +0000410 }
411
Marek Vasut5e2ad052020-04-19 04:00:49 +0200412 for (i = 0; i < NUM_TX_DESC; i++) {
Marek Vasutf19db7f2020-07-08 07:01:32 +0200413 priv->tx_ring[i].status = 0;
414 priv->tx_ring[i].des1 = 0;
415 priv->tx_ring[i].buf = 0;
416 priv->tx_ring[i].next = 0;
wdenkc6097192002-11-03 00:24:07 +0000417 }
418
Marek Vasutf19db7f2020-07-08 07:01:32 +0200419 priv->rx_ring_size = NUM_RX_DESC;
420 priv->tx_ring_size = NUM_TX_DESC;
wdenkc6097192002-11-03 00:24:07 +0000421
Marek Vasut5e2ad052020-04-19 04:00:49 +0200422 /* Write the end of list marker to the descriptor lists. */
Marek Vasutf19db7f2020-07-08 07:01:32 +0200423 priv->rx_ring[priv->rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
424 priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
wdenkc6097192002-11-03 00:24:07 +0000425
Marek Vasut5e2ad052020-04-19 04:00:49 +0200426 /* Tell the adapter where the TX/RX rings are located. */
Marek Vasutf19db7f2020-07-08 07:01:32 +0200427 dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->rx_ring),
Marek Vasutb8e0b472020-07-08 06:50:41 +0200428 DE4X5_RRBA);
Marek Vasutf19db7f2020-07-08 07:01:32 +0200429 dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->tx_ring),
Marek Vasutb8e0b472020-07-08 06:50:41 +0200430 DE4X5_TRBA);
Marek Vasute13635a2020-04-19 03:10:50 +0200431
Marek Vasut25ada1f2020-07-08 06:46:09 +0200432 start_de4x5(priv);
wdenkc6097192002-11-03 00:24:07 +0000433
Marek Vasutf19db7f2020-07-08 07:01:32 +0200434 priv->tx_new = 0;
435 priv->rx_new = 0;
wdenk0260cd62004-01-02 15:01:32 +0000436
Marek Vasut29b9efc2020-07-08 07:20:14 +0200437 send_setup_frame(priv);
wdenkc6097192002-11-03 00:24:07 +0000438
Marek Vasut5e2ad052020-04-19 04:00:49 +0200439 return 0;
wdenkc6097192002-11-03 00:24:07 +0000440}
441
Marek Vasut29b9efc2020-07-08 07:20:14 +0200442static void dc21x4x_halt_common(struct dc2114x_priv *priv)
wdenkc6097192002-11-03 00:24:07 +0000443{
Marek Vasut25ada1f2020-07-08 06:46:09 +0200444 stop_de4x5(priv);
445 dc2114x_outl(priv, 0, DE4X5_SICR);
wdenkc6097192002-11-03 00:24:07 +0000446}
447
Marek Vasuta3f89082020-07-08 06:42:07 +0200448static void read_hw_addr(struct dc2114x_priv *priv)
wdenkc6097192002-11-03 00:24:07 +0000449{
Marek Vasuta3f89082020-07-08 06:42:07 +0200450 u_short tmp, *p = (u_short *)(&priv->enetaddr[0]);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200451 int i, j = 0;
Marek Vasutb46c7a02020-04-19 03:11:06 +0200452
Marek Vasut5e2ad052020-04-19 04:00:49 +0200453 for (i = 0; i < (ETH_ALEN >> 1); i++) {
Marek Vasut25ada1f2020-07-08 06:46:09 +0200454 tmp = read_srom(priv, DE4X5_APROM, (SROM_HWADD >> 1) + i);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200455 *p = le16_to_cpu(tmp);
456 j += *p++;
wdenkc6097192002-11-03 00:24:07 +0000457 }
458
Marek Vasut5e2ad052020-04-19 04:00:49 +0200459 if (!j || j == 0x2fffd) {
Marek Vasuta3f89082020-07-08 06:42:07 +0200460 memset(priv->enetaddr, 0, ETH_ALEN);
Marek Vasut5e2ad052020-04-19 04:00:49 +0200461 debug("Warning: can't read HW address from SROM.\n");
wdenkc6097192002-11-03 00:24:07 +0000462 }
wdenkc6097192002-11-03 00:24:07 +0000463}
464
Marek Vasut5e2ad052020-04-19 04:00:49 +0200465static struct pci_device_id supported[] = {
Marek Vasut7cc35c82020-06-20 17:36:42 +0200466 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST) },
467 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142) },
Marek Vasut5e2ad052020-04-19 04:00:49 +0200468 { }
469};
wdenkc6097192002-11-03 00:24:07 +0000470
Marek Vasut1d6c7382020-07-08 07:26:14 +0200471static int dc2114x_start(struct udevice *dev)
472{
Simon Glassfa20e932020-12-03 16:55:20 -0700473 struct eth_pdata *plat = dev_get_plat(dev);
Marek Vasut1d6c7382020-07-08 07:26:14 +0200474 struct dc2114x_priv *priv = dev_get_priv(dev);
475
476 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
477
478 /* Ensure we're not sleeping. */
479 dm_pci_write_config8(dev, PCI_CFDA_PSM, WAKEUP);
480
481 return dc21x4x_init_common(priv);
482}
483
484static void dc2114x_stop(struct udevice *dev)
485{
486 struct dc2114x_priv *priv = dev_get_priv(dev);
487
488 dc21x4x_halt_common(priv);
489
490 dm_pci_write_config8(dev, PCI_CFDA_PSM, SLEEP);
491}
492
493static int dc2114x_send(struct udevice *dev, void *packet, int length)
494{
495 struct dc2114x_priv *priv = dev_get_priv(dev);
496 int ret;
497
498 ret = dc21x4x_send_common(priv, packet, length);
499
500 return ret ? 0 : -ETIMEDOUT;
501}
502
503static int dc2114x_recv(struct udevice *dev, int flags, uchar **packetp)
504{
505 struct dc2114x_priv *priv = dev_get_priv(dev);
506 int ret;
507
508 ret = dc21x4x_recv_check(priv);
509
510 if (ret < 0) {
511 /* Update entry information. */
512 priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
513 ret = 0;
514 }
515
516 if (!ret)
517 return 0;
518
519 *packetp = net_rx_packets[priv->rx_new];
520
521 return ret - 4;
522}
523
524static int dc2114x_free_pkt(struct udevice *dev, uchar *packet, int length)
525{
526 struct dc2114x_priv *priv = dev_get_priv(dev);
527
528 priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
529
530 /* Update entry information. */
531 priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
532
533 return 0;
534}
535
536static int dc2114x_read_rom_hwaddr(struct udevice *dev)
537{
538 struct dc2114x_priv *priv = dev_get_priv(dev);
539
540 read_hw_addr(priv);
541
542 return 0;
543}
544
545static int dc2114x_bind(struct udevice *dev)
546{
547 static int card_number;
548 char name[16];
549
550 sprintf(name, "dc2114x#%u", card_number++);
551
552 return device_set_name(dev, name);
553}
554
555static int dc2114x_probe(struct udevice *dev)
556{
Simon Glassfa20e932020-12-03 16:55:20 -0700557 struct eth_pdata *plat = dev_get_plat(dev);
Marek Vasut1d6c7382020-07-08 07:26:14 +0200558 struct dc2114x_priv *priv = dev_get_priv(dev);
559 u16 command, status;
560 u32 iobase;
561
562 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
563 iobase &= ~0xf;
564
565 debug("dc2114x: DEC 2114x PCI Device @0x%x\n", iobase);
566
567 priv->devno = dev;
568 priv->enetaddr = plat->enetaddr;
569 priv->iobase = (void __iomem *)dm_pci_mem_to_phys(dev, iobase);
570
571 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
572 dm_pci_write_config16(dev, PCI_COMMAND, command);
573 dm_pci_read_config16(dev, PCI_COMMAND, &status);
574 if ((status & command) != command) {
575 printf("dc2114x: Couldn't enable IO access or Bus Mastering\n");
576 return -EINVAL;
577 }
578
579 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x60);
580
581 return 0;
582}
583
584static const struct eth_ops dc2114x_ops = {
585 .start = dc2114x_start,
586 .send = dc2114x_send,
587 .recv = dc2114x_recv,
588 .stop = dc2114x_stop,
589 .free_pkt = dc2114x_free_pkt,
590 .read_rom_hwaddr = dc2114x_read_rom_hwaddr,
591};
592
593U_BOOT_DRIVER(eth_dc2114x) = {
594 .name = "eth_dc2114x",
595 .id = UCLASS_ETH,
596 .bind = dc2114x_bind,
597 .probe = dc2114x_probe,
598 .ops = &dc2114x_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700599 .priv_auto = sizeof(struct dc2114x_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -0700600 .plat_auto = sizeof(struct eth_pdata),
Marek Vasut1d6c7382020-07-08 07:26:14 +0200601};
602
603U_BOOT_PCI_DEVICE(eth_dc2114x, supported);