Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015, Freescale Semiconductor |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ |
| 8 | #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ |
| 9 | |
York Sun | bad4984 | 2016-09-26 08:09:24 -0700 | [diff] [blame] | 10 | #include <linux/kconfig.h> |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 11 | #include <fsl_ddrc_version.h> |
| 12 | |
Shaohui Xie | 6759cc2 | 2016-09-07 17:56:09 +0800 | [diff] [blame] | 13 | #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 |
| 14 | |
York Sun | 0804d56 | 2015-12-04 11:57:08 -0800 | [diff] [blame] | 15 | /* |
| 16 | * Reserve secure memory |
| 17 | * To be aligned with MMU block size |
| 18 | */ |
| 19 | #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ |
| 20 | |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 21 | #ifdef CONFIG_LS2080A |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 22 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } |
| 23 | #define SRDS_MAX_LANES 8 |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 24 | #define CONFIG_SYS_PAGE_SIZE 0x10000 |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 25 | #ifndef L1_CACHE_BYTES |
| 26 | #define L1_CACHE_SHIFT 6 |
| 27 | #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) |
Priyanka Jain | 4a6f173 | 2016-11-17 12:29:55 +0530 | [diff] [blame] | 28 | #define CONFIG_FSL_TZASC_400 |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 29 | #endif |
| 30 | |
| 31 | #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ |
| 32 | #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ |
| 33 | |
| 34 | /* DDR */ |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 35 | #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 36 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE |
| 37 | |
| 38 | #define CONFIG_SYS_FSL_CCSR_GUR_LE |
| 39 | #define CONFIG_SYS_FSL_CCSR_SCFG_LE |
| 40 | #define CONFIG_SYS_FSL_ESDHC_LE |
| 41 | #define CONFIG_SYS_FSL_IFC_LE |
Mingkai Hu | 1921899 | 2015-11-11 17:58:34 +0800 | [diff] [blame] | 42 | #define CONFIG_SYS_FSL_PEX_LUT_LE |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 43 | |
| 44 | #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN |
| 45 | |
| 46 | /* Generic Interrupt Controller Definitions */ |
| 47 | #define GICD_BASE 0x06000000 |
| 48 | #define GICR_BASE 0x06100000 |
| 49 | |
| 50 | /* SMMU Defintions */ |
| 51 | #define SMMU_BASE 0x05000000 /* GR0 Base */ |
| 52 | |
Saksham Jain | 62888be | 2016-03-23 16:24:32 +0530 | [diff] [blame] | 53 | /* SFP */ |
| 54 | #define CONFIG_SYS_FSL_SFP_VER_3_4 |
| 55 | #define CONFIG_SYS_FSL_SFP_LE |
Saksham Jain | 6ae7f58 | 2016-03-23 16:24:33 +0530 | [diff] [blame] | 56 | #define CONFIG_SYS_FSL_SRK_LE |
| 57 | |
Saksham Jain | 6ae7f58 | 2016-03-23 16:24:33 +0530 | [diff] [blame] | 58 | /* Security Monitor */ |
| 59 | #define CONFIG_SYS_FSL_SEC_MON_LE |
| 60 | |
Saksham Jain | 6121f08 | 2016-03-23 16:24:34 +0530 | [diff] [blame] | 61 | /* Secure Boot */ |
| 62 | #define CONFIG_ESBC_HDR_LS |
Saksham Jain | 62888be | 2016-03-23 16:24:32 +0530 | [diff] [blame] | 63 | |
Saksham Jain | 7b0b250 | 2016-03-23 16:24:39 +0530 | [diff] [blame] | 64 | /* DCFG - GUR */ |
| 65 | #define CONFIG_SYS_FSL_CCSR_GUR_LE |
| 66 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 67 | /* Cache Coherent Interconnect */ |
| 68 | #define CCI_MN_BASE 0x04000000 |
| 69 | #define CCI_MN_RNF_NODEID_LIST 0x180 |
| 70 | #define CCI_MN_DVM_DOMAIN_CTL 0x200 |
| 71 | #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 |
| 72 | |
York Sun | d957a67 | 2015-11-04 09:53:10 -0800 | [diff] [blame] | 73 | #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) |
| 74 | #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) |
| 75 | #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ |
| 76 | #define CCN_HN_F_SAM_NODEID_MASK 0x7f |
| 77 | #define CCN_HN_F_SAM_NODEID_DDR0 0x4 |
| 78 | #define CCN_HN_F_SAM_NODEID_DDR1 0xe |
| 79 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 80 | #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) |
| 81 | #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) |
| 82 | #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) |
| 83 | #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) |
| 84 | #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) |
| 85 | #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) |
| 86 | |
| 87 | #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) |
| 88 | #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) |
| 89 | #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) |
| 90 | |
Prabhakar Kushwaha | edbbd25 | 2016-01-25 12:08:45 +0530 | [diff] [blame] | 91 | #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) |
| 92 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 93 | /* TZ Protection Controller Definitions */ |
| 94 | #define TZPC_BASE 0x02200000 |
| 95 | #define TZPCR0SIZE_BASE (TZPC_BASE) |
| 96 | #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) |
| 97 | #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) |
| 98 | #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) |
| 99 | #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) |
| 100 | #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) |
| 101 | #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) |
| 102 | #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) |
| 103 | #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) |
| 104 | #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) |
| 105 | |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 106 | #define DCSR_CGACRE5 0x700070914ULL |
| 107 | #define EPU_EPCMPR5 0x700060914ULL |
| 108 | #define EPU_EPCCR5 0x700060814ULL |
| 109 | #define EPU_EPSMCR5 0x700060228ULL |
| 110 | #define EPU_EPECR5 0x700060314ULL |
| 111 | #define EPU_EPCTR5 0x700060a14ULL |
| 112 | #define EPU_EPGCR 0x700060000ULL |
| 113 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 114 | #define CONFIG_SYS_FSL_ERRATUM_A008336 |
| 115 | #define CONFIG_SYS_FSL_ERRATUM_A008511 |
| 116 | #define CONFIG_SYS_FSL_ERRATUM_A008514 |
| 117 | #define CONFIG_SYS_FSL_ERRATUM_A008585 |
| 118 | #define CONFIG_SYS_FSL_ERRATUM_A008751 |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 119 | #define CONFIG_SYS_FSL_ERRATUM_A009635 |
Shengzhou Liu | bdda96c | 2015-12-16 16:45:41 +0800 | [diff] [blame] | 120 | #define CONFIG_SYS_FSL_ERRATUM_A009663 |
Shengzhou Liu | 9c3cdc2 | 2016-03-16 13:50:23 +0800 | [diff] [blame] | 121 | #define CONFIG_SYS_FSL_ERRATUM_A009801 |
Shengzhou Liu | b03e1b1 | 2016-03-10 17:36:57 +0800 | [diff] [blame] | 122 | #define CONFIG_SYS_FSL_ERRATUM_A009803 |
Shengzhou Liu | fa2e2fb | 2016-01-06 11:26:51 +0800 | [diff] [blame] | 123 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
Shengzhou Liu | c72d12e | 2016-05-10 16:03:47 +0800 | [diff] [blame] | 124 | #define CONFIG_SYS_FSL_ERRATUM_A010165 |
Shengzhou Liu | bdda96c | 2015-12-16 16:45:41 +0800 | [diff] [blame] | 125 | |
Ashish kumar | 9c6d33c | 2016-01-27 18:09:32 +0530 | [diff] [blame] | 126 | /* ARM A57 CORE ERRATA */ |
Ashish kumar | b01bbb7 | 2016-01-29 16:40:08 +0530 | [diff] [blame] | 127 | #define CONFIG_ARM_ERRATA_826974 |
| 128 | #define CONFIG_ARM_ERRATA_828024 |
Ashish kumar | 9c6d33c | 2016-01-27 18:09:32 +0530 | [diff] [blame] | 129 | #define CONFIG_ARM_ERRATA_829520 |
| 130 | #define CONFIG_ARM_ERRATA_833471 |
| 131 | |
Alex Porosanu | b4848d0 | 2016-04-29 15:17:59 +0300 | [diff] [blame] | 132 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 133 | #elif defined(CONFIG_FSL_LSCH2) |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 134 | #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 135 | #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 136 | |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 137 | #define CONFIG_SYS_FSL_CCSR_SCFG_BE |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 138 | #define CONFIG_SYS_FSL_ESDHC_BE |
| 139 | #define CONFIG_SYS_FSL_WDOG_BE |
| 140 | #define CONFIG_SYS_FSL_DSPI_BE |
| 141 | #define CONFIG_SYS_FSL_QSPI_BE |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 142 | #define CONFIG_SYS_FSL_CCSR_GUR_BE |
Mingkai Hu | 1921899 | 2015-11-11 17:58:34 +0800 | [diff] [blame] | 143 | #define CONFIG_SYS_FSL_PEX_LUT_BE |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 144 | |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 145 | /* SoC related */ |
| 146 | #ifdef CONFIG_LS1043A |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 147 | #define CONFIG_SYS_FMAN_V3 |
| 148 | #define CONFIG_SYS_NUM_FMAN 1 |
| 149 | #define CONFIG_SYS_NUM_FM1_DTSEC 7 |
| 150 | #define CONFIG_SYS_NUM_FM1_10GEC 1 |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 151 | #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 152 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 153 | |
| 154 | #define QE_MURAM_SIZE 0x6000UL |
| 155 | #define MAX_QE_RISC 1 |
| 156 | #define QE_NUM_OF_SNUM 28 |
| 157 | |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 158 | #define CONFIG_SYS_FSL_IFC_BE |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 159 | #define CONFIG_SYS_FSL_SFP_VER_3_2 |
Aneesh Bansal | b3e9820 | 2015-12-08 13:54:29 +0530 | [diff] [blame] | 160 | #define CONFIG_SYS_FSL_SEC_MON_BE |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 161 | #define CONFIG_SYS_FSL_SFP_BE |
| 162 | #define CONFIG_SYS_FSL_SRK_LE |
| 163 | #define CONFIG_KEY_REVOCATION |
| 164 | |
| 165 | /* SMMU Defintions */ |
| 166 | #define SMMU_BASE 0x09000000 |
| 167 | |
| 168 | /* Generic Interrupt Controller Definitions */ |
| 169 | #define GICD_BASE 0x01401000 |
| 170 | #define GICC_BASE 0x01402000 |
| 171 | |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 172 | #define CONFIG_SYS_FSL_ERRATUM_A008850 |
Shengzhou Liu | bdda96c | 2015-12-16 16:45:41 +0800 | [diff] [blame] | 173 | #define CONFIG_SYS_FSL_ERRATUM_A009663 |
Mingkai Hu | 8beb075 | 2015-12-07 16:58:54 +0800 | [diff] [blame] | 174 | #define CONFIG_SYS_FSL_ERRATUM_A009929 |
Shengzhou Liu | 3ed72eb | 2016-01-29 16:56:01 +0800 | [diff] [blame] | 175 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
Mingkai Hu | 172081c | 2016-02-02 11:28:03 +0800 | [diff] [blame] | 176 | #define CONFIG_SYS_FSL_ERRATUM_A009660 |
Alex Porosanu | b4848d0 | 2016-04-29 15:17:59 +0300 | [diff] [blame] | 177 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 178 | #elif defined(CONFIG_ARCH_LS1012A) |
Prabhakar Kushwaha | d169ebe | 2016-06-03 18:41:31 +0530 | [diff] [blame] | 179 | #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 |
| 180 | |
Prabhakar Kushwaha | d169ebe | 2016-06-03 18:41:31 +0530 | [diff] [blame] | 181 | #define GICD_BASE 0x01401000 |
| 182 | #define GICC_BASE 0x01402000 |
York Sun | bad4984 | 2016-09-26 08:09:24 -0700 | [diff] [blame] | 183 | #elif defined(CONFIG_ARCH_LS1046A) |
Mingkai Hu | cd54c0f | 2016-07-05 16:01:55 +0800 | [diff] [blame] | 184 | #define CONFIG_SYS_FMAN_V3 |
| 185 | #define CONFIG_SYS_NUM_FMAN 1 |
| 186 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 |
| 187 | #define CONFIG_SYS_NUM_FM1_10GEC 2 |
Mingkai Hu | cd54c0f | 2016-07-05 16:01:55 +0800 | [diff] [blame] | 188 | #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 189 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE |
| 190 | |
Mingkai Hu | cd54c0f | 2016-07-05 16:01:55 +0800 | [diff] [blame] | 191 | #define CONFIG_SYS_FSL_IFC_BE |
| 192 | #define CONFIG_SYS_FSL_SFP_VER_3_2 |
| 193 | #define CONFIG_SYS_FSL_SNVS_LE |
| 194 | #define CONFIG_SYS_FSL_SFP_BE |
| 195 | #define CONFIG_SYS_FSL_SRK_LE |
| 196 | #define CONFIG_KEY_REVOCATION |
| 197 | |
| 198 | /* SMMU Defintions */ |
| 199 | #define SMMU_BASE 0x09000000 |
| 200 | |
| 201 | /* Generic Interrupt Controller Definitions */ |
| 202 | #define GICD_BASE 0x01410000 |
| 203 | #define GICC_BASE 0x01420000 |
| 204 | |
| 205 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |
Shengzhou Liu | 4fd4e1d | 2016-09-07 17:56:11 +0800 | [diff] [blame] | 206 | |
| 207 | #define CONFIG_SYS_FSL_ERRATUM_A008511 |
| 208 | #define CONFIG_SYS_FSL_ERRATUM_A009801 |
| 209 | #define CONFIG_SYS_FSL_ERRATUM_A009803 |
| 210 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
| 211 | #define CONFIG_SYS_FSL_ERRATUM_A010165 |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 212 | #else |
| 213 | #error SoC not defined |
| 214 | #endif |
Qianyu Gong | 8aec719 | 2016-07-05 16:01:53 +0800 | [diff] [blame] | 215 | #endif |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 216 | |
| 217 | #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ |