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Mingkai Hu0e58b512015-10-26 19:47:50 +08001/*
2 * Copyright 2015, Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
9
York Sunbad49842016-09-26 08:09:24 -070010#include <linux/kconfig.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080011#include <fsl_ddrc_version.h>
12
Shaohui Xie6759cc22016-09-07 17:56:09 +080013#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
14
Mingkai Hu0e58b512015-10-26 19:47:50 +080015#ifdef CONFIG_SYS_FSL_DDR4
16#define CONFIG_SYS_FSL_DDRC_GEN4
17#else
18#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
19#endif
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +053020
York Sunb3d71642016-09-26 08:09:26 -070021#ifndef CONFIG_ARCH_LS1012A
Mingkai Hu0e58b512015-10-26 19:47:50 +080022#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
23#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +053024#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +080025
York Sun0804d562015-12-04 11:57:08 -080026/*
27 * Reserve secure memory
28 * To be aligned with MMU block size
29 */
30#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
31
York Suncbe8e1c2016-04-04 11:41:26 -070032#ifdef CONFIG_LS2080A
Mingkai Hu0e58b512015-10-26 19:47:50 +080033#define CONFIG_MAX_CPUS 16
34#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
Prabhakar Kushwaha77f7ded2015-11-09 16:42:20 +053035#define CONFIG_NUM_DDR_CONTROLLERS 3
York Suncbe8e1c2016-04-04 11:41:26 -070036#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
Mingkai Hu0e58b512015-10-26 19:47:50 +080037#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
38#define SRDS_MAX_LANES 8
39#define CONFIG_SYS_FSL_SRDS_1
40#define CONFIG_SYS_FSL_SRDS_2
41#define CONFIG_SYS_PAGE_SIZE 0x10000
Mingkai Hu0e58b512015-10-26 19:47:50 +080042#ifndef L1_CACHE_BYTES
43#define L1_CACHE_SHIFT 6
44#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
45#endif
46
47#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
48#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
49
50/* DDR */
51#define CONFIG_SYS_FSL_DDR_LE
52#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
53#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
54
55#define CONFIG_SYS_FSL_CCSR_GUR_LE
56#define CONFIG_SYS_FSL_CCSR_SCFG_LE
57#define CONFIG_SYS_FSL_ESDHC_LE
58#define CONFIG_SYS_FSL_IFC_LE
Mingkai Hu19218992015-11-11 17:58:34 +080059#define CONFIG_SYS_FSL_PEX_LUT_LE
Mingkai Hu0e58b512015-10-26 19:47:50 +080060
61#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
62
63/* Generic Interrupt Controller Definitions */
64#define GICD_BASE 0x06000000
65#define GICR_BASE 0x06100000
66
67/* SMMU Defintions */
68#define SMMU_BASE 0x05000000 /* GR0 Base */
69
Saksham Jain62888be2016-03-23 16:24:32 +053070/* SFP */
71#define CONFIG_SYS_FSL_SFP_VER_3_4
72#define CONFIG_SYS_FSL_SFP_LE
Saksham Jain6ae7f582016-03-23 16:24:33 +053073#define CONFIG_SYS_FSL_SRK_LE
74
75/* SEC */
76#define CONFIG_SYS_FSL_SEC_LE
77#define CONFIG_SYS_FSL_SEC_COMPAT 5
78
79/* Security Monitor */
80#define CONFIG_SYS_FSL_SEC_MON_LE
81
Saksham Jain6121f082016-03-23 16:24:34 +053082/* Secure Boot */
83#define CONFIG_ESBC_HDR_LS
Saksham Jain62888be2016-03-23 16:24:32 +053084
Saksham Jain7b0b2502016-03-23 16:24:39 +053085/* DCFG - GUR */
86#define CONFIG_SYS_FSL_CCSR_GUR_LE
87
Mingkai Hu0e58b512015-10-26 19:47:50 +080088/* Cache Coherent Interconnect */
89#define CCI_MN_BASE 0x04000000
90#define CCI_MN_RNF_NODEID_LIST 0x180
91#define CCI_MN_DVM_DOMAIN_CTL 0x200
92#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
93
York Sund957a672015-11-04 09:53:10 -080094#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
95#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
96#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
97#define CCN_HN_F_SAM_NODEID_MASK 0x7f
98#define CCN_HN_F_SAM_NODEID_DDR0 0x4
99#define CCN_HN_F_SAM_NODEID_DDR1 0xe
100
Mingkai Hu0e58b512015-10-26 19:47:50 +0800101#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
102#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
103#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
104#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
105#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
106#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
107
108#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
109#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
110#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
111
Prabhakar Kushwahaedbbd252016-01-25 12:08:45 +0530112#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
113
Mingkai Hu0e58b512015-10-26 19:47:50 +0800114/* TZ Protection Controller Definitions */
115#define TZPC_BASE 0x02200000
116#define TZPCR0SIZE_BASE (TZPC_BASE)
117#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
118#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
119#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
120#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
121#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
122#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
123#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
124#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
125#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
126
Prabhakar Kushwaha22cfe962015-11-05 12:00:14 +0530127#define DCSR_CGACRE5 0x700070914ULL
128#define EPU_EPCMPR5 0x700060914ULL
129#define EPU_EPCCR5 0x700060814ULL
130#define EPU_EPSMCR5 0x700060228ULL
131#define EPU_EPECR5 0x700060314ULL
132#define EPU_EPCTR5 0x700060a14ULL
133#define EPU_EPGCR 0x700060000ULL
134
Mingkai Hu0e58b512015-10-26 19:47:50 +0800135#define CONFIG_SYS_FSL_ERRATUM_A008336
136#define CONFIG_SYS_FSL_ERRATUM_A008511
137#define CONFIG_SYS_FSL_ERRATUM_A008514
138#define CONFIG_SYS_FSL_ERRATUM_A008585
139#define CONFIG_SYS_FSL_ERRATUM_A008751
Prabhakar Kushwaha22cfe962015-11-05 12:00:14 +0530140#define CONFIG_SYS_FSL_ERRATUM_A009635
Shengzhou Liubdda96c2015-12-16 16:45:41 +0800141#define CONFIG_SYS_FSL_ERRATUM_A009663
Shengzhou Liu9c3cdc22016-03-16 13:50:23 +0800142#define CONFIG_SYS_FSL_ERRATUM_A009801
Shengzhou Liub03e1b12016-03-10 17:36:57 +0800143#define CONFIG_SYS_FSL_ERRATUM_A009803
Shengzhou Liufa2e2fb2016-01-06 11:26:51 +0800144#define CONFIG_SYS_FSL_ERRATUM_A009942
Shengzhou Liuc72d12e2016-05-10 16:03:47 +0800145#define CONFIG_SYS_FSL_ERRATUM_A010165
Shengzhou Liubdda96c2015-12-16 16:45:41 +0800146
Ashish kumar9c6d33c2016-01-27 18:09:32 +0530147/* ARM A57 CORE ERRATA */
Ashish kumarb01bbb72016-01-29 16:40:08 +0530148#define CONFIG_ARM_ERRATA_826974
149#define CONFIG_ARM_ERRATA_828024
Ashish kumar9c6d33c2016-01-27 18:09:32 +0530150#define CONFIG_ARM_ERRATA_829520
151#define CONFIG_ARM_ERRATA_833471
152
Alex Porosanub4848d02016-04-29 15:17:59 +0300153#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
Qianyu Gong8aec7192016-07-05 16:01:53 +0800154#elif defined(CONFIG_FSL_LSCH2)
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800155#define CONFIG_NUM_DDR_CONTROLLERS 1
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800156#define CONFIG_SYS_FSL_SEC_COMPAT 5
157#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
Qianyu Gong8aec7192016-07-05 16:01:53 +0800158#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
159#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800160
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800161#define CONFIG_SYS_FSL_CCSR_SCFG_BE
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800162#define CONFIG_SYS_FSL_ESDHC_BE
163#define CONFIG_SYS_FSL_WDOG_BE
164#define CONFIG_SYS_FSL_DSPI_BE
165#define CONFIG_SYS_FSL_QSPI_BE
Qianyu Gong8aec7192016-07-05 16:01:53 +0800166#define CONFIG_SYS_FSL_CCSR_GUR_BE
Mingkai Hu19218992015-11-11 17:58:34 +0800167#define CONFIG_SYS_FSL_PEX_LUT_BE
Qianyu Gong8aec7192016-07-05 16:01:53 +0800168#define CONFIG_SYS_FSL_SEC_BE
169
170#define CONFIG_SYS_FSL_SRDS_1
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +0800171
172#define CONFIG_SYS_FSL_ERRATUM_A010315
Qianyu Gong8aec7192016-07-05 16:01:53 +0800173/* SoC related */
174#ifdef CONFIG_LS1043A
175#define CONFIG_MAX_CPUS 4
176#define CONFIG_SYS_FMAN_V3
177#define CONFIG_SYS_NUM_FMAN 1
178#define CONFIG_SYS_NUM_FM1_DTSEC 7
179#define CONFIG_SYS_NUM_FM1_10GEC 1
180#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
181#define CONFIG_SYS_FSL_DDR_BE
182#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
183#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800184
185#define QE_MURAM_SIZE 0x6000UL
186#define MAX_QE_RISC 1
187#define QE_NUM_OF_SNUM 28
188
Qianyu Gong8aec7192016-07-05 16:01:53 +0800189#define CONFIG_SYS_FSL_IFC_BE
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800190#define CONFIG_SYS_FSL_SFP_VER_3_2
Aneesh Bansalb3e98202015-12-08 13:54:29 +0530191#define CONFIG_SYS_FSL_SEC_MON_BE
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800192#define CONFIG_SYS_FSL_SFP_BE
193#define CONFIG_SYS_FSL_SRK_LE
194#define CONFIG_KEY_REVOCATION
195
196/* SMMU Defintions */
197#define SMMU_BASE 0x09000000
198
199/* Generic Interrupt Controller Definitions */
200#define GICD_BASE 0x01401000
201#define GICC_BASE 0x01402000
202
Shengzhou Liuddf060b2016-04-07 16:22:21 +0800203#define CONFIG_SYS_FSL_ERRATUM_A008850
Shengzhou Liubdda96c2015-12-16 16:45:41 +0800204#define CONFIG_SYS_FSL_ERRATUM_A009663
Mingkai Hu8beb0752015-12-07 16:58:54 +0800205#define CONFIG_SYS_FSL_ERRATUM_A009929
Shengzhou Liu3ed72eb2016-01-29 16:56:01 +0800206#define CONFIG_SYS_FSL_ERRATUM_A009942
Mingkai Hu172081c2016-02-02 11:28:03 +0800207#define CONFIG_SYS_FSL_ERRATUM_A009660
Alex Porosanub4848d02016-04-29 15:17:59 +0300208#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
York Sunb3d71642016-09-26 08:09:26 -0700209#elif defined(CONFIG_ARCH_LS1012A)
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +0530210#define CONFIG_MAX_CPUS 1
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +0530211#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
212
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +0530213#define GICD_BASE 0x01401000
214#define GICC_BASE 0x01402000
York Sunbad49842016-09-26 08:09:24 -0700215#elif defined(CONFIG_ARCH_LS1046A)
Mingkai Hucd54c0f2016-07-05 16:01:55 +0800216#define CONFIG_MAX_CPUS 4
217#define CONFIG_SYS_FMAN_V3
218#define CONFIG_SYS_NUM_FMAN 1
219#define CONFIG_SYS_NUM_FM1_DTSEC 8
220#define CONFIG_SYS_NUM_FM1_10GEC 2
221#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
222#define CONFIG_SYS_FSL_DDR_BE
223#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
224#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
225
226#define CONFIG_SYS_FSL_SRDS_2
227#define CONFIG_SYS_FSL_IFC_BE
228#define CONFIG_SYS_FSL_SFP_VER_3_2
229#define CONFIG_SYS_FSL_SNVS_LE
230#define CONFIG_SYS_FSL_SFP_BE
231#define CONFIG_SYS_FSL_SRK_LE
232#define CONFIG_KEY_REVOCATION
233
234/* SMMU Defintions */
235#define SMMU_BASE 0x09000000
236
237/* Generic Interrupt Controller Definitions */
238#define GICD_BASE 0x01410000
239#define GICC_BASE 0x01420000
240
241#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
Shengzhou Liu4fd4e1d2016-09-07 17:56:11 +0800242
243#define CONFIG_SYS_FSL_ERRATUM_A008511
244#define CONFIG_SYS_FSL_ERRATUM_A009801
245#define CONFIG_SYS_FSL_ERRATUM_A009803
246#define CONFIG_SYS_FSL_ERRATUM_A009942
247#define CONFIG_SYS_FSL_ERRATUM_A010165
Mingkai Hu0e58b512015-10-26 19:47:50 +0800248#else
249#error SoC not defined
250#endif
Qianyu Gong8aec7192016-07-05 16:01:53 +0800251#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800252
253#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */