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Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbò i Serraed116482013-12-06 21:30:24 +010013#define CONFIG_NR_DRAM_BANKS 2
Ladislav Michl43a60622016-07-12 20:28:32 +020014#define CONFIG_NAND
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040015
Enric Balletbò i Serraed116482013-12-06 21:30:24 +010016#include <configs/ti_omap3_common.h>
Enric Balletbo i Serra74fea922013-02-07 00:40:05 +000017#include <asm/mach-types.h>
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040018
Tom Rinicfff4aa2016-08-26 13:30:43 -040019/*
20 * We are only ever GP parts and will utilize all of the "downloaded image"
21 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
22 */
Enric Balletbo i Serra8aa10d42016-05-03 08:59:24 +020023#undef CONFIG_SPL_TEXT_BASE
Enric Balletbo i Serra8aa10d42016-05-03 08:59:24 +020024#define CONFIG_SPL_TEXT_BASE 0x40200000
25
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040026/*
27 * Display CPU and Board information
28 */
29#define CONFIG_DISPLAY_CPUINFO 1
30#define CONFIG_DISPLAY_BOARDINFO 1
31
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040032#define CONFIG_MISC_INIT_R
33
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040034#define CONFIG_REVISION_TAG 1
35
Enric Balletbo i Serra3bb41cc2015-02-24 19:27:15 +010036/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
37#if (CONFIG_MACH_TYPE != MACH_TYPE_IGEP0032)
Enric Balletbo i Serraa66c8872015-01-28 15:01:32 +010038#define CONFIG_STATUS_LED
39#define CONFIG_BOARD_SPECIFIC_LED
40#define CONFIG_GPIO_LED
41#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
42#define RED_LED_GPIO 27
Enric Balletbo i Serra3bb41cc2015-02-24 19:27:15 +010043#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
Enric Balletbo i Serraa66c8872015-01-28 15:01:32 +010044#define RED_LED_GPIO 16
Enric Balletbo i Serra3bb41cc2015-02-24 19:27:15 +010045#else
46#error "status LED not defined for this machine."
Enric Balletbo i Serra02043a72013-02-07 00:40:06 +000047#endif
Ladislav Michl06c1cd02016-01-04 23:08:01 +010048#define RED_LED_DEV 0
Enric Balletbo i Serraa66c8872015-01-28 15:01:32 +010049#define STATUS_LED_BIT RED_LED_GPIO
50#define STATUS_LED_STATE STATUS_LED_ON
51#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
52#define STATUS_LED_BOOT RED_LED_DEV
Enric Balletbo i Serra3bb41cc2015-02-24 19:27:15 +010053#endif
Javier Martinez Canillasd549ace2012-12-27 03:36:01 +000054
Enric Balletbo i Serra12fcb8c2014-01-25 22:52:22 +010055/* GPIO banks */
56#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */
57#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
58#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
59
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040060/* USB */
Ladislav Michl06c1cd02016-01-04 23:08:01 +010061#define CONFIG_USB_MUSB_UDC 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040062#define CONFIG_USB_OMAP3 1
63#define CONFIG_TWL4030_USB 1
64
65/* USB device configuration */
66#define CONFIG_USB_DEVICE 1
67#define CONFIG_USB_TTY 1
68#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
69
70/* Change these to suit your needs */
71#define CONFIG_USBD_VENDORID 0x0451
72#define CONFIG_USBD_PRODUCTID 0x5678
73#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
74#define CONFIG_USBD_PRODUCT_NAME "IGEP"
75
Ladislav Michl43a60622016-07-12 20:28:32 +020076#define CONFIG_CMD_MTDPARTS
77#define CONFIG_CMD_ONENAND
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040078
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020079#ifndef CONFIG_SPL_BUILD
80
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020081/* Environment */
82#define ENV_DEVICE_SETTINGS \
83 "stdin=serial\0" \
84 "stdout=serial\0" \
85 "stderr=serial\0"
86
87#define MEM_LAYOUT_SETTINGS \
88 DEFAULT_LINUX_BOOT_ENV \
89 "scriptaddr=0x87E00000\0" \
90 "pxefile_addr_r=0x87F00000\0"
91
92#define BOOT_TARGET_DEVICES(func) \
93 func(MMC, mmc, 0)
94
95#include <config_distro_bootcmd.h>
96
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040097#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020098 ENV_DEVICE_SETTINGS \
99 MEM_LAYOUT_SETTINGS \
100 BOOTENV
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400101
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +0200102#endif
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400103
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400104/*
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400105 * SMSC911x Ethernet
106 */
107#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400108#define CONFIG_SMC911X
109#define CONFIG_SMC911X_32_BIT
Ladislav Michl06c1cd02016-01-04 23:08:01 +0100110#define CONFIG_SMC911X_BASE 0x2C000000
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400111#endif /* (CONFIG_CMD_NET) */
112
Ladislav Michl43a60622016-07-12 20:28:32 +0200113#define CONFIG_RBTREE
114#define CONFIG_MTD_PARTITIONS
Ladislav Michlc44e29f2016-07-12 20:28:33 +0200115#define CONFIG_SYS_MTDPARTS_RUNTIME
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000116
Ladislav Michl43a60622016-07-12 20:28:32 +0200117/* OneNAND config */
Ladislav Michl43a60622016-07-12 20:28:32 +0200118#define CONFIG_USE_ONENAND_BOARD_INIT
119#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
120#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000121
Ladislav Michl43a60622016-07-12 20:28:32 +0200122/* NAND config */
Ladislav Michl43a60622016-07-12 20:28:32 +0200123#define CONFIG_SPL_OMAP3_ID_NAND
Stefano Babic0cd41182015-07-26 15:18:15 +0200124#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000125#define CONFIG_SYS_NAND_5_ADDR_CYCLE
126#define CONFIG_SYS_NAND_PAGE_COUNT 64
127#define CONFIG_SYS_NAND_PAGE_SIZE 2048
128#define CONFIG_SYS_NAND_OOBSIZE 64
129#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +0200130#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
131#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
132 10, 11, 12, 13, 14, 15, 16, 17, \
133 18, 19, 20, 21, 22, 23, 24, 25, \
134 26, 27, 28, 29, 30, 31, 32, 33, \
135 34, 35, 36, 37, 38, 39, 40, 41, \
136 42, 43, 44, 45, 46, 47, 48, 49, \
137 50, 51, 52, 53, 54, 55, 56, 57, }
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000138#define CONFIG_SYS_NAND_ECCSIZE 512
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +0200139#define CONFIG_SYS_NAND_ECCBYTES 14
140#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
141#define CONFIG_NAND_OMAP_GPMC
142#define CONFIG_BCH
143
Ladislav Michl43a60622016-07-12 20:28:32 +0200144/* UBI configuration */
145#define CONFIG_SPL_UBI 1
146#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
147#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
148#define CONFIG_SPL_UBI_MAX_PEBS 4096
149#define CONFIG_SPL_UBI_VOL_IDS 8
150#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
151#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
152#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
153#define CONFIG_SPL_UBI_PEB_OFFSET 4
154#define CONFIG_SPL_UBI_VID_OFFSET 512
155#define CONFIG_SPL_UBI_LEB_START 2048
156#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
157
158/* environment organization */
159#define CONFIG_ENV_IS_IN_UBI 1
160#define CONFIG_ENV_UBI_PART "UBI"
161#define CONFIG_ENV_UBI_VOLUME "config"
162#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
163#define CONFIG_UBI_SILENCE_MSG 1
164#define CONFIG_UBIFS_SILENCE_MSG 1
165#define CONFIG_ENV_SIZE (32*1024)
166
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +0000167#endif /* __IGEP00X0_H */