| Michal Simek | 21d62e6 | 2007-03-27 00:32:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 Michal Simek |
| 3 | * |
| 4 | * Michal SIMEK <monstr@monstr.eu> |
| 5 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| Michal Simek | 21d62e6 | 2007-03-27 00:32:16 +0200 | [diff] [blame] | 7 | * |
| Stephan Linz | 2dd5cb1 | 2012-02-25 00:48:33 +0000 | [diff] [blame] | 8 | * CAUTION: This file is a faked configuration !!! |
| 9 | * There is no real target for the microblaze-generic |
| 10 | * configuration. You have to replace this file with |
| 11 | * the generated file from your Xilinx design flow. |
| Michal Simek | 21d62e6 | 2007-03-27 00:32:16 +0200 | [diff] [blame] | 12 | */ |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 13 | |
| Michal Simek | 0d14165 | 2008-12-19 13:25:55 +0100 | [diff] [blame] | 14 | #define XILINX_BOARD_NAME microblaze-generic |
| 15 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 16 | /* System Clock Frequency */ |
| Michal Simek | 9251df3 | 2007-04-21 20:53:31 +0200 | [diff] [blame] | 17 | #define XILINX_CLOCK_FREQ 100000000 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 18 | |
| Michal Simek | 9594583 | 2007-05-05 18:54:42 +0200 | [diff] [blame] | 19 | /* Microblaze is microblaze_0 */ |
| Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 20 | #define XILINX_USE_MSR_INSTR 1 |
| Michal Simek | 603aa74 | 2007-05-07 17:11:09 +0200 | [diff] [blame] | 21 | #define XILINX_FSL_NUMBER 3 |
| Michal Simek | 9594583 | 2007-05-05 18:54:42 +0200 | [diff] [blame] | 22 | |
| Michal Simek | 603aa74 | 2007-05-07 17:11:09 +0200 | [diff] [blame] | 23 | /* Interrupt controller is opb_intc_0 */ |
| Michal Simek | 9251df3 | 2007-04-21 20:53:31 +0200 | [diff] [blame] | 24 | #define XILINX_INTC_BASEADDR 0x41200000 |
| Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 25 | #define XILINX_INTC_NUM_INTR_INPUTS 6 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 26 | |
| Michal Simek | 603aa74 | 2007-05-07 17:11:09 +0200 | [diff] [blame] | 27 | /* Timer pheriphery is opb_timer_1 */ |
| Michal Simek | 9251df3 | 2007-04-21 20:53:31 +0200 | [diff] [blame] | 28 | #define XILINX_TIMER_BASEADDR 0x41c00000 |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 29 | #define XILINX_TIMER_IRQ 0 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 30 | |
| Michal Simek | 603aa74 | 2007-05-07 17:11:09 +0200 | [diff] [blame] | 31 | /* GPIO is LEDs_4Bit*/ |
| 32 | #define XILINX_GPIO_BASEADDR 0x40000000 |
| 33 | |
| 34 | /* Flash Memory is FLASH_2Mx32 */ |
| Michal Simek | 9251df3 | 2007-04-21 20:53:31 +0200 | [diff] [blame] | 35 | #define XILINX_FLASH_START 0x2c000000 |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 36 | #define XILINX_FLASH_SIZE 0x00800000 |
| 37 | |
| Michal Simek | 80e045f | 2013-04-22 11:23:16 +0200 | [diff] [blame] | 38 | /* Watchdog IP is wxi_timebase_wdt_0 */ |
| 39 | #define XILINX_WATCHDOG_BASEADDR 0x50000000 |
| 40 | #define XILINX_WATCHDOG_IRQ 1 |