| Michal Simek | 21d62e6 | 2007-03-27 00:32:16 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2007 Michal Simek |
| 3 | * |
| 4 | * Michal SIMEK <monstr@monstr.eu> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | * |
| 24 | * |
| 25 | * CAUTION: This file is automatically generated by libgen. |
| 26 | * Version: Xilinx EDK 6.3 EDK_Gmm.12.3 |
| 27 | */ |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 28 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 29 | /* System Clock Frequency */ |
| 30 | #define XILINX_CLOCK_FREQ 66666667 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 31 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 32 | /* Interrupt controller is intc_0 */ |
| 33 | #define XILINX_INTC_BASEADDR 0xd1000fc0 |
| 34 | #define XILINX_INTC_NUM_INTR_INPUTS 12 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 35 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 36 | /* Timer pheriphery is opb_timer_0 */ |
| 37 | #define XILINX_TIMER_BASEADDR 0xa2000000 |
| 38 | #define XILINX_TIMER_IRQ 0 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 39 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 40 | /* Uart pheriphery is console_uart */ |
| 41 | #define XILINX_UART_BASEADDR 0xa0000000 |
| 42 | #define XILINX_UART_BAUDRATE 115200 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 43 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 44 | /* GPIO is opb_gpio_0*/ |
| 45 | #define XILINX_GPIO_BASEADDR 0x90000000 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 46 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 47 | /* Flash Memory is opb_emc_0 */ |
| 48 | #define XILINX_FLASH_START 0x28000000 |
| 49 | #define XILINX_FLASH_SIZE 0x00800000 |
| 50 | |
| 51 | /* Main Memory is plb_ddr_0 */ |
| 52 | #define XILINX_RAM_START 0x10000000 |
| 53 | #define XILINX_RAM_SIZE 0x10000000 |
| 54 | |
| 55 | /* Sysace Controller is opb_sysace_0 */ |
| 56 | #define XILINX_SYSACE_BASEADDR 0xCF000000 |
| 57 | #define XILINX_SYSACE_HIGHADDR 0xCF0001FF |
| 58 | #define XILINX_SYSACE_MEM_WIDTH 16 |
| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 59 | |
| Michal Simek | 1f0c40c | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 60 | /* Ethernet controller is opb_ethernet_0 */ |
| 61 | #define XPAR_XEMAC_NUM_INSTANCES 1 |
| 62 | #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 |
| 63 | #define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 |
| 64 | #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF |
| 65 | #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 |
| 66 | #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 |
| 67 | #define XPAR_OPB_ETHERNET_0_MII_EXIST 1 |