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Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +02001#ifndef __ASM_ARM_SYSTEM_H
2#define __ASM_ARM_SYSTEM_H
3
Sergey Temerkhanov064949c2015-10-14 09:55:46 -07004#include <linux/compiler.h>
Tom Rini3b787ef2016-08-01 18:54:53 -04005#include <asm/barriers.h>
Sergey Temerkhanov064949c2015-10-14 09:55:46 -07006
David Feng85fd5f12013-12-14 11:47:35 +08007#ifdef CONFIG_ARM64
8
9/*
10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
11 */
12#define CR_M (1 << 0) /* MMU enable */
13#define CR_A (1 << 1) /* Alignment abort enable */
14#define CR_C (1 << 2) /* Dcache enable */
15#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
16#define CR_I (1 << 12) /* Icache enable */
17#define CR_WXN (1 << 19) /* Write Permision Imply XN */
18#define CR_EE (1 << 25) /* Exception (Big) Endian */
19
Alison Wang73818d52016-11-10 10:49:03 +080020#define ES_TO_AARCH64 1
21#define ES_TO_AARCH32 0
22
23/*
24 * SCR_EL3 bits definitions
25 */
26#define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
27#define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
28#define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
29#define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
30#define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
Chee Hong Angb07ac0c2018-08-20 10:57:34 -070031#define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */
Alison Wang73818d52016-11-10 10:49:03 +080032#define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
33
34/*
35 * SPSR_EL3/SPSR_EL2 bits definitions
36 */
37#define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
38#define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
39#define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
40#define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
41#define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
42#define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
43#define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
44#define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
45#define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
46#define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
47#define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
48#define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
49#define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
50
51/*
52 * CPTR_EL2 bits definitions
53 */
54#define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
55
56/*
57 * SCTLR_EL2 bits definitions
58 */
59#define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
60 1 << 11 | 3 << 4) /* Reserved, RES1 */
61#define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
62#define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
63#define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
64#define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
65#define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
66#define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
67#define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
68
69/*
70 * CNTHCTL_EL2 bits definitions
71 */
72#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
73#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
74
75/*
76 * HCR_EL2 bits definitions
77 */
78#define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
79#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
80#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
81
82/*
83 * CPACR_EL1 bits definitions
84 */
85#define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
86
87/*
88 * SCTLR_EL1 bits definitions
89 */
90#define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
91 1 << 11) /* Reserved, RES1 */
92#define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
93#define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
94#define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
95#define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
96#define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
97#define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
98#define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
99#define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
100#define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
101#define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
102#define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
103#define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
104#define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
105#define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
106#define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
107#define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
108#define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
109
David Feng85fd5f12013-12-14 11:47:35 +0800110#ifndef __ASSEMBLY__
111
Simon Glass1e268642020-05-10 11:39:55 -0600112struct pt_regs;
113
Alexander Grafe317fe82016-03-04 01:09:47 +0100114u64 get_page_table_size(void);
115#define PGTABLE_SIZE get_page_table_size()
Alexander Grafce0a64e2016-03-04 01:09:54 +0100116
117/* 2MB granularity */
118#define MMU_SECTION_SHIFT 21
119#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
Alexander Grafe317fe82016-03-04 01:09:47 +0100120
Alexander Graf188c8ff2016-03-16 15:41:20 +0100121/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +0530122enum dcache_option {
Alexander Graf188c8ff2016-03-16 15:41:20 +0100123 DCACHE_OFF = 0 << 2,
124 DCACHE_WRITETHROUGH = 3 << 2,
125 DCACHE_WRITEBACK = 4 << 2,
126 DCACHE_WRITEALLOC = 4 << 2,
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +0530127};
128
David Feng85fd5f12013-12-14 11:47:35 +0800129#define wfi() \
130 ({asm volatile( \
131 "wfi" : : : "memory"); \
132 })
133
134static inline unsigned int current_el(void)
135{
Heinrich Schuchardtea9a22d2020-05-27 20:04:24 +0200136 unsigned long el;
137
David Feng85fd5f12013-12-14 11:47:35 +0800138 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
Heinrich Schuchardtea9a22d2020-05-27 20:04:24 +0200139 return 3 & (el >> 2);
David Feng85fd5f12013-12-14 11:47:35 +0800140}
141
142static inline unsigned int get_sctlr(void)
143{
Heinrich Schuchardtea9a22d2020-05-27 20:04:24 +0200144 unsigned int el;
145 unsigned long val;
David Feng85fd5f12013-12-14 11:47:35 +0800146
147 el = current_el();
148 if (el == 1)
149 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
150 else if (el == 2)
151 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
152 else
153 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
154
155 return val;
156}
157
Heinrich Schuchardtea9a22d2020-05-27 20:04:24 +0200158static inline void set_sctlr(unsigned long val)
David Feng85fd5f12013-12-14 11:47:35 +0800159{
160 unsigned int el;
161
162 el = current_el();
163 if (el == 1)
164 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
165 else if (el == 2)
166 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
167 else
168 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
169
170 asm volatile("isb");
171}
172
Sergey Temerkhanov6774e4e2015-10-14 09:55:44 -0700173static inline unsigned long read_mpidr(void)
174{
175 unsigned long val;
176
177 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
178
179 return val;
180}
181
182#define BSP_COREID 0
183
David Feng85fd5f12013-12-14 11:47:35 +0800184void __asm_flush_dcache_all(void);
York Sunef042012014-02-26 13:26:04 -0800185void __asm_invalidate_dcache_all(void);
David Feng85fd5f12013-12-14 11:47:35 +0800186void __asm_flush_dcache_range(u64 start, u64 end);
Simon Glass4415c3b2017-04-05 17:53:18 -0600187
188/**
189 * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
190 *
191 * This performance an invalidate from @start to @end - 1. Both addresses
192 * should be cache-aligned, otherwise this function will align the start
193 * address and may continue past the end address.
194 *
195 * Data in the address range is evicted from the cache and is not written back
196 * to memory.
197 *
198 * @start: Start address to invalidate
199 * @end: End address to invalidate up to (exclusive)
200 */
201void __asm_invalidate_dcache_range(u64 start, u64 end);
David Feng85fd5f12013-12-14 11:47:35 +0800202void __asm_invalidate_tlb_all(void);
203void __asm_invalidate_icache_all(void);
Stephen Warrenddb0f632016-10-19 15:18:46 -0600204int __asm_invalidate_l3_dcache(void);
205int __asm_flush_l3_dcache(void);
206int __asm_invalidate_l3_icache(void);
Alexander Grafe317fe82016-03-04 01:09:47 +0100207void __asm_switch_ttbr(u64 new_ttbr);
David Feng85fd5f12013-12-14 11:47:35 +0800208
Alison Wang73818d52016-11-10 10:49:03 +0800209/*
Marek Szyprowskidacbb3b2020-06-03 14:43:41 +0200210 * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
Alison Wang73818d52016-11-10 10:49:03 +0800211 *
212 * @args: For loading 64-bit OS, fdt address.
213 * For loading 32-bit OS, zero.
214 * @mach_nr: For loading 64-bit OS, zero.
215 * For loading 32-bit OS, machine nr
216 * @fdt_addr: For loading 64-bit OS, zero.
217 * For loading 32-bit OS, fdt address.
Alison Wangeb2088d2017-01-17 09:39:17 +0800218 * @arg4: Input argument.
Alison Wang73818d52016-11-10 10:49:03 +0800219 * @entry_point: kernel entry point
220 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
221 */
York Sunffea3e62017-09-28 08:42:14 -0700222void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
223 u64 arg4, u64 entry_point, u64 es_flag);
Alison Wang73818d52016-11-10 10:49:03 +0800224/*
Marek Szyprowskidacbb3b2020-06-03 14:43:41 +0200225 * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
Alison Wang73818d52016-11-10 10:49:03 +0800226 *
227 * @args: For loading 64-bit OS, fdt address.
228 * For loading 32-bit OS, zero.
229 * @mach_nr: For loading 64-bit OS, zero.
230 * For loading 32-bit OS, machine nr
231 * @fdt_addr: For loading 64-bit OS, zero.
232 * For loading 32-bit OS, fdt address.
Alison Wangeb2088d2017-01-17 09:39:17 +0800233 * @arg4: Input argument.
Alison Wang73818d52016-11-10 10:49:03 +0800234 * @entry_point: kernel entry point
235 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
236 */
237void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
Alison Wangeb2088d2017-01-17 09:39:17 +0800238 u64 arg4, u64 entry_point, u64 es_flag);
Alison Wangf547fca2016-11-10 10:49:05 +0800239void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
Alison Wangeb2088d2017-01-17 09:39:17 +0800240 u64 arg4, u64 entry_point);
David Feng85fd5f12013-12-14 11:47:35 +0800241void gic_init(void);
242void gic_send_sgi(unsigned long sgino);
243void wait_for_wakeup(void);
Ian Campbelld07e7b02015-04-21 07:18:36 +0200244void protect_secure_region(void);
David Feng85fd5f12013-12-14 11:47:35 +0800245void smp_kick_all_cpus(void);
246
York Suna84cd722014-06-23 15:15:54 -0700247void flush_l3_cache(void);
York Sun5bb14e02017-03-06 09:02:33 -0800248void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
York Suna84cd722014-06-23 15:15:54 -0700249
Sergey Temerkhanov064949c2015-10-14 09:55:46 -0700250/*
Marek Szyprowskidacbb3b2020-06-03 14:43:41 +0200251 * smc_call() - issue a secure monitor call
252 *
253 * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
Sergey Temerkhanov064949c2015-10-14 09:55:46 -0700254 * DEN0028A
255 *
256 * @args: input and output arguments
Sergey Temerkhanov064949c2015-10-14 09:55:46 -0700257 */
258void smc_call(struct pt_regs *args);
259
Alexander Grafa5b18322016-08-16 21:08:46 +0200260void __noreturn psci_system_reset(void);
Rajesh Ravi45bbe712019-11-22 14:50:01 -0800261void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
Alexander Graf467c83e2016-08-16 21:08:47 +0200262void __noreturn psci_system_off(void);
Beniamino Galvanib8845e12016-05-08 08:30:14 +0200263
macro.wave.z@gmail.com05725ed2016-12-08 11:58:25 +0800264#ifdef CONFIG_ARMV8_PSCI
265extern char __secure_start[];
266extern char __secure_end[];
267extern char __secure_stack_start[];
268extern char __secure_stack_end[];
269
270void armv8_setup_psci(void);
271void psci_setup_vectors(void);
272void psci_arch_init(void);
273#endif
274
David Feng85fd5f12013-12-14 11:47:35 +0800275#endif /* __ASSEMBLY__ */
276
277#else /* CONFIG_ARM64 */
278
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200279#ifdef __KERNEL__
280
281#define CPU_ARCH_UNKNOWN 0
282#define CPU_ARCH_ARMv3 1
283#define CPU_ARCH_ARMv4 2
284#define CPU_ARCH_ARMv4T 3
285#define CPU_ARCH_ARMv5 4
286#define CPU_ARCH_ARMv5T 5
287#define CPU_ARCH_ARMv5TE 6
288#define CPU_ARCH_ARMv5TEJ 7
289#define CPU_ARCH_ARMv6 8
290#define CPU_ARCH_ARMv7 9
291
292/*
293 * CR1 bits (CP#15 CR1)
294 */
295#define CR_M (1 << 0) /* MMU enable */
296#define CR_A (1 << 1) /* Alignment abort enable */
297#define CR_C (1 << 2) /* Dcache enable */
298#define CR_W (1 << 3) /* Write buffer enable */
299#define CR_P (1 << 4) /* 32-bit exception handler */
300#define CR_D (1 << 5) /* 32-bit data address range */
301#define CR_L (1 << 6) /* Implementation defined */
302#define CR_B (1 << 7) /* Big endian */
303#define CR_S (1 << 8) /* System MMU protection */
304#define CR_R (1 << 9) /* ROM MMU protection */
305#define CR_F (1 << 10) /* Implementation defined */
306#define CR_Z (1 << 11) /* Implementation defined */
307#define CR_I (1 << 12) /* Icache enable */
308#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
309#define CR_RR (1 << 14) /* Round Robin cache replacement */
310#define CR_L4 (1 << 15) /* LDR pc can set T bit */
311#define CR_DT (1 << 16)
312#define CR_IT (1 << 18)
313#define CR_ST (1 << 19)
314#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
315#define CR_U (1 << 22) /* Unaligned access operation */
316#define CR_XP (1 << 23) /* Extended page tables */
317#define CR_VE (1 << 24) /* Vectored interrupts */
318#define CR_EE (1 << 25) /* Exception (Big) Endian */
319#define CR_TRE (1 << 28) /* TEX remap enable */
320#define CR_AFE (1 << 29) /* Access flag enable */
321#define CR_TE (1 << 30) /* Thumb exception enable */
322
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100323#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
324#define PGTABLE_SIZE (4096 * 5)
325#elif !defined(PGTABLE_SIZE)
David Feng85fd5f12013-12-14 11:47:35 +0800326#define PGTABLE_SIZE (4096 * 4)
Sergey Temerkhanov78eaa492015-10-14 09:55:45 -0700327#endif
David Feng85fd5f12013-12-14 11:47:35 +0800328
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200329/*
330 * This is used to ensure the compiler did actually allocate the register we
331 * asked it for some inline assembly sequences. Apparently we can't trust
332 * the compiler from one version to another so a bit of paranoia won't hurt.
333 * This string is meant to be concatenated with the inline asm string and
334 * will cause compilation to stop on mismatch.
335 * (for details, see gcc PR 15089)
336 */
337#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
338
339#ifndef __ASSEMBLY__
340
Keerthy61488c12016-09-14 10:43:32 +0530341#ifdef CONFIG_ARMV7_LPAE
342void switch_to_hypervisor_ret(void);
343#endif
344
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200345#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
346
Rob Herringaa470302012-12-02 17:06:21 +0000347#ifdef __ARM_ARCH_7A__
348#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
349#else
350#define wfi()
351#endif
352
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100353static inline unsigned long get_cpsr(void)
354{
355 unsigned long cpsr;
356
357 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
358 return cpsr;
359}
360
361static inline int is_hyp(void)
362{
363#ifdef CONFIG_ARMV7_LPAE
364 /* HYP mode requires LPAE ... */
365 return ((get_cpsr() & 0x1f) == 0x1a);
366#else
367 /* ... so without LPAE support we can optimize all hyp code away */
368 return 0;
369#endif
370}
371
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200372static inline unsigned int get_cr(void)
373{
374 unsigned int val;
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100375
376 if (is_hyp())
377 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
378 :
379 : "cc");
380 else
381 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
382 :
383 : "cc");
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200384 return val;
385}
386
387static inline void set_cr(unsigned int val)
388{
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100389 if (is_hyp())
390 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
391 : "r" (val)
392 : "cc");
393 else
394 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
395 : "r" (val)
396 : "cc");
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200397 isb();
398}
399
R Sricharan06396c12013-03-04 20:04:45 +0000400static inline unsigned int get_dacr(void)
401{
402 unsigned int val;
403 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
404 return val;
405}
406
407static inline void set_dacr(unsigned int val)
408{
409 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
410 : : "r" (val) : "cc");
411 isb();
412}
413
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100414#ifdef CONFIG_ARMV7_LPAE
415/* Long-Descriptor Translation Table Level 1/2 Bits */
416#define TTB_SECT_XN_MASK (1ULL << 54)
417#define TTB_SECT_NG_MASK (1 << 11)
418#define TTB_SECT_AF (1 << 10)
419#define TTB_SECT_SH_MASK (3 << 8)
420#define TTB_SECT_NS_MASK (1 << 5)
421#define TTB_SECT_AP (1 << 6)
422/* Note: TTB AP bits are set elsewhere */
423#define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
424#define TTB_SECT (1 << 0)
425#define TTB_PAGETABLE (3 << 0)
426
427/* TTBCR flags */
428#define TTBCR_EAE (1 << 31)
429#define TTBCR_T0SZ(x) ((x) << 0)
430#define TTBCR_T1SZ(x) ((x) << 16)
431#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
432#define TTBCR_IRGN0_NC (0 << 8)
433#define TTBCR_IRGN0_WBWA (1 << 8)
434#define TTBCR_IRGN0_WT (2 << 8)
435#define TTBCR_IRGN0_WBNWA (3 << 8)
436#define TTBCR_IRGN0_MASK (3 << 8)
437#define TTBCR_ORGN0_NC (0 << 10)
438#define TTBCR_ORGN0_WBWA (1 << 10)
439#define TTBCR_ORGN0_WT (2 << 10)
440#define TTBCR_ORGN0_WBNWA (3 << 10)
441#define TTBCR_ORGN0_MASK (3 << 10)
442#define TTBCR_SHARED_NON (0 << 12)
443#define TTBCR_SHARED_OUTER (2 << 12)
444#define TTBCR_SHARED_INNER (3 << 12)
445#define TTBCR_EPD0 (0 << 7)
446
447/*
448 * Memory types
449 */
450#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
451 (0xcc << (2 * 8)) | (0xff << (3 * 8)))
452
453/* options available for data cache on each page */
454enum dcache_option {
Keerthy266c8c12016-10-29 15:19:10 +0530455 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100456 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
457 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
458 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
459};
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530460#elif defined(CONFIG_CPU_V7A)
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500461/* Short-Descriptor Translation Table Level 1 Bits */
462#define TTB_SECT_NS_MASK (1 << 19)
463#define TTB_SECT_NG_MASK (1 << 17)
464#define TTB_SECT_S_MASK (1 << 16)
465/* Note: TTB AP bits are set elsewhere */
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100466#define TTB_SECT_AP (3 << 10)
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500467#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
468#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
469#define TTB_SECT_XN_MASK (1 << 4)
470#define TTB_SECT_C_MASK (1 << 3)
471#define TTB_SECT_B_MASK (1 << 2)
472#define TTB_SECT (2 << 0)
473
Simon Glassa4f20792012-10-17 13:24:53 +0000474/* options available for data cache on each page */
475enum dcache_option {
Marek Vasutd6e436e2015-12-29 19:44:02 +0100476 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500477 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
478 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
479 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
480};
481#else
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100482#define TTB_SECT_AP (3 << 10)
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500483/* options available for data cache on each page */
484enum dcache_option {
Simon Glassa4f20792012-10-17 13:24:53 +0000485 DCACHE_OFF = 0x12,
486 DCACHE_WRITETHROUGH = 0x1a,
487 DCACHE_WRITEBACK = 0x1e,
Marek Vasut79b90722014-09-15 02:44:36 +0200488 DCACHE_WRITEALLOC = 0x16,
Simon Glassa4f20792012-10-17 13:24:53 +0000489};
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500490#endif
Simon Glassa4f20792012-10-17 13:24:53 +0000491
Patrick Delaunayd7e6a1d2020-04-24 20:20:16 +0200492#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
493#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
494#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
495#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
496#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
497#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
498#endif
499
Simon Glassa4f20792012-10-17 13:24:53 +0000500/* Size of an MMU section */
501enum {
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100502#ifdef CONFIG_ARMV7_LPAE
503 MMU_SECTION_SHIFT = 21, /* 2MB */
504#else
505 MMU_SECTION_SHIFT = 20, /* 1MB */
506#endif
Simon Glassa4f20792012-10-17 13:24:53 +0000507 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
508};
509
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530510#ifdef CONFIG_CPU_V7A
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500511/* TTBR0 bits */
512#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
513#define TTBR0_RGN_NC (0 << 3)
514#define TTBR0_RGN_WBWA (1 << 3)
515#define TTBR0_RGN_WT (2 << 3)
516#define TTBR0_RGN_WB (3 << 3)
517/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
518#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
519#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
520#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
521#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
522#endif
523
Simon Glassa4f20792012-10-17 13:24:53 +0000524/**
Marek Szyprowskidacbb3b2020-06-03 14:43:41 +0200525 * mmu_page_table_flush() - register an update to page tables
526 *
Simon Glassa4f20792012-10-17 13:24:53 +0000527 * Register an update to the page tables, and flush the TLB
528 *
Marek Szyprowskidacbb3b2020-06-03 14:43:41 +0200529 * @start: start address of update in page table
530 * @stop: stop address of update in page table
Simon Glassa4f20792012-10-17 13:24:53 +0000531 */
532void mmu_page_table_flush(unsigned long start, unsigned long stop);
533
Patrick Delaunay9c59d862019-07-22 14:19:20 +0200534#ifdef CONFIG_ARMV7_PSCI
535void psci_arch_cpu_entry(void);
Masahiro Yamadab047d1b2020-05-20 11:43:34 +0900536void psci_arch_init(void);
Patrick Delaunay9c59d862019-07-22 14:19:20 +0200537u32 psci_version(void);
538s32 psci_features(u32 function_id, u32 psci_fid);
539s32 psci_cpu_off(void);
540s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
541 u32 context_id);
542s32 psci_affinity_info(u32 function_id, u32 target_affinity,
543 u32 lowest_affinity_level);
544u32 psci_migrate_info_type(void);
545void psci_system_off(void);
546void psci_system_reset(void);
547s32 psci_features(u32 function_id, u32 psci_fid);
548#endif
549
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200550#endif /* __ASSEMBLY__ */
551
552#define arch_align_stack(x) (x)
553
554#endif /* __KERNEL__ */
555
David Feng85fd5f12013-12-14 11:47:35 +0800556#endif /* CONFIG_ARM64 */
557
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +0530558#ifndef __ASSEMBLY__
559/**
Philipp Tomsichcd36d452017-10-10 16:21:11 +0200560 * save_boot_params() - Save boot parameters before starting reset sequence
561 *
562 * If you provide this function it will be called immediately U-Boot starts,
563 * both for SPL and U-Boot proper.
564 *
565 * All registers are unchanged from U-Boot entry. No registers need be
566 * preserved.
567 *
568 * This is not a normal C function. There is no stack. Return by branching to
569 * save_boot_params_ret.
570 *
571 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
572 */
573
574/**
575 * save_boot_params_ret() - Return from save_boot_params()
576 *
577 * If you provide save_boot_params(), then you should jump back to this
578 * function when done. Try to preserve all registers.
579 *
580 * If your implementation of save_boot_params() is in C then it is acceptable
581 * to simply call save_boot_params_ret() at the end of your function. Since
582 * there is no link register set up, you cannot just exit the function. U-Boot
583 * will return to the (initialised) value of lr, and likely crash/hang.
584 *
585 * If your implementation of save_boot_params() is in assembler then you
586 * should use 'b' or 'bx' to return to save_boot_params_ret.
587 */
588void save_boot_params_ret(void);
589
590/**
Marek Szyprowskif76fb512020-06-03 14:43:42 +0200591 * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
592 *
593 * Change the virt/phys mapping and cache settings for a region.
594 *
595 * @virt: virtual start address of memory region to change
596 * @phys: physical address for the memory region to set
597 * @size: size of memory region to change
598 * @option: dcache option to select
599 */
600void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
601 size_t size, enum dcache_option option);
602
603/**
Marek Szyprowskidacbb3b2020-06-03 14:43:41 +0200604 * mmu_set_region_dcache_behaviour() - set cache settings
605 *
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +0530606 * Change the cache settings for a region.
607 *
Marek Szyprowskidacbb3b2020-06-03 14:43:41 +0200608 * @start: start address of memory region to change
609 * @size: size of memory region to change
610 * @option: dcache option to select
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +0530611 */
612void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
613 enum dcache_option option);
614
Stephen Warrenfbdcd222015-10-05 12:08:59 -0600615#ifdef CONFIG_SYS_NONCACHED_MEMORY
616void noncached_init(void);
617phys_addr_t noncached_alloc(size_t size, size_t align);
618#endif /* CONFIG_SYS_NONCACHED_MEMORY */
619
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +0530620#endif /* __ASSEMBLY__ */
621
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200622#endif