Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Socfpga Reset Controller Driver |
| 4 | * |
| 5 | * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> |
| 6 | * |
| 7 | * based on |
| 8 | * Allwinner SoCs Reset Controller driver |
| 9 | * |
| 10 | * Copyright 2013 Maxime Ripard |
| 11 | * |
| 12 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 13 | */ |
| 14 | |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 15 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 16 | #include <log.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 17 | #include <malloc.h> |
Simon Goldschmidt | fc82466 | 2019-07-15 21:47:55 +0200 | [diff] [blame] | 18 | #include <dm/lists.h> |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 19 | #include <dm/of_access.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 20 | #include <env.h> |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 21 | #include <reset-uclass.h> |
Ley Foon Tan | 30f1775 | 2020-01-10 13:48:37 +0800 | [diff] [blame] | 22 | #include <wait_bit.h> |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 23 | #include <linux/bitops.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/sizes.h> |
| 26 | |
| 27 | #define BANK_INCREMENT 4 |
| 28 | #define NR_BANKS 8 |
| 29 | |
| 30 | struct socfpga_reset_data { |
Simon Goldschmidt | 53a0cf5 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 31 | void __iomem *modrst_base; |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 32 | }; |
| 33 | |
Simon Goldschmidt | e568bb7 | 2019-03-01 20:12:32 +0100 | [diff] [blame] | 34 | /* |
| 35 | * For compatibility with Kernels that don't support peripheral reset, this |
| 36 | * driver can keep the old behaviour of not asserting peripheral reset before |
| 37 | * starting the OS and deasserting all peripheral resets (enabling all |
| 38 | * peripherals). |
| 39 | * |
| 40 | * For that, the reset driver checks the environment variable |
| 41 | * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not |
| 42 | * reset again once taken out of reset and all peripherals in 'permodrst' are |
| 43 | * taken out of reset before booting into the OS. |
| 44 | * Note that this should be required for gen5 systems only that are running |
| 45 | * Linux kernels without proper peripheral reset support for all drivers used. |
| 46 | */ |
| 47 | static bool socfpga_reset_keep_enabled(void) |
| 48 | { |
| 49 | #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT) |
| 50 | const char *env_str; |
| 51 | long val; |
| 52 | |
| 53 | env_str = env_get("socfpga_legacy_reset_compat"); |
| 54 | if (env_str) { |
| 55 | val = simple_strtol(env_str, NULL, 0); |
| 56 | if (val == 1) |
| 57 | return true; |
| 58 | } |
| 59 | #endif |
| 60 | |
| 61 | return false; |
| 62 | } |
| 63 | |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 64 | static int socfpga_reset_assert(struct reset_ctl *reset_ctl) |
| 65 | { |
| 66 | struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); |
| 67 | int id = reset_ctl->id; |
| 68 | int reg_width = sizeof(u32); |
| 69 | int bank = id / (reg_width * BITS_PER_BYTE); |
| 70 | int offset = id % (reg_width * BITS_PER_BYTE); |
| 71 | |
Simon Goldschmidt | 53a0cf5 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 72 | setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) |
| 77 | { |
| 78 | struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); |
| 79 | int id = reset_ctl->id; |
| 80 | int reg_width = sizeof(u32); |
| 81 | int bank = id / (reg_width * BITS_PER_BYTE); |
| 82 | int offset = id % (reg_width * BITS_PER_BYTE); |
| 83 | |
Simon Goldschmidt | 53a0cf5 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 84 | clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); |
Ley Foon Tan | 30f1775 | 2020-01-10 13:48:37 +0800 | [diff] [blame] | 85 | |
| 86 | return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT), |
| 87 | BIT(offset), |
| 88 | false, 500, false); |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 89 | } |
| 90 | |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 91 | static const struct reset_ops socfpga_reset_ops = { |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 92 | .rst_assert = socfpga_reset_assert, |
| 93 | .rst_deassert = socfpga_reset_deassert, |
| 94 | }; |
| 95 | |
| 96 | static int socfpga_reset_probe(struct udevice *dev) |
| 97 | { |
| 98 | struct socfpga_reset_data *data = dev_get_priv(dev); |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 99 | u32 modrst_offset; |
Simon Goldschmidt | 53a0cf5 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 100 | void __iomem *membase; |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 101 | |
Masahiro Yamada | 32822d0 | 2020-08-04 14:14:43 +0900 | [diff] [blame] | 102 | membase = dev_read_addr_ptr(dev); |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 103 | |
Simon Goldschmidt | e5291ad | 2019-05-09 22:11:59 +0200 | [diff] [blame] | 104 | modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10); |
Simon Goldschmidt | 53a0cf5 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 105 | data->modrst_base = membase + modrst_offset; |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 106 | |
| 107 | return 0; |
| 108 | } |
| 109 | |
Simon Goldschmidt | e568bb7 | 2019-03-01 20:12:32 +0100 | [diff] [blame] | 110 | static int socfpga_reset_remove(struct udevice *dev) |
| 111 | { |
| 112 | struct socfpga_reset_data *data = dev_get_priv(dev); |
| 113 | |
| 114 | if (socfpga_reset_keep_enabled()) { |
| 115 | puts("Deasserting all peripheral resets\n"); |
| 116 | writel(0, data->modrst_base + 4); |
| 117 | } |
| 118 | |
| 119 | return 0; |
| 120 | } |
| 121 | |
Simon Goldschmidt | fc82466 | 2019-07-15 21:47:55 +0200 | [diff] [blame] | 122 | static int socfpga_reset_bind(struct udevice *dev) |
| 123 | { |
| 124 | int ret; |
| 125 | struct udevice *sys_child; |
| 126 | |
| 127 | /* |
| 128 | * The sysreset driver does not have a device node, so bind it here. |
| 129 | * Bind it to the node, too, so that it can get its base address. |
| 130 | */ |
| 131 | ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset", |
Simon Glass | a7ece58 | 2020-12-19 10:40:14 -0700 | [diff] [blame] | 132 | dev_ofnode(dev), &sys_child); |
Simon Goldschmidt | fc82466 | 2019-07-15 21:47:55 +0200 | [diff] [blame] | 133 | if (ret) |
| 134 | debug("Warning: No sysreset driver: ret=%d\n", ret); |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 139 | static const struct udevice_id socfpga_reset_match[] = { |
| 140 | { .compatible = "altr,rst-mgr" }, |
| 141 | { /* sentinel */ }, |
| 142 | }; |
| 143 | |
| 144 | U_BOOT_DRIVER(socfpga_reset) = { |
| 145 | .name = "socfpga-reset", |
| 146 | .id = UCLASS_RESET, |
| 147 | .of_match = socfpga_reset_match, |
Simon Goldschmidt | fc82466 | 2019-07-15 21:47:55 +0200 | [diff] [blame] | 148 | .bind = socfpga_reset_bind, |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 149 | .probe = socfpga_reset_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 150 | .priv_auto = sizeof(struct socfpga_reset_data), |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 151 | .ops = &socfpga_reset_ops, |
Simon Goldschmidt | e568bb7 | 2019-03-01 20:12:32 +0100 | [diff] [blame] | 152 | .remove = socfpga_reset_remove, |
| 153 | .flags = DM_FLAG_OS_PREPARE, |
Dinh Nguyen | 5427f5a | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 154 | }; |