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Tom Warrena3e280b2011-01-27 10:58:07 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __TEGRA2_COMMON_H
25#define __TEGRA2_COMMON_H
26#include <asm/sizes.h>
27
28/*
29 * High Level Configuration Options
30 */
31#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
32#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
33#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
Aneesh Vecee9c82011-06-16 23:30:48 +000034#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
Tom Warrena3e280b2011-01-27 10:58:07 +000035
Anton staaf5420cba2011-10-03 13:54:58 +000036#define CONFIG_SYS_CACHELINE_SIZE 32
37
Simon Glass5f3a8992011-11-05 03:56:49 +000038#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */
Tom Warren112a1882011-04-14 12:18:06 +000039
Tom Warrena3e280b2011-01-27 10:58:07 +000040#include <asm/arch/tegra2.h> /* get chip and board defs */
41
42/*
43 * Display CPU and Board information
44 */
45#define CONFIG_DISPLAY_CPUINFO
46#define CONFIG_DISPLAY_BOARDINFO
47
Tom Warrena3e280b2011-01-27 10:58:07 +000048#define CONFIG_SKIP_LOWLEVEL_INIT
49
50#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Grant Likely100b8492011-03-28 09:59:07 +000051#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
Tom Warrena3e280b2011-01-27 10:58:07 +000052
53/* Environment */
Simon Glass4e61a342011-11-05 04:46:48 +000054#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
Tom Warrena3e280b2011-01-27 10:58:07 +000055
56/*
57 * Size of malloc() pool
58 */
59#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
60
61/*
62 * PllX Configuration
63 */
64#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
65
66/*
67 * NS16550 Configuration
68 */
69#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
70
71#define CONFIG_SYS_NS16550
72#define CONFIG_SYS_NS16550_SERIAL
73#define CONFIG_SYS_NS16550_REG_SIZE (-4)
74#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
75
76/*
77 * select serial console configuration
78 */
79#define CONFIG_CONS_INDEX 1
80
81/* allow to overwrite serial and ethaddr */
82#define CONFIG_ENV_OVERWRITE
83#define CONFIG_BAUDRATE 115200
84#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
85 115200}
86
Simon Glass9d580862012-02-27 10:52:51 +000087/*
88 * This parameter affects a TXFILLTUNING field that controls how much data is
89 * sent to the latency fifo before it is sent to the wire. Without this
90 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
91 * packets depending on the buffer address and size.
92 */
93#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
94#define CONFIG_EHCI_IS_TDI
95#define CONFIG_EHCI_DCACHE
96
Simon Glassaac60882012-02-03 15:13:59 +000097/* Total I2C ports on Tegra2 */
98#define TEGRA_I2C_NUM_CONTROLLERS 4
99
Tom Warrena3e280b2011-01-27 10:58:07 +0000100/* include default commands */
101#include <config_cmd_default.h>
102
103/* remove unused commands */
104#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
105#undef CONFIG_CMD_FPGA /* FPGA configuration support */
106#undef CONFIG_CMD_IMI
107#undef CONFIG_CMD_IMLS
108#undef CONFIG_CMD_NFS /* NFS support */
109#undef CONFIG_CMD_NET /* network support */
110
111/* turn on command-line edit/hist/auto */
112#define CONFIG_CMDLINE_EDITING
113#define CONFIG_COMMAND_HISTORY
Mike Frysingerc1285cb2011-10-26 00:19:58 +0000114#define CONFIG_AUTO_COMPLETE
Tom Warrena3e280b2011-01-27 10:58:07 +0000115
116#define CONFIG_SYS_NO_FLASH
117
118/* Environment information */
119#define CONFIG_EXTRA_ENV_SETTINGS \
120 "console=ttyS0,115200n8\0" \
121 "mem=" TEGRA2_SYSMEM "\0" \
122 "smpflag=smp\0" \
123
124#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
125#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
126
127/*
128 * Miscellaneous configurable options
129 */
130#define CONFIG_SYS_LONGHELP /* undef to save memory */
131#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
132#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
133#define CONFIG_SYS_PROMPT V_PROMPT
134/*
135 * Increasing the size of the IO buffer as default nfsargs size is more
136 * than 256 and so it is not possible to edit it
137 */
138#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
139/* Print Buffer Size */
140#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
141 sizeof(CONFIG_SYS_PROMPT) + 16)
142#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
143/* Boot Argument Buffer Size */
144#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
145
146#define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000)
147#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
148
149#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
150#define CONFIG_SYS_HZ 1000
151
152/*-----------------------------------------------------------------------
153 * Stack sizes
154 *
155 * The stack sizes are set up in start.S using the settings below
156 */
157#define CONFIG_STACKBASE 0x2800000 /* 40MB */
158#define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/
159
160/*-----------------------------------------------------------------------
161 * Physical Memory Map
162 */
163#define CONFIG_NR_DRAM_BANKS 1
164#define PHYS_SDRAM_1 TEGRA2_SDRC_CS0
165#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
166
Thierry Reding925fae62011-11-17 00:04:06 +0000167#define CONFIG_SYS_TEXT_BASE 0x00108000
Tom Warrena3e280b2011-01-27 10:58:07 +0000168#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
169
170#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
171#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
172#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
173 CONFIG_SYS_INIT_RAM_SIZE - \
174 GENERATED_GBL_DATA_SIZE)
175
Tom Warren6e3806b2011-06-17 06:27:29 +0000176#define CONFIG_TEGRA2_GPIO
177#define CONFIG_CMD_GPIO
Tom Warrena3e280b2011-01-27 10:58:07 +0000178#endif /* __TEGRA2_COMMON_H */