blob: a9c665c8d802735a7e5ec217587367c18e9264eb [file] [log] [blame]
Tom Warrena3e280b2011-01-27 10:58:07 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __TEGRA2_COMMON_H
25#define __TEGRA2_COMMON_H
26#include <asm/sizes.h>
27
28/*
29 * High Level Configuration Options
30 */
31#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
32#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
33#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
Aneesh Vecee9c82011-06-16 23:30:48 +000034#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
Tom Warrena3e280b2011-01-27 10:58:07 +000035
Anton staaf5420cba2011-10-03 13:54:58 +000036#define CONFIG_SYS_CACHELINE_SIZE 32
37
Tom Warren112a1882011-04-14 12:18:06 +000038#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
39
Tom Warrena3e280b2011-01-27 10:58:07 +000040#include <asm/arch/tegra2.h> /* get chip and board defs */
41
42/*
43 * Display CPU and Board information
44 */
45#define CONFIG_DISPLAY_CPUINFO
46#define CONFIG_DISPLAY_BOARDINFO
47
48#define CONFIG_SKIP_RELOCATE_UBOOT
49#define CONFIG_SKIP_LOWLEVEL_INIT
50
51#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Grant Likely100b8492011-03-28 09:59:07 +000052#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
Tom Warrena3e280b2011-01-27 10:58:07 +000053
54/* Environment */
55#define CONFIG_ENV_IS_NOWHERE
56#define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */
57
58/*
59 * Size of malloc() pool
60 */
61#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
62
63/*
64 * PllX Configuration
65 */
66#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
67
68/*
69 * NS16550 Configuration
70 */
71#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
72
73#define CONFIG_SYS_NS16550
74#define CONFIG_SYS_NS16550_SERIAL
75#define CONFIG_SYS_NS16550_REG_SIZE (-4)
76#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
77
78/*
79 * select serial console configuration
80 */
81#define CONFIG_CONS_INDEX 1
82
83/* allow to overwrite serial and ethaddr */
84#define CONFIG_ENV_OVERWRITE
85#define CONFIG_BAUDRATE 115200
86#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
87 115200}
88
89/* include default commands */
90#include <config_cmd_default.h>
91
92/* remove unused commands */
93#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
94#undef CONFIG_CMD_FPGA /* FPGA configuration support */
95#undef CONFIG_CMD_IMI
96#undef CONFIG_CMD_IMLS
97#undef CONFIG_CMD_NFS /* NFS support */
98#undef CONFIG_CMD_NET /* network support */
99
100/* turn on command-line edit/hist/auto */
101#define CONFIG_CMDLINE_EDITING
102#define CONFIG_COMMAND_HISTORY
103#define CONFIG_AUTOCOMPLETE
104
105#define CONFIG_SYS_NO_FLASH
106
107/* Environment information */
108#define CONFIG_EXTRA_ENV_SETTINGS \
109 "console=ttyS0,115200n8\0" \
110 "mem=" TEGRA2_SYSMEM "\0" \
111 "smpflag=smp\0" \
112
113#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
114#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
115
116/*
117 * Miscellaneous configurable options
118 */
119#define CONFIG_SYS_LONGHELP /* undef to save memory */
120#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
121#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
122#define CONFIG_SYS_PROMPT V_PROMPT
123/*
124 * Increasing the size of the IO buffer as default nfsargs size is more
125 * than 256 and so it is not possible to edit it
126 */
127#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
128/* Print Buffer Size */
129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
130 sizeof(CONFIG_SYS_PROMPT) + 16)
131#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
132/* Boot Argument Buffer Size */
133#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
134
135#define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000)
136#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
137
138#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
139#define CONFIG_SYS_HZ 1000
140
141/*-----------------------------------------------------------------------
142 * Stack sizes
143 *
144 * The stack sizes are set up in start.S using the settings below
145 */
146#define CONFIG_STACKBASE 0x2800000 /* 40MB */
147#define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/
148
149/*-----------------------------------------------------------------------
150 * Physical Memory Map
151 */
152#define CONFIG_NR_DRAM_BANKS 1
153#define PHYS_SDRAM_1 TEGRA2_SDRC_CS0
154#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
155
156#define CONFIG_SYS_TEXT_BASE 0x00E08000
157#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
158
159#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
160#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
161#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
162 CONFIG_SYS_INIT_RAM_SIZE - \
163 GENERATED_GBL_DATA_SIZE)
164
Tom Warren6e3806b2011-06-17 06:27:29 +0000165#define CONFIG_TEGRA2_GPIO
166#define CONFIG_CMD_GPIO
Tom Warrena3e280b2011-01-27 10:58:07 +0000167#endif /* __TEGRA2_COMMON_H */