Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / f32c5b1e4904924d0a3487570478705f5be7c1a1 / . / doc / device-tree-bindings / memory-controllers / st,stm32mp1-ddr.txt
blob: e6ea8d0ef54ba172e01448e694932f4d789ff076 [file] [log] [blame]
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]1ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
2
3--------------------
4Required properties:
5--------------------
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]6- compatible : Should be "st,stm32mp1-ddr" for STM32MP15x
7 Should be "st,stm32mp13-ddr" for STM32MP13x
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]8- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
9- clocks : controller clocks handle
10- clock-names : associated controller clock names
11 the "ddrphyc" clock is used to check the DDR frequency
12 at phy level according the expected value in "mem-speed" field
13
14the next attributes are DDR parameters, they are generated by DDR tools
15included in STM32 Cube tool
16
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]17They are required only in SPL, when TFABOOT is not activated.
18
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]19info attributes:
20----------------
21- st,mem-name : name for DDR configuration, simple string for information
Patrick Delaunay29e1a942019-04-10 14:09:23 +0200[diff] [blame]22- st,mem-speed : DDR expected speed for the setting in kHz
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]23- st,mem-size : DDR mem size in byte
24
25
26controlleur attributes:
27-----------------------
28- st,ctl-reg : controleur values depending of the DDR type
29 (DDR3/LPDDR2/LPDDR3)
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]30 for STM32MP15x and STM32MP13x: 25 values are requested in this order
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]31 MSTR
32 MRCTRL0
33 MRCTRL1
34 DERATEEN
35 DERATEINT
36 PWRCTL
37 PWRTMG
38 HWLPCTL
39 RFSHCTL0
40 RFSHCTL3
41 CRCPARCTL0
42 ZQCTL0
43 DFITMG0
44 DFITMG1
45 DFILPCFG0
46 DFIUPD0
47 DFIUPD1
48 DFIUPD2
49 DFIPHYMSTR
50 ODTMAP
51 DBG0
52 DBG1
53 DBGCMD
54 POISONCFG
55 PCCFG
56
57- st,ctl-timing : controleur values depending of frequency and timing parameter
58 of DDR
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]59 for STM32MP15x and STM32MP13x: 12 values are requested in this order
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]60 RFSHTMG
61 DRAMTMG0
62 DRAMTMG1
63 DRAMTMG2
64 DRAMTMG3
65 DRAMTMG4
66 DRAMTMG5
67 DRAMTMG6
68 DRAMTMG7
69 DRAMTMG8
70 DRAMTMG14
71 ODTCFG
72
73- st,ctl-map : controleur values depending of address mapping
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]74 for STM32MP15x and STM32MP13x: 9 values are requested in this order
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]75 ADDRMAP1
76 ADDRMAP2
77 ADDRMAP3
78 ADDRMAP4
79 ADDRMAP5
80 ADDRMAP6
81 ADDRMAP9
82 ADDRMAP10
83 ADDRMAP11
84
85- st,ctl-perf : controleur values depending of performance and scheduling
86 for STM32MP15x: 17 values are requested in this order
87 SCHED
88 SCHED1
89 PERFHPR1
90 PERFLPR1
91 PERFWR1
92 PCFGR_0
93 PCFGW_0
94 PCFGQOS0_0
95 PCFGQOS1_0
96 PCFGWQOS0_0
97 PCFGWQOS1_0
98 PCFGR_1
99 PCFGW_1
100 PCFGQOS0_1
101 PCFGQOS1_1
102 PCFGWQOS0_1
103 PCFGWQOS1_1
104
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]105 for STM32MP13x: 11 values are requested in this order
106 SCHED
107 SCHED1
108 PERFHPR1
109 PERFLPR1
110 PERFWR1
111 PCFGR_0
112 PCFGW_0
113 PCFGQOS0_0
114 PCFGQOS1_0
115 PCFGWQOS0_0
116 PCFGWQOS1_0
117
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]118phyc attributes:
119----------------
120- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
Patrick Delaunayd892d272019-04-10 14:09:25 +0200[diff] [blame]121 for STM32MP15x: 11 values are requested in this order
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]122 PGCR
123 ACIOCR
124 DXCCR
125 DSGCR
126 DCR
127 ODTCR
128 ZQ0CR1
129 DX0GCR
130 DX1GCR
131 DX2GCR
132 DX3GCR
133
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]134 for STM32MP13x: 9 values are requested in this order
135 PGCR
136 ACIOCR
137 DXCCR
138 DSGCR
139 DCR
140 ODTCR
141 ZQ0CR1
142 DX0GCR
143 DX1GCR
144
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]145- st,phy-timing : phy values depending of frequency and timing parameter of DDR
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]146 for STM32MP15x and STM32MP13x: 10 values are requested in this order
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]147 PTR0
148 PTR1
149 PTR2
150 DTPR0
151 DTPR1
152 DTPR2
153 MR0
154 MR1
155 MR2
156 MR3
157
Patrick Delaunayb5bb08d2022-05-20 18:24:50 +0200[diff] [blame]158 for STM32MP13x: 6 values are requested in this order
159 DX0DLLCR
160 DX0DQTR
161 DX0DQSTR
162 DX1DLLCR
163 DX1DQTR
164 DX1DQSTR
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]165Example:
166
167/ {
168 soc {
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]169 ddr: ddr@0x5A003000{
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]170 compatible = "st,stm32mp1-ddr";
171
172 reg = <0x5A003000 0x550
173 0x5A004000 0x234>;
174
175 clocks = <&rcc_clk AXIDCG>,
176 <&rcc_clk DDRC1>,
177 <&rcc_clk DDRC2>,
178 <&rcc_clk DDRPHYC>,
179 <&rcc_clk DDRCAPB>,
180 <&rcc_clk DDRPHYCAPB>;
181
182 clock-names = "axidcg",
183 "ddrc1",
184 "ddrc2",
185 "ddrphyc",
186 "ddrcapb",
187 "ddrphycapb";
188
189 st,mem-name = "DDR3 2x4Gb 533MHz";
Patrick Delaunay29e1a942019-04-10 14:09:23 +0200[diff] [blame]190 st,mem-speed = <533000>;
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]191 st,mem-size = <0x40000000>;
192
193 st,ctl-reg = <
194 0x00040401 /*MSTR*/
195 0x00000010 /*MRCTRL0*/
196 0x00000000 /*MRCTRL1*/
197 0x00000000 /*DERATEEN*/
198 0x00800000 /*DERATEINT*/
199 0x00000000 /*PWRCTL*/
200 0x00400010 /*PWRTMG*/
201 0x00000000 /*HWLPCTL*/
202 0x00210000 /*RFSHCTL0*/
203 0x00000000 /*RFSHCTL3*/
204 0x00000000 /*CRCPARCTL0*/
205 0xC2000040 /*ZQCTL0*/
206 0x02050105 /*DFITMG0*/
207 0x00000202 /*DFITMG1*/
208 0x07000000 /*DFILPCFG0*/
209 0xC0400003 /*DFIUPD0*/
210 0x00000000 /*DFIUPD1*/
211 0x00000000 /*DFIUPD2*/
212 0x00000000 /*DFIPHYMSTR*/
213 0x00000001 /*ODTMAP*/
214 0x00000000 /*DBG0*/
215 0x00000000 /*DBG1*/
216 0x00000000 /*DBGCMD*/
217 0x00000000 /*POISONCFG*/
218 0x00000010 /*PCCFG*/
219 >;
220
221 st,ctl-timing = <
222 0x0080008A /*RFSHTMG*/
223 0x121B2414 /*DRAMTMG0*/
224 0x000D041B /*DRAMTMG1*/
225 0x0607080E /*DRAMTMG2*/
226 0x0050400C /*DRAMTMG3*/
227 0x07040407 /*DRAMTMG4*/
228 0x06060303 /*DRAMTMG5*/
229 0x02020002 /*DRAMTMG6*/
230 0x00000202 /*DRAMTMG7*/
231 0x00001005 /*DRAMTMG8*/
232 0x000D041B /*DRAMTMG1*/4
233 0x06000600 /*ODTCFG*/
234 >;
235
236 st,ctl-map = <
237 0x00080808 /*ADDRMAP1*/
238 0x00000000 /*ADDRMAP2*/
239 0x00000000 /*ADDRMAP3*/
240 0x00001F1F /*ADDRMAP4*/
241 0x07070707 /*ADDRMAP5*/
242 0x0F070707 /*ADDRMAP6*/
243 0x00000000 /*ADDRMAP9*/
244 0x00000000 /*ADDRMAP10*/
245 0x00000000 /*ADDRMAP11*/
246 >;
247
248 st,ctl-perf = <
249 0x00001201 /*SCHED*/
250 0x00001201 /*SCHED*/1
251 0x01000001 /*PERFHPR1*/
252 0x08000200 /*PERFLPR1*/
253 0x08000400 /*PERFWR1*/
254 0x00010000 /*PCFGR_0*/
255 0x00000000 /*PCFGW_0*/
256 0x02100B03 /*PCFGQOS0_0*/
257 0x00800100 /*PCFGQOS1_0*/
258 0x01100B03 /*PCFGWQOS0_0*/
259 0x01000200 /*PCFGWQOS1_0*/
260 0x00010000 /*PCFGR_1*/
261 0x00000000 /*PCFGW_1*/
262 0x02100B03 /*PCFGQOS0_1*/
263 0x00800000 /*PCFGQOS1_1*/
264 0x01100B03 /*PCFGWQOS0_1*/
265 0x01000200 /*PCFGWQOS1_1*/
266 >;
267
268 st,phy-reg = <
269 0x01442E02 /*PGCR*/
270 0x10400812 /*ACIOCR*/
271 0x00000C40 /*DXCCR*/
272 0xF200001F /*DSGCR*/
273 0x0000000B /*DCR*/
274 0x00010000 /*ODTCR*/
275 0x0000007B /*ZQ0CR1*/
276 0x0000CE81 /*DX0GCR*/
277 0x0000CE81 /*DX1GCR*/
278 0x0000CE81 /*DX2GCR*/
279 0x0000CE81 /*DX3GCR*/
280 >;
281
282 st,phy-timing = <
283 0x0022A41B /*PTR0*/
284 0x047C0740 /*PTR1*/
285 0x042D9C80 /*PTR2*/
286 0x369477D0 /*DTPR0*/
287 0x098A00D8 /*DTPR1*/
288 0x10023600 /*DTPR2*/
289 0x00000830 /*MR0*/
290 0x00000000 /*MR1*/
291 0x00000208 /*MR2*/
292 0x00000000 /*MR3*/
293 >;
294
Patrick Delaunay939d5362018-03-12 10:46:11 +0100[diff] [blame]295 status = "okay";
296 };
297 };
298};