| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Ruchika Gupta | 8ca8d82 | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
| Ruchika Gupta | 8ca8d82 | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __FSL_SECURE_BOOT_H |
| 7 | #define __FSL_SECURE_BOOT_H |
| gaurav rana | 8b5ea65 | 2015-02-27 09:46:17 +0530 | [diff] [blame] | 8 | #include <asm/config_mpc85xx.h> |
| Ruchika Gupta | 8ca8d82 | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 9 | |
| Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 10 | #ifdef CONFIG_NXP_ESBC |
| Ruchika Gupta | 8ca8d82 | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 11 | #if defined(CONFIG_FSL_CORENET) |
| 12 | #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 |
| 13 | #else |
| 14 | #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 |
| 15 | #endif |
| 16 | #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 |
| 17 | |
| Tom Rini | bf1dfd8 | 2022-06-17 16:24:34 -0400 | [diff] [blame] | 18 | #if defined(CONFIG_TARGET_T2080QDS) || \ |
| York Sun | a05baa4 | 2016-12-28 08:43:37 -0800 | [diff] [blame] | 19 | defined(CONFIG_TARGET_T2080RDB) || \ |
| York Sun | 097aa60 | 2016-11-21 11:25:26 -0800 | [diff] [blame] | 20 | defined(CONFIG_TARGET_T1042RDB) || \ |
| 21 | defined(CONFIG_TARGET_T1042D4RDB) || \ |
| 22 | defined(CONFIG_TARGET_T1042RDB_PI) || \ |
| York Sun | 7d29dd6 | 2016-11-18 13:01:34 -0800 | [diff] [blame] | 23 | defined(CONFIG_ARCH_T1024) |
| Aneesh Bansal | 8bcbc27 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 24 | #undef CONFIG_SYS_INIT_L3_ADDR |
| 25 | #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 |
| 26 | #endif |
| 27 | |
| Aneesh Bansal | e0f5015 | 2015-06-16 10:36:00 +0530 | [diff] [blame] | 28 | #if defined(CONFIG_RAMBOOT_PBL) |
| 29 | #undef CONFIG_SYS_INIT_L3_ADDR |
| Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 30 | #ifdef CONFIG_SYS_INIT_L3_VADDR |
| 31 | #define CONFIG_SYS_INIT_L3_ADDR \ |
| 32 | (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ |
| 33 | 0xbff00000 |
| 34 | #else |
| 35 | #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 |
| 36 | #endif |
| Aneesh Bansal | e0f5015 | 2015-06-16 10:36:00 +0530 | [diff] [blame] | 37 | #endif |
| 38 | |
| York Sun | df70d06 | 2016-11-18 11:20:40 -0800 | [diff] [blame] | 39 | #if defined(CONFIG_ARCH_P3041) || \ |
| York Sun | 84be8a9 | 2016-11-18 11:24:40 -0800 | [diff] [blame] | 40 | defined(CONFIG_ARCH_P4080) || \ |
| York Sun | a3c5b66 | 2016-11-18 11:39:36 -0800 | [diff] [blame] | 41 | defined(CONFIG_ARCH_P5040) || \ |
| York Sun | 5786fca | 2016-11-18 11:15:21 -0800 | [diff] [blame] | 42 | defined(CONFIG_ARCH_P2041) |
| gaurav rana | 8b5ea65 | 2015-02-27 09:46:17 +0530 | [diff] [blame] | 43 | #define CONFIG_FSL_TRUST_ARCH_v1 |
| 44 | #endif |
| 45 | |
| Aneesh Bansal | d31bb3e | 2015-07-31 14:10:03 +0530 | [diff] [blame] | 46 | #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) |
| gaurav rana | 8b5ea65 | 2015-02-27 09:46:17 +0530 | [diff] [blame] | 47 | /* The key used for verification of next level images |
| 48 | * is picked up from an Extension Table which has |
| 49 | * been verified by the ISBC (Internal Secure boot Code) |
| Aneesh Bansal | d31bb3e | 2015-07-31 14:10:03 +0530 | [diff] [blame] | 50 | * in boot ROM of the SoC. |
| 51 | * The feature is only applicable in case of NOR boot and is |
| 52 | * not applicable in case of RAMBOOT (NAND, SD, SPI). |
| gaurav rana | 8b5ea65 | 2015-02-27 09:46:17 +0530 | [diff] [blame] | 53 | */ |
| 54 | #define CONFIG_FSL_ISBC_KEY_EXT |
| 55 | #endif |
| Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 56 | #endif /* #ifdef CONFIG_NXP_ESBC */ |
| gaurav rana | 8b5ea65 | 2015-02-27 09:46:17 +0530 | [diff] [blame] | 57 | |
| Aneesh Bansal | 4310470 | 2016-01-22 16:37:24 +0530 | [diff] [blame] | 58 | #ifdef CONFIG_CHAIN_OF_TRUST |
| Simon Glass | 3aa6612 | 2016-09-12 23:18:23 -0600 | [diff] [blame] | 59 | #ifdef CONFIG_SPL_BUILD |
| Sumit Garg | f6d96cb | 2016-07-14 12:27:51 -0400 | [diff] [blame] | 60 | /* |
| 61 | * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init |
| 62 | * due to space crunch on CPC and thus malloc will not work. |
| 63 | */ |
| 64 | #define CONFIG_SPL_PPAACT_ADDR 0x2e000000 |
| 65 | #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 |
| 66 | #define CONFIG_SPL_JR0_LIODN_S 454 |
| 67 | #define CONFIG_SPL_JR0_LIODN_NS 458 |
| Sumit Garg | f6d96cb | 2016-07-14 12:27:51 -0400 | [diff] [blame] | 68 | #endif /* ifdef CONFIG_SPL_BUILD */ |
| 69 | |
| Sumit Garg | f6d96cb | 2016-07-14 12:27:51 -0400 | [diff] [blame] | 70 | #ifndef CONFIG_SPL_BUILD |
| Aneesh Bansal | 4310470 | 2016-01-22 16:37:24 +0530 | [diff] [blame] | 71 | #include <config_fsl_chain_trust.h> |
| Sumit Garg | f6d96cb | 2016-07-14 12:27:51 -0400 | [diff] [blame] | 72 | #endif /* #ifndef CONFIG_SPL_BUILD */ |
| Aneesh Bansal | 4310470 | 2016-01-22 16:37:24 +0530 | [diff] [blame] | 73 | #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ |
| Po Liu | d103009 | 2013-08-21 14:20:21 +0800 | [diff] [blame] | 74 | #endif |