Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Xiaowei Bao | 3a13e29 | 2020-01-08 14:29:54 +0800 | [diff] [blame] | 3 | * Copyright 2018-2020 NXP |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 85d6531 | 2019-12-28 10:44:58 -0700 | [diff] [blame] | 7 | #include <clock_legacy.h> |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 8 | #include <dm.h> |
| 9 | #include <dm/platform_data/serial_pl01x.h> |
| 10 | #include <i2c.h> |
| 11 | #include <malloc.h> |
| 12 | #include <errno.h> |
| 13 | #include <netdev.h> |
| 14 | #include <fsl_ddr.h> |
| 15 | #include <fsl_sec.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <fdt_support.h> |
| 18 | #include <linux/libfdt.h> |
| 19 | #include <fsl-mc/fsl_mc.h> |
Simon Glass | 9d1f619 | 2019-08-02 09:44:25 -0600 | [diff] [blame] | 20 | #include <env_internal.h> |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 21 | #include <efi_loader.h> |
| 22 | #include <asm/arch/mmu.h> |
| 23 | #include <hwconfig.h> |
Pankaj Bansal | c6b6ba6 | 2019-08-17 01:07:32 +0000 | [diff] [blame] | 24 | #include <asm/arch/clock.h> |
| 25 | #include <asm/arch/config.h> |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 26 | #include <asm/arch/fsl_serdes.h> |
| 27 | #include <asm/arch/soc.h> |
| 28 | #include "../common/qixis.h" |
| 29 | #include "../common/vid.h" |
| 30 | #include <fsl_immap.h> |
Laurentiu Tudor | 7085d07 | 2019-10-18 09:01:55 +0000 | [diff] [blame] | 31 | #include <asm/arch-fsl-layerscape/fsl_icid.h> |
Wasim Khan | 2f7e016 | 2020-02-14 11:04:34 +0530 | [diff] [blame] | 32 | #include <asm/gic-v3.h> |
| 33 | #include <cpu_func.h> |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 34 | |
Meenakshi Aggarwal | 936a68d | 2018-11-30 22:32:12 +0530 | [diff] [blame] | 35 | #ifdef CONFIG_EMC2305 |
| 36 | #include "../common/emc2305.h" |
| 37 | #endif |
| 38 | |
Wasim Khan | 2f7e016 | 2020-02-14 11:04:34 +0530 | [diff] [blame] | 39 | #define GIC_LPI_SIZE 0x200000 |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 40 | #ifdef CONFIG_TARGET_LX2160AQDS |
| 41 | #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) |
| 42 | #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) |
| 43 | #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) |
| 44 | #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value) |
| 45 | #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value) |
| 46 | #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value) |
| 47 | #define SDHC1_BASE_PMUX_DSPI 2 |
| 48 | #define SDHC2_BASE_PMUX_DSPI 2 |
| 49 | #define IIC5_PMUX_SPI3 3 |
| 50 | #endif /* CONFIG_TARGET_LX2160AQDS */ |
| 51 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 52 | DECLARE_GLOBAL_DATA_PTR; |
| 53 | |
| 54 | static struct pl01x_serial_platdata serial0 = { |
| 55 | #if CONFIG_CONS_INDEX == 0 |
| 56 | .base = CONFIG_SYS_SERIAL0, |
| 57 | #elif CONFIG_CONS_INDEX == 1 |
| 58 | .base = CONFIG_SYS_SERIAL1, |
| 59 | #else |
| 60 | #error "Unsupported console index value." |
| 61 | #endif |
| 62 | .type = TYPE_PL011, |
| 63 | }; |
| 64 | |
| 65 | U_BOOT_DEVICE(nxp_serial0) = { |
| 66 | .name = "serial_pl01x", |
| 67 | .platdata = &serial0, |
| 68 | }; |
| 69 | |
| 70 | static struct pl01x_serial_platdata serial1 = { |
| 71 | .base = CONFIG_SYS_SERIAL1, |
| 72 | .type = TYPE_PL011, |
| 73 | }; |
| 74 | |
| 75 | U_BOOT_DEVICE(nxp_serial1) = { |
| 76 | .name = "serial_pl01x", |
| 77 | .platdata = &serial1, |
| 78 | }; |
| 79 | |
| 80 | int select_i2c_ch_pca9547(u8 ch) |
| 81 | { |
| 82 | int ret; |
| 83 | |
Chuanhua Han | 37c2c5e | 2019-07-10 21:00:20 +0800 | [diff] [blame] | 84 | #ifndef CONFIG_DM_I2C |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 85 | ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
Chuanhua Han | 37c2c5e | 2019-07-10 21:00:20 +0800 | [diff] [blame] | 86 | #else |
| 87 | struct udevice *dev; |
| 88 | |
| 89 | ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); |
| 90 | if (!ret) |
| 91 | ret = dm_i2c_write(dev, 0, &ch, 1); |
| 92 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 93 | if (ret) { |
| 94 | puts("PCA: failed to select proper channel\n"); |
| 95 | return ret; |
| 96 | } |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static void uart_get_clock(void) |
| 102 | { |
| 103 | serial0.clock = get_serial_clock(); |
| 104 | serial1.clock = get_serial_clock(); |
| 105 | } |
| 106 | |
| 107 | int board_early_init_f(void) |
| 108 | { |
| 109 | #ifdef CONFIG_SYS_I2C_EARLY_INIT |
| 110 | i2c_early_init_f(); |
| 111 | #endif |
| 112 | /* get required clock for UART IP */ |
| 113 | uart_get_clock(); |
| 114 | |
Meenakshi Aggarwal | 936a68d | 2018-11-30 22:32:12 +0530 | [diff] [blame] | 115 | #ifdef CONFIG_EMC2305 |
| 116 | select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305); |
| 117 | emc2305_init(); |
| 118 | set_fan_speed(I2C_EMC2305_PWM); |
| 119 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
| 120 | #endif |
| 121 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 122 | fsl_lsch3_early_init_f(); |
| 123 | return 0; |
| 124 | } |
| 125 | |
Pankaj Bansal | c6b6ba6 | 2019-08-17 01:07:32 +0000 | [diff] [blame] | 126 | #ifdef CONFIG_OF_BOARD_FIXUP |
| 127 | int board_fix_fdt(void *fdt) |
| 128 | { |
| 129 | char *reg_names, *reg_name; |
| 130 | int names_len, old_name_len, new_name_len, remaining_names_len; |
| 131 | struct str_map { |
| 132 | char *old_str; |
| 133 | char *new_str; |
| 134 | } reg_names_map[] = { |
Pankaj Bansal | 58ace21 | 2019-11-20 09:12:47 +0000 | [diff] [blame] | 135 | { "ccsr", "dbi" }, |
Pankaj Bansal | c6b6ba6 | 2019-08-17 01:07:32 +0000 | [diff] [blame] | 136 | { "pf_ctrl", "ctrl" } |
| 137 | }; |
Pankaj Bansal | 844e0ed | 2020-01-15 05:57:00 +0000 | [diff] [blame] | 138 | int off = -1, i = 0; |
Pankaj Bansal | c6b6ba6 | 2019-08-17 01:07:32 +0000 | [diff] [blame] | 139 | |
| 140 | if (IS_SVR_REV(get_svr(), 1, 0)) |
| 141 | return 0; |
| 142 | |
| 143 | off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie"); |
| 144 | while (off != -FDT_ERR_NOTFOUND) { |
| 145 | fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", |
| 146 | strlen("fsl,ls-pcie") + 1); |
| 147 | |
| 148 | reg_names = (char *)fdt_getprop(fdt, off, "reg-names", |
| 149 | &names_len); |
| 150 | if (!reg_names) |
| 151 | continue; |
| 152 | |
| 153 | reg_name = reg_names; |
| 154 | remaining_names_len = names_len - (reg_name - reg_names); |
Vikas Singh | 1fe634a | 2020-02-12 13:47:09 +0530 | [diff] [blame] | 155 | i = 0; |
Pankaj Bansal | 844e0ed | 2020-01-15 05:57:00 +0000 | [diff] [blame] | 156 | while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { |
Pankaj Bansal | c6b6ba6 | 2019-08-17 01:07:32 +0000 | [diff] [blame] | 157 | old_name_len = strlen(reg_names_map[i].old_str); |
| 158 | new_name_len = strlen(reg_names_map[i].new_str); |
| 159 | if (memcmp(reg_name, reg_names_map[i].old_str, |
| 160 | old_name_len) == 0) { |
| 161 | /* first only leave required bytes for new_str |
| 162 | * and copy rest of the string after it |
| 163 | */ |
| 164 | memcpy(reg_name + new_name_len, |
| 165 | reg_name + old_name_len, |
| 166 | remaining_names_len - old_name_len); |
| 167 | /* Now copy new_str */ |
| 168 | memcpy(reg_name, reg_names_map[i].new_str, |
| 169 | new_name_len); |
| 170 | names_len -= old_name_len; |
| 171 | names_len += new_name_len; |
Pankaj Bansal | 844e0ed | 2020-01-15 05:57:00 +0000 | [diff] [blame] | 172 | i++; |
Pankaj Bansal | c6b6ba6 | 2019-08-17 01:07:32 +0000 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | reg_name = memchr(reg_name, '\0', remaining_names_len); |
| 176 | if (!reg_name) |
| 177 | break; |
| 178 | |
| 179 | reg_name += 1; |
| 180 | |
| 181 | remaining_names_len = names_len - |
| 182 | (reg_name - reg_names); |
| 183 | } |
| 184 | |
| 185 | fdt_setprop(fdt, off, "reg-names", reg_names, names_len); |
| 186 | off = fdt_node_offset_by_compatible(fdt, off, |
| 187 | "fsl,lx2160a-pcie"); |
| 188 | } |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | #endif |
| 193 | |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 194 | #if defined(CONFIG_TARGET_LX2160AQDS) |
| 195 | void esdhc_dspi_status_fixup(void *blob) |
| 196 | { |
| 197 | const char esdhc0_path[] = "/soc/esdhc@2140000"; |
| 198 | const char esdhc1_path[] = "/soc/esdhc@2150000"; |
Xiaowei Bao | 3a13e29 | 2020-01-08 14:29:54 +0800 | [diff] [blame] | 199 | const char dspi0_path[] = "/soc/spi@2100000"; |
| 200 | const char dspi1_path[] = "/soc/spi@2110000"; |
| 201 | const char dspi2_path[] = "/soc/spi@2120000"; |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 202 | |
| 203 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 204 | u32 sdhc1_base_pmux; |
| 205 | u32 sdhc2_base_pmux; |
| 206 | u32 iic5_pmux; |
| 207 | |
| 208 | /* Check RCW field sdhc1_base_pmux to enable/disable |
| 209 | * esdhc0/dspi0 DT node |
| 210 | */ |
| 211 | sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) |
| 212 | & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; |
| 213 | sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; |
| 214 | |
| 215 | if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { |
| 216 | do_fixup_by_path(blob, dspi0_path, "status", "okay", |
| 217 | sizeof("okay"), 1); |
| 218 | do_fixup_by_path(blob, esdhc0_path, "status", "disabled", |
| 219 | sizeof("disabled"), 1); |
| 220 | } else { |
| 221 | do_fixup_by_path(blob, esdhc0_path, "status", "okay", |
| 222 | sizeof("okay"), 1); |
| 223 | do_fixup_by_path(blob, dspi0_path, "status", "disabled", |
| 224 | sizeof("disabled"), 1); |
| 225 | } |
| 226 | |
| 227 | /* Check RCW field sdhc2_base_pmux to enable/disable |
| 228 | * esdhc1/dspi1 DT node |
| 229 | */ |
| 230 | sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) |
| 231 | & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; |
| 232 | sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; |
| 233 | |
| 234 | if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { |
| 235 | do_fixup_by_path(blob, dspi1_path, "status", "okay", |
| 236 | sizeof("okay"), 1); |
| 237 | do_fixup_by_path(blob, esdhc1_path, "status", "disabled", |
| 238 | sizeof("disabled"), 1); |
| 239 | } else { |
| 240 | do_fixup_by_path(blob, esdhc1_path, "status", "okay", |
| 241 | sizeof("okay"), 1); |
| 242 | do_fixup_by_path(blob, dspi1_path, "status", "disabled", |
| 243 | sizeof("disabled"), 1); |
| 244 | } |
| 245 | |
| 246 | /* Check RCW field IIC5 to enable dspi2 DT node */ |
| 247 | iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) |
| 248 | & FSL_CHASSIS3_IIC5_PMUX_MASK; |
| 249 | iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; |
| 250 | |
Xiaowei Bao | 3a13e29 | 2020-01-08 14:29:54 +0800 | [diff] [blame] | 251 | if (iic5_pmux == IIC5_PMUX_SPI3) |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 252 | do_fixup_by_path(blob, dspi2_path, "status", "okay", |
| 253 | sizeof("okay"), 1); |
Xiaowei Bao | 3a13e29 | 2020-01-08 14:29:54 +0800 | [diff] [blame] | 254 | else |
| 255 | do_fixup_by_path(blob, dspi2_path, "status", "disabled", |
| 256 | sizeof("disabled"), 1); |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 257 | } |
| 258 | #endif |
| 259 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 260 | int esdhc_status_fixup(void *blob, const char *compat) |
| 261 | { |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 262 | #if defined(CONFIG_TARGET_LX2160AQDS) |
| 263 | /* Enable esdhc and dspi DT nodes based on RCW fields */ |
| 264 | esdhc_dspi_status_fixup(blob); |
| 265 | #else |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 266 | /* Enable both esdhc DT nodes for LX2160ARDB */ |
| 267 | do_fixup_by_compat(blob, compat, "status", "okay", |
| 268 | sizeof("okay"), 1); |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 269 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | #if defined(CONFIG_VID) |
| 274 | int i2c_multiplexer_select_vid_channel(u8 channel) |
| 275 | { |
| 276 | return select_i2c_ch_pca9547(channel); |
| 277 | } |
| 278 | |
Priyanka Jain | e94c324 | 2019-02-04 06:32:36 +0000 | [diff] [blame] | 279 | int init_func_vid(void) |
| 280 | { |
Meenakshi Aggarwal | cdc1200 | 2020-02-26 16:46:48 +0530 | [diff] [blame] | 281 | int set_vid; |
| 282 | |
| 283 | if (IS_SVR_REV(get_svr(), 1, 0)) |
| 284 | set_vid = adjust_vdd(800); |
| 285 | else |
| 286 | set_vid = adjust_vdd(0); |
| 287 | |
| 288 | if (set_vid < 0) |
Priyanka Jain | e94c324 | 2019-02-04 06:32:36 +0000 | [diff] [blame] | 289 | printf("core voltage not adjusted\n"); |
| 290 | |
| 291 | return 0; |
| 292 | } |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 293 | #endif |
| 294 | |
| 295 | int checkboard(void) |
| 296 | { |
| 297 | enum boot_src src = get_boot_src(); |
| 298 | char buf[64]; |
| 299 | u8 sw; |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 300 | #ifdef CONFIG_TARGET_LX2160AQDS |
| 301 | int clock; |
| 302 | static const char *const freq[] = {"100", "125", "156.25", |
| 303 | "161.13", "322.26", "", "", "", |
| 304 | "", "", "", "", "", "", "", |
| 305 | "100 separate SSCG"}; |
| 306 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 307 | |
| 308 | cpu_name(buf); |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 309 | #ifdef CONFIG_TARGET_LX2160AQDS |
| 310 | printf("Board: %s-QDS, ", buf); |
| 311 | #else |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 312 | printf("Board: %s-RDB, ", buf); |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 313 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 314 | |
| 315 | sw = QIXIS_READ(arch); |
| 316 | printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); |
| 317 | |
| 318 | if (src == BOOT_SOURCE_SD_MMC) { |
| 319 | puts("SD\n"); |
Meenakshi Aggarwal | 74bd499 | 2020-01-23 17:55:10 +0530 | [diff] [blame] | 320 | } else if (src == BOOT_SOURCE_SD_MMC2) { |
| 321 | puts("eMMC\n"); |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 322 | } else { |
| 323 | sw = QIXIS_READ(brdcfg[0]); |
| 324 | sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; |
| 325 | switch (sw) { |
| 326 | case 0: |
| 327 | case 4: |
| 328 | puts("FlexSPI DEV#0\n"); |
| 329 | break; |
| 330 | case 1: |
| 331 | puts("FlexSPI DEV#1\n"); |
| 332 | break; |
| 333 | case 2: |
| 334 | case 3: |
| 335 | puts("FlexSPI EMU\n"); |
| 336 | break; |
| 337 | default: |
| 338 | printf("invalid setting, xmap: %d\n", sw); |
| 339 | break; |
| 340 | } |
| 341 | } |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 342 | #ifdef CONFIG_TARGET_LX2160AQDS |
| 343 | printf("FPGA: v%d (%s), build %d", |
| 344 | (int)QIXIS_READ(scver), qixis_read_tag(buf), |
| 345 | (int)qixis_read_minor()); |
| 346 | /* the timestamp string contains "\n" at the end */ |
| 347 | printf(" on %s", qixis_read_time(buf)); |
| 348 | |
| 349 | puts("SERDES1 Reference : "); |
| 350 | sw = QIXIS_READ(brdcfg[2]); |
| 351 | clock = sw >> 4; |
| 352 | printf("Clock1 = %sMHz ", freq[clock]); |
| 353 | clock = sw & 0x0f; |
| 354 | printf("Clock2 = %sMHz", freq[clock]); |
| 355 | |
| 356 | sw = QIXIS_READ(brdcfg[3]); |
| 357 | puts("\nSERDES2 Reference : "); |
| 358 | clock = sw >> 4; |
| 359 | printf("Clock1 = %sMHz ", freq[clock]); |
| 360 | clock = sw & 0x0f; |
| 361 | printf("Clock2 = %sMHz", freq[clock]); |
| 362 | |
| 363 | sw = QIXIS_READ(brdcfg[12]); |
| 364 | puts("\nSERDES3 Reference : "); |
| 365 | clock = sw >> 4; |
| 366 | printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); |
| 367 | #else |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 368 | printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); |
| 369 | |
| 370 | puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); |
| 371 | puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); |
Meenakshi Aggarwal | 06f4388 | 2019-09-04 16:39:56 +0530 | [diff] [blame] | 372 | puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 373 | #endif |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | #ifdef CONFIG_TARGET_LX2160AQDS |
| 378 | /* |
| 379 | * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. |
| 380 | */ |
| 381 | u8 qixis_esdhc_detect_quirk(void) |
| 382 | { |
| 383 | /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1) |
| 384 | * SDHC1 Card ID: |
| 385 | * Specifies the type of card installed in the SDHC1 adapter slot. |
| 386 | * 000= (reserved) |
| 387 | * 001= eMMC V4.5 adapter is installed. |
| 388 | * 010= SD/MMC 3.3V adapter is installed. |
| 389 | * 011= eMMC V4.4 adapter is installed. |
| 390 | * 100= eMMC V5.0 adapter is installed. |
| 391 | * 101= MMC card/Legacy (3.3V) adapter is installed. |
| 392 | * 110= SDCard V2/V3 adapter installed. |
| 393 | * 111= no adapter is installed. |
| 394 | */ |
| 395 | return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) != |
| 396 | QIXIS_ESDHC_NO_ADAPTER); |
| 397 | } |
| 398 | |
| 399 | int config_board_mux(void) |
| 400 | { |
| 401 | u8 reg11, reg5, reg13; |
| 402 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 403 | u32 sdhc1_base_pmux; |
| 404 | u32 sdhc2_base_pmux; |
| 405 | u32 iic5_pmux; |
| 406 | |
| 407 | /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}. |
| 408 | * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}. |
| 409 | * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}. |
| 410 | * Qixis and remote systems are isolated from the I2C1 bus. |
| 411 | * Processor connections are still available. |
| 412 | * SPI2 CS2_B controls EN25S64 SPI memory device. |
| 413 | * SPI3 CS2_B controls EN25S64 SPI memory device. |
| 414 | * EC2 connects to PHY #2 using RGMII protocol. |
| 415 | * CLK_OUT connects to FPGA for clock measurement. |
| 416 | */ |
| 417 | |
| 418 | reg5 = QIXIS_READ(brdcfg[5]); |
| 419 | reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40); |
| 420 | QIXIS_WRITE(brdcfg[5], reg5); |
| 421 | |
| 422 | /* Check RCW field sdhc1_base_pmux |
| 423 | * esdhc0 : sdhc1_base_pmux = 0 |
| 424 | * dspi0 : sdhc1_base_pmux = 2 |
| 425 | */ |
| 426 | sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) |
| 427 | & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; |
| 428 | sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; |
| 429 | |
| 430 | if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { |
| 431 | reg11 = QIXIS_READ(brdcfg[11]); |
| 432 | reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40); |
| 433 | QIXIS_WRITE(brdcfg[11], reg11); |
| 434 | } else { |
| 435 | /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot. |
| 436 | * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot. |
| 437 | * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot. |
| 438 | */ |
| 439 | reg11 = QIXIS_READ(brdcfg[11]); |
| 440 | reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11); |
| 441 | QIXIS_WRITE(brdcfg[11], reg11); |
| 442 | } |
| 443 | |
| 444 | /* Check RCW field sdhc2_base_pmux |
| 445 | * esdhc1 : sdhc2_base_pmux = 0 (default) |
| 446 | * dspi1 : sdhc2_base_pmux = 2 |
| 447 | */ |
| 448 | sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) |
| 449 | & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; |
| 450 | sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; |
| 451 | |
| 452 | if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { |
| 453 | reg13 = QIXIS_READ(brdcfg[13]); |
| 454 | reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01); |
| 455 | QIXIS_WRITE(brdcfg[13], reg13); |
| 456 | } else { |
| 457 | reg13 = QIXIS_READ(brdcfg[13]); |
| 458 | reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00); |
| 459 | QIXIS_WRITE(brdcfg[13], reg13); |
| 460 | } |
| 461 | |
| 462 | /* Check RCW field IIC5 to enable dspi2 DT nodei |
| 463 | * dspi2: IIC5 = 3 |
| 464 | */ |
| 465 | iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) |
| 466 | & FSL_CHASSIS3_IIC5_PMUX_MASK; |
| 467 | iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; |
| 468 | |
| 469 | if (iic5_pmux == IIC5_PMUX_SPI3) { |
| 470 | /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */ |
| 471 | reg11 = QIXIS_READ(brdcfg[11]); |
| 472 | reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10); |
| 473 | QIXIS_WRITE(brdcfg[11], reg11); |
| 474 | |
| 475 | /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere. |
| 476 | * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }. |
| 477 | * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}. |
| 478 | */ |
| 479 | reg11 = QIXIS_READ(brdcfg[11]); |
| 480 | reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01); |
| 481 | QIXIS_WRITE(brdcfg[11], reg11); |
| 482 | } else { |
Yangbo Lu | a0923d7 | 2020-03-19 15:18:54 +0800 | [diff] [blame] | 483 | /* |
| 484 | * If {SDHC1_DAT4} has been configured to route to SDHC1_VS, |
| 485 | * do not change it. |
| 486 | * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot. |
| 487 | */ |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 488 | reg11 = QIXIS_READ(brdcfg[11]); |
Yangbo Lu | a0923d7 | 2020-03-19 15:18:54 +0800 | [diff] [blame] | 489 | if ((reg11 & 0x30) != 0x30) { |
| 490 | reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); |
| 491 | QIXIS_WRITE(brdcfg[11], reg11); |
| 492 | } |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 493 | |
| 494 | /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot. |
| 495 | * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot. |
| 496 | * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot. |
| 497 | */ |
| 498 | reg11 = QIXIS_READ(brdcfg[11]); |
| 499 | reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00); |
| 500 | QIXIS_WRITE(brdcfg[11], reg11); |
| 501 | } |
| 502 | |
| 503 | return 0; |
| 504 | } |
Pankaj Bansal | 504472c | 2019-07-17 09:34:34 +0000 | [diff] [blame] | 505 | #elif defined(CONFIG_TARGET_LX2160ARDB) |
| 506 | int config_board_mux(void) |
| 507 | { |
| 508 | u8 brdcfg; |
| 509 | |
| 510 | brdcfg = QIXIS_READ(brdcfg[4]); |
| 511 | /* The BRDCFG4 register controls general board configuration. |
| 512 | *|-------------------------------------------| |
| 513 | *|Field | Function | |
| 514 | *|-------------------------------------------| |
| 515 | *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| |
| 516 | *|CAN_EN | 0= CAN transceivers are disabled. | |
| 517 | *| | 1= CAN transceivers are enabled. | |
| 518 | *|-------------------------------------------| |
| 519 | */ |
| 520 | brdcfg |= BIT_MASK(5); |
| 521 | QIXIS_WRITE(brdcfg[4], brdcfg); |
| 522 | |
| 523 | return 0; |
| 524 | } |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 525 | #else |
| 526 | int config_board_mux(void) |
| 527 | { |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 528 | return 0; |
| 529 | } |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 530 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 531 | |
| 532 | unsigned long get_board_sys_clk(void) |
| 533 | { |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 534 | #ifdef CONFIG_TARGET_LX2160AQDS |
| 535 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
| 536 | |
| 537 | switch (sysclk_conf & 0x03) { |
| 538 | case QIXIS_SYSCLK_100: |
| 539 | return 100000000; |
| 540 | case QIXIS_SYSCLK_125: |
| 541 | return 125000000; |
| 542 | case QIXIS_SYSCLK_133: |
| 543 | return 133333333; |
| 544 | } |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 545 | return 100000000; |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 546 | #else |
| 547 | return 100000000; |
| 548 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 549 | } |
| 550 | |
| 551 | unsigned long get_board_ddr_clk(void) |
| 552 | { |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 553 | #ifdef CONFIG_TARGET_LX2160AQDS |
| 554 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
| 555 | |
| 556 | switch ((ddrclk_conf & 0x30) >> 4) { |
| 557 | case QIXIS_DDRCLK_100: |
| 558 | return 100000000; |
| 559 | case QIXIS_DDRCLK_125: |
| 560 | return 125000000; |
| 561 | case QIXIS_DDRCLK_133: |
| 562 | return 133333333; |
| 563 | } |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 564 | return 100000000; |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 565 | #else |
| 566 | return 100000000; |
| 567 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | int board_init(void) |
| 571 | { |
Florin Chiculita | d90d506 | 2019-04-22 11:57:47 +0300 | [diff] [blame] | 572 | #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) |
| 573 | u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; |
| 574 | #endif |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 575 | #ifdef CONFIG_ENV_IS_NOWHERE |
| 576 | gd->env_addr = (ulong)&default_environment[0]; |
| 577 | #endif |
| 578 | |
| 579 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
| 580 | |
Florin Chiculita | d90d506 | 2019-04-22 11:57:47 +0300 | [diff] [blame] | 581 | #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) |
| 582 | /* invert AQR107 IRQ pins polarity */ |
| 583 | out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); |
| 584 | #endif |
| 585 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 586 | #ifdef CONFIG_FSL_CAAM |
| 587 | sec_init(); |
| 588 | #endif |
| 589 | |
| 590 | return 0; |
| 591 | } |
| 592 | |
| 593 | void detail_board_ddr_info(void) |
| 594 | { |
| 595 | int i; |
| 596 | u64 ddr_size = 0; |
| 597 | |
| 598 | puts("\nDDR "); |
| 599 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) |
| 600 | ddr_size += gd->bd->bi_dram[i].size; |
| 601 | print_size(ddr_size, ""); |
| 602 | print_ddr_info(0); |
| 603 | } |
| 604 | |
Alex Marginean | b4f8023 | 2020-01-11 01:05:36 +0200 | [diff] [blame] | 605 | #ifdef CONFIG_MISC_INIT_R |
| 606 | int misc_init_r(void) |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 607 | { |
Pankaj Bansal | 338baa3 | 2019-02-08 10:29:58 +0000 | [diff] [blame] | 608 | config_board_mux(); |
| 609 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 610 | return 0; |
| 611 | } |
| 612 | #endif |
| 613 | |
| 614 | #ifdef CONFIG_FSL_MC_ENET |
| 615 | extern int fdt_fixup_board_phy(void *fdt); |
| 616 | |
| 617 | void fdt_fixup_board_enet(void *fdt) |
| 618 | { |
| 619 | int offset; |
| 620 | |
| 621 | offset = fdt_path_offset(fdt, "/soc/fsl-mc"); |
| 622 | |
| 623 | if (offset < 0) |
| 624 | offset = fdt_path_offset(fdt, "/fsl-mc"); |
| 625 | |
| 626 | if (offset < 0) { |
| 627 | printf("%s: fsl-mc node not found in device tree (error %d)\n", |
| 628 | __func__, offset); |
| 629 | return; |
| 630 | } |
| 631 | |
Mian Yousaf Kaukab | c387c01 | 2019-05-23 10:57:33 +0200 | [diff] [blame] | 632 | if (get_mc_boot_status() == 0 && |
| 633 | (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 634 | fdt_status_okay(fdt, offset); |
| 635 | fdt_fixup_board_phy(fdt); |
| 636 | } else { |
| 637 | fdt_status_fail(fdt, offset); |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | void board_quiesce_devices(void) |
| 642 | { |
| 643 | fsl_mc_ldpaa_exit(gd->bd); |
| 644 | } |
| 645 | #endif |
| 646 | |
Wasim Khan | 392d5fa | 2020-02-14 11:04:36 +0530 | [diff] [blame] | 647 | #ifdef CONFIG_GIC_V3_ITS |
| 648 | void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base) |
| 649 | { |
| 650 | u32 phandle; |
| 651 | int err; |
| 652 | struct fdt_memory gic_lpi; |
| 653 | |
| 654 | gic_lpi.start = gic_lpi_base; |
| 655 | gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1; |
| 656 | err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle); |
| 657 | if (err < 0) |
| 658 | debug("failed to add reserved memory: %d\n", err); |
| 659 | } |
| 660 | #endif |
| 661 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 662 | #ifdef CONFIG_OF_BOARD_SETUP |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 663 | int ft_board_setup(void *blob, bd_t *bd) |
| 664 | { |
| 665 | int i; |
Meenakshi Aggarwal | d67ae48 | 2019-05-23 15:13:43 +0530 | [diff] [blame] | 666 | u16 mc_memory_bank = 0; |
| 667 | |
| 668 | u64 *base; |
| 669 | u64 *size; |
| 670 | u64 mc_memory_base = 0; |
| 671 | u64 mc_memory_size = 0; |
| 672 | u16 total_memory_banks; |
Wasim Khan | 2f7e016 | 2020-02-14 11:04:34 +0530 | [diff] [blame] | 673 | u64 gic_lpi_base; |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 674 | |
| 675 | ft_cpu_setup(blob, bd); |
| 676 | |
Meenakshi Aggarwal | d67ae48 | 2019-05-23 15:13:43 +0530 | [diff] [blame] | 677 | fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); |
| 678 | |
| 679 | if (mc_memory_base != 0) |
| 680 | mc_memory_bank++; |
| 681 | |
| 682 | total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; |
| 683 | |
| 684 | base = calloc(total_memory_banks, sizeof(u64)); |
| 685 | size = calloc(total_memory_banks, sizeof(u64)); |
| 686 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 687 | /* fixup DT for the three GPP DDR banks */ |
| 688 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 689 | base[i] = gd->bd->bi_dram[i].start; |
| 690 | size[i] = gd->bd->bi_dram[i].size; |
| 691 | } |
| 692 | |
Wasim Khan | 2f7e016 | 2020-02-14 11:04:34 +0530 | [diff] [blame] | 693 | #ifdef CONFIG_GIC_V3_ITS |
| 694 | gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; |
| 695 | gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); |
Wasim Khan | 392d5fa | 2020-02-14 11:04:36 +0530 | [diff] [blame] | 696 | fdt_fixup_gic_lpi_memory(blob, gic_lpi_base); |
Wasim Khan | 2f7e016 | 2020-02-14 11:04:34 +0530 | [diff] [blame] | 697 | #endif |
| 698 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 699 | #ifdef CONFIG_RESV_RAM |
| 700 | /* reduce size if reserved memory is within this bank */ |
| 701 | if (gd->arch.resv_ram >= base[0] && |
| 702 | gd->arch.resv_ram < base[0] + size[0]) |
| 703 | size[0] = gd->arch.resv_ram - base[0]; |
| 704 | else if (gd->arch.resv_ram >= base[1] && |
| 705 | gd->arch.resv_ram < base[1] + size[1]) |
| 706 | size[1] = gd->arch.resv_ram - base[1]; |
| 707 | else if (gd->arch.resv_ram >= base[2] && |
| 708 | gd->arch.resv_ram < base[2] + size[2]) |
| 709 | size[2] = gd->arch.resv_ram - base[2]; |
| 710 | #endif |
| 711 | |
Meenakshi Aggarwal | d67ae48 | 2019-05-23 15:13:43 +0530 | [diff] [blame] | 712 | if (mc_memory_base != 0) { |
| 713 | for (i = 0; i <= total_memory_banks; i++) { |
| 714 | if (base[i] == 0 && size[i] == 0) { |
| 715 | base[i] = mc_memory_base; |
| 716 | size[i] = mc_memory_size; |
| 717 | break; |
| 718 | } |
| 719 | } |
| 720 | } |
| 721 | |
| 722 | fdt_fixup_memory_banks(blob, base, size, total_memory_banks); |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 723 | |
| 724 | #ifdef CONFIG_USB |
| 725 | fsl_fdt_fixup_dr_usb(blob, bd); |
| 726 | #endif |
| 727 | |
| 728 | #ifdef CONFIG_FSL_MC_ENET |
| 729 | fdt_fsl_mc_fixup_iommu_map_entry(blob); |
| 730 | fdt_fixup_board_enet(blob); |
| 731 | #endif |
Laurentiu Tudor | 7085d07 | 2019-10-18 09:01:55 +0000 | [diff] [blame] | 732 | fdt_fixup_icid(blob); |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 733 | |
| 734 | return 0; |
| 735 | } |
| 736 | #endif |
| 737 | |
| 738 | void qixis_dump_switch(void) |
| 739 | { |
| 740 | int i, nr_of_cfgsw; |
| 741 | |
| 742 | QIXIS_WRITE(cms[0], 0x00); |
| 743 | nr_of_cfgsw = QIXIS_READ(cms[1]); |
| 744 | |
| 745 | puts("DIP switch settings dump:\n"); |
| 746 | for (i = 1; i <= nr_of_cfgsw; i++) { |
| 747 | QIXIS_WRITE(cms[0], i); |
| 748 | printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); |
| 749 | } |
| 750 | } |