armv8: lx2160ardb : Add support for LX2160ARDB platform
LX2160ARDB is an evaluation board that supports LX2160A
family SoCs. This patch add base support for this board.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han
and re-arrange defconfig]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
new file mode 100644
index 0000000..a62222e
--- /dev/null
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <efi_loader.h>
+#include <asm/arch/mmu.h>
+#include <hwconfig.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include "../common/qixis.h"
+#include "../common/vid.h"
+#include <fsl_immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl01x_serial_platdata serial0 = {
+#if CONFIG_CONS_INDEX == 0
+ .base = CONFIG_SYS_SERIAL0,
+#elif CONFIG_CONS_INDEX == 1
+ .base = CONFIG_SYS_SERIAL1,
+#else
+#error "Unsupported console index value."
+#endif
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial0) = {
+ .name = "serial_pl01x",
+ .platdata = &serial0,
+};
+
+static struct pl01x_serial_platdata serial1 = {
+ .base = CONFIG_SYS_SERIAL1,
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial1) = {
+ .name = "serial_pl01x",
+ .platdata = &serial1,
+};
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void uart_get_clock(void)
+{
+ serial0.clock = get_serial_clock();
+ serial1.clock = get_serial_clock();
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
+ /* get required clock for UART IP */
+ uart_get_clock();
+
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+ /* Enable both esdhc DT nodes for LX2160ARDB */
+ do_fixup_by_compat(blob, compat, "status", "okay",
+ sizeof("okay"), 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_VID)
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+#endif
+
+int checkboard(void)
+{
+ enum boot_src src = get_boot_src();
+ char buf[64];
+ u8 sw;
+
+ cpu_name(buf);
+ printf("Board: %s-RDB, ", buf);
+
+ sw = QIXIS_READ(arch);
+ printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
+
+ if (src == BOOT_SOURCE_SD_MMC) {
+ puts("SD\n");
+ } else {
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
+ switch (sw) {
+ case 0:
+ case 4:
+ puts("FlexSPI DEV#0\n");
+ break;
+ case 1:
+ puts("FlexSPI DEV#1\n");
+ break;
+ case 2:
+ case 3:
+ puts("FlexSPI EMU\n");
+ break;
+ default:
+ printf("invalid setting, xmap: %d\n", sw);
+ break;
+ }
+ }
+ printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+
+ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
+ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return 100000000;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return 100000000;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ int i;
+ u64 ddr_size = 0;
+
+ puts("\nDDR ");
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ ddr_size += gd->bd->bi_dram[i].size;
+ print_size(ddr_size, "");
+ print_ddr_info(0);
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+extern int fdt_fixup_board_phy(void *fdt);
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0) {
+ printf("%s: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {
+ fdt_status_okay(fdt, offset);
+ fdt_fixup_board_phy(fdt);
+ } else {
+ fdt_status_fail(fdt, offset);
+ }
+}
+
+void board_quiesce_devices(void)
+{
+ fsl_mc_ldpaa_exit(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int i;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the three GPP DDR banks */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ }
+
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+ else if (gd->arch.resv_ram >= base[2] &&
+ gd->arch.resv_ram < base[2] + size[2])
+ size[2] = gd->arch.resv_ram - base[2];
+#endif
+
+ fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+
+#ifdef CONFIG_USB
+ fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+ int i, nr_of_cfgsw;
+
+ QIXIS_WRITE(cms[0], 0x00);
+ nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+ puts("DIP switch settings dump:\n");
+ for (i = 1; i <= nr_of_cfgsw; i++) {
+ QIXIS_WRITE(cms[0], i);
+ printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+ }
+}