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git01.mediatek.com / filogic / uboot / ef64c0b4a2bbc877c6a671cb25ef8fec55c53c8e / . / arch / arm / mach-tegra / tegra210 / clock.c
blob: b240860f08cf30e8c74dbdcf0f16dd701dc1978b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]2/*
3 * (C) Copyright 2013-2015
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]5 */
6
7/* Tegra210 Clock control functions */
8
9#include <common.h>
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]10#include <errno.h>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/sysctr.h>
14#include <asm/arch/tegra.h>
15#include <asm/arch-tegra/clk_rst.h>
16#include <asm/arch-tegra/timer.h>
17#include <div64.h>
18#include <fdtdec.h>
19
20/*
21 * Clock types that we can use as a source. The Tegra210 has muxes for the
22 * peripheral clocks, and in most cases there are four options for the clock
23 * source. This gives us a clock 'type' and exploits what commonality exists
24 * in the device.
25 *
26 * Letters are obvious, except for T which means CLK_M, and S which means the
27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
28 * datasheet) and PLL_M are different things. The former is the basic
29 * clock supplied to the SOC from an external oscillator. The latter is the
30 * memory clock PLL.
31 *
32 * See definitions in clock_id in the header file.
33 */
34enum clock_type_id {
35 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
36 CLOCK_TYPE_MCPA, /* and so on */
37 CLOCK_TYPE_MCPT,
38 CLOCK_TYPE_PCM,
39 CLOCK_TYPE_PCMT,
40 CLOCK_TYPE_PDCT,
41 CLOCK_TYPE_ACPT,
42 CLOCK_TYPE_ASPTE,
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]43 CLOCK_TYPE_PDD2T,
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]44 CLOCK_TYPE_PCST,
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]45 CLOCK_TYPE_DP,
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]46
47 CLOCK_TYPE_PC2CC3M,
48 CLOCK_TYPE_PC2CC3S_T,
49 CLOCK_TYPE_PC2CC3M_T,
50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
51 CLOCK_TYPE_MC2CC3P_A,
52 CLOCK_TYPE_M,
53 CLOCK_TYPE_MCPTM2C2C3,
54 CLOCK_TYPE_PC2CC3T_S,
55 CLOCK_TYPE_AC2CC3P_TS2,
56 CLOCK_TYPE_PC01C00_C42C41TC40,
57
58 CLOCK_TYPE_COUNT,
59 CLOCK_TYPE_NONE = -1, /* invalid clock type */
60};
61
62enum {
63 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
64};
65
66/*
67 * Clock source mux for each clock type. This just converts our enum into
68 * a list of mux sources for use by the code.
69 *
70 * Note:
71 * The extra column in each clock source array is used to store the mask
72 * bits in its register for the source.
73 */
74#define CLK(x) CLOCK_ID_ ## x
75static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
76 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
78 MASK_BITS_31_30},
79 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
81 MASK_BITS_31_30},
82 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
84 MASK_BITS_31_30},
85 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
87 MASK_BITS_31_30},
88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
90 MASK_BITS_31_30},
91 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
92 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
93 MASK_BITS_31_30},
94 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
96 MASK_BITS_31_30},
97 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
98 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
99 MASK_BITS_31_29},
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]100 { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
101 CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]102 MASK_BITS_31_29},
103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
104 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
105 MASK_BITS_31_28},
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]106 /* CLOCK_TYPE_DP */
107 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
108 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
109 MASK_BITS_31_28},
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]110
111 /* Additional clock types on Tegra114+ */
112 /* CLOCK_TYPE_PC2CC3M */
113 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
114 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
115 MASK_BITS_31_29},
116 /* CLOCK_TYPE_PC2CC3S_T */
117 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
118 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
119 MASK_BITS_31_29},
120 /* CLOCK_TYPE_PC2CC3M_T */
121 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
122 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
123 MASK_BITS_31_29},
124 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
125 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
126 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
127 MASK_BITS_31_29},
128 /* CLOCK_TYPE_MC2CC3P_A */
129 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
130 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
131 MASK_BITS_31_29},
132 /* CLOCK_TYPE_M */
133 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
134 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
135 MASK_BITS_31_30},
136 /* CLOCK_TYPE_MCPTM2C2C3 */
137 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
138 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
139 MASK_BITS_31_29},
140 /* CLOCK_TYPE_PC2CC3T_S */
141 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
142 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
143 MASK_BITS_31_29},
144 /* CLOCK_TYPE_AC2CC3P_TS2 */
145 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
146 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
147 MASK_BITS_31_29},
148 /* CLOCK_TYPE_PC01C00_C42C41TC40 */
149 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
150 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
151 MASK_BITS_31_29},
152};
153
154/*
155 * Clock type for each peripheral clock source. We put the name in each
156 * record just so it is easy to match things up
157 */
158#define TYPE(name, type) type
159static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
160 /* 0x00 */
161 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
162 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
163 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
164 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
165 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
166 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
167 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
168 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
169
170 /* 0x08 */
171 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
172 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
173 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
174 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
175 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
176 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]177 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
178 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]179
180 /* 0x10 */
181 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
182 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
183 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
184 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
185 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
186 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
187 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
188 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
189
190 /* 0x18 */
191 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
192 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
193 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
194 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
195 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
196 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
197 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
198 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
199
200 /* 0x20 */
201 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
202 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
203 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
204 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
205 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
206 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
207 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
208 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
209
210 /* 0x28 */
211 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
212 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
214 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
215 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
216 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
217 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
218 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
219
220 /* 0x30 */
221 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
222 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
223 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
224 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
225 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
226 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
227 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
228 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
229
230 /* 0x38 */
231 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
232 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
233 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
234 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
235 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
236 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
237 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
238 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
239
240 /* 0x40 */
241 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
242 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
243 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
244 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
245 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
246 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
247 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
248 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
249
250 /* 0x48 */
251 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
252 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
253 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
254 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
255 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
256 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
257 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
258 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
259
260 /* 0x50 */
261 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
262 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
263 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
264 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
265 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
266 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
267 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
268 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
269
270 /* 0x58 */
271 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
272 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
273 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
274 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
275 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
276 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
277 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
278 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
279
280 /* 0x60 */
281 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
282 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
283 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
284 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
285 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
286 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
287 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
288 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
289
290 /* 0x68 */
291 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
292 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
293 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
294 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
295 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
296 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
297 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
298 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
299
300 /* 0x70 */
301 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
302 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
303 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
304 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
305 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
306 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
307 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
308 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
309
310 /* 0x78 */
311 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
312 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
313 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
314 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
315 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
316 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
317 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
318 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
319
320 /* 0x80 */
321 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
322 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
323 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
324 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
325 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
326 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
327 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
328 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
329
330 /* 0x88 */
331 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
332 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
333 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
334 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
335 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
336 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE),
337 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
338 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
339
340 /* 0x90 */
341 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
342 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
343};
344
345/*
346 * This array translates a periph_id to a periphc_internal_id
347 *
348 * Not present/matched up:
349 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
350 * SPDIF - which is both 0x08 and 0x0c
351 *
352 */
353#define NONE(name) (-1)
354#define OFFSET(name, value) PERIPHC_ ## name
355#define INTERNAL_ID(id) (id & 0x000000ff)
356static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
357 /* Low word: 31:0 */
358 NONE(CPU),
359 NONE(COP),
360 NONE(TRIGSYS),
361 NONE(ISPB),
362 NONE(RESERVED4),
363 NONE(TMR),
364 PERIPHC_UART1,
365 PERIPHC_UART2, /* and vfir 0x68 */
366
367 /* 8 */
368 NONE(GPIO),
369 PERIPHC_SDMMC2,
370 PERIPHC_SPDIF_IN,
371 PERIPHC_I2S2,
372 PERIPHC_I2C1,
373 NONE(RESERVED13),
374 PERIPHC_SDMMC1,
375 PERIPHC_SDMMC4,
376
377 /* 16 */
378 NONE(TCW),
379 PERIPHC_PWM,
380 PERIPHC_I2S3,
381 NONE(RESERVED19),
382 PERIPHC_VI,
383 NONE(RESERVED21),
384 NONE(USBD),
385 NONE(ISP),
386
387 /* 24 */
388 NONE(RESERVED24),
389 NONE(RESERVED25),
390 PERIPHC_DISP2,
391 PERIPHC_DISP1,
392 PERIPHC_HOST1X,
393 NONE(VCP),
394 PERIPHC_I2S1,
395 NONE(CACHE2),
396
397 /* Middle word: 63:32 */
398 NONE(MEM),
399 NONE(AHBDMA),
400 NONE(APBDMA),
401 NONE(RESERVED35),
402 NONE(RESERVED36),
403 NONE(STAT_MON),
404 NONE(RESERVED38),
405 NONE(FUSE),
406
407 /* 40 */
408 NONE(KFUSE),
409 PERIPHC_SBC1, /* SBCx = SPIx */
410 PERIPHC_NOR,
411 NONE(RESERVED43),
412 PERIPHC_SBC2,
413 NONE(XIO),
414 PERIPHC_SBC3,
415 PERIPHC_I2C5,
416
417 /* 48 */
418 NONE(DSI),
419 NONE(RESERVED49),
420 PERIPHC_HSI,
421 NONE(RESERVED51),
422 NONE(CSI),
423 NONE(RESERVED53),
424 PERIPHC_I2C2,
425 PERIPHC_UART3,
426
427 /* 56 */
428 NONE(MIPI_CAL),
429 PERIPHC_EMC,
430 NONE(USB2),
431 NONE(USB3),
432 NONE(RESERVED60),
433 PERIPHC_VDE,
434 NONE(BSEA),
435 NONE(BSEV),
436
437 /* Upper word 95:64 */
438 NONE(RESERVED64),
439 PERIPHC_UART4,
440 PERIPHC_UART5,
441 PERIPHC_I2C3,
442 PERIPHC_SBC4,
443 PERIPHC_SDMMC3,
444 NONE(PCIE),
445 PERIPHC_OWR,
446
447 /* 72 */
448 NONE(AFI),
449 PERIPHC_CSITE,
450 NONE(PCIEXCLK),
451 NONE(AVPUCQ),
452 NONE(LA),
453 NONE(TRACECLKIN),
454 NONE(SOC_THERM),
455 NONE(DTV),
456
457 /* 80 */
458 NONE(RESERVED80),
459 PERIPHC_I2CSLOW,
460 NONE(DSIB),
461 PERIPHC_TSEC,
462 NONE(RESERVED84),
463 NONE(RESERVED85),
464 NONE(RESERVED86),
465 NONE(EMUCIF),
466
467 /* 88 */
468 NONE(RESERVED88),
469 NONE(XUSB_HOST),
470 NONE(RESERVED90),
471 PERIPHC_MSENC,
472 NONE(RESERVED92),
473 NONE(RESERVED93),
474 NONE(RESERVED94),
475 NONE(XUSB_DEV),
476
477 /* V word: 31:0 */
478 NONE(CPUG),
479 NONE(CPULP),
480 NONE(V_RESERVED2),
481 PERIPHC_MSELECT,
482 NONE(V_RESERVED4),
483 PERIPHC_I2S4,
484 PERIPHC_I2S5,
485 PERIPHC_I2C4,
486
487 /* 104 */
488 PERIPHC_SBC5,
489 PERIPHC_SBC6,
490 PERIPHC_AUDIO,
491 NONE(APBIF),
492 NONE(V_RESERVED12),
493 NONE(V_RESERVED13),
494 NONE(V_RESERVED14),
495 PERIPHC_HDA2CODEC2X,
496
497 /* 112 */
498 NONE(ATOMICS),
499 NONE(V_RESERVED17),
500 NONE(V_RESERVED18),
501 NONE(V_RESERVED19),
502 NONE(V_RESERVED20),
503 NONE(V_RESERVED21),
504 NONE(V_RESERVED22),
505 PERIPHC_ACTMON,
506
507 /* 120 */
508 NONE(EXTPERIPH1),
509 NONE(EXTPERIPH2),
510 NONE(EXTPERIPH3),
511 NONE(OOB),
512 PERIPHC_SATA,
513 PERIPHC_HDA,
514 NONE(TZRAM),
515 NONE(SE),
516
517 /* W word: 31:0 */
518 NONE(HDA2HDMICODEC),
519 NONE(SATACOLD),
520 NONE(W_RESERVED2),
521 NONE(W_RESERVED3),
522 NONE(W_RESERVED4),
523 NONE(W_RESERVED5),
524 NONE(W_RESERVED6),
525 NONE(W_RESERVED7),
526
527 /* 136 */
528 NONE(CEC),
529 NONE(W_RESERVED9),
530 NONE(W_RESERVED10),
531 NONE(W_RESERVED11),
532 NONE(W_RESERVED12),
533 NONE(W_RESERVED13),
534 NONE(XUSB_PADCTL),
535 NONE(W_RESERVED15),
536
537 /* 144 */
538 NONE(W_RESERVED16),
539 NONE(W_RESERVED17),
540 NONE(W_RESERVED18),
541 NONE(W_RESERVED19),
542 NONE(W_RESERVED20),
543 NONE(ENTROPY),
544 NONE(DDS),
545 NONE(W_RESERVED23),
546
547 /* 152 */
548 NONE(W_RESERVED24),
549 NONE(W_RESERVED25),
550 NONE(W_RESERVED26),
551 NONE(DVFS),
552 NONE(XUSB_SS),
553 NONE(W_RESERVED29),
554 NONE(W_RESERVED30),
555 NONE(W_RESERVED31),
556
557 /* X word: 31:0 */
558 NONE(SPARE),
559 NONE(X_RESERVED1),
560 NONE(X_RESERVED2),
561 NONE(X_RESERVED3),
562 NONE(CAM_MCLK),
563 NONE(CAM_MCLK2),
564 PERIPHC_I2C6,
565 NONE(X_RESERVED7),
566
567 /* 168 */
568 NONE(X_RESERVED8),
569 NONE(X_RESERVED9),
570 NONE(X_RESERVED10),
571 NONE(VIM2_CLK),
572 NONE(X_RESERVED12),
573 NONE(X_RESERVED13),
574 NONE(EMC_DLL),
575 NONE(X_RESERVED15),
576
577 /* 176 */
578 NONE(X_RESERVED16),
579 NONE(CLK72MHZ),
580 NONE(VIC),
581 NONE(X_RESERVED19),
582 NONE(X_RESERVED20),
583 NONE(DPAUX),
584 NONE(SOR0),
585 NONE(X_RESERVED23),
586
587 /* 184 */
588 NONE(GPU),
589 NONE(X_RESERVED25),
590 NONE(X_RESERVED26),
591 NONE(X_RESERVED27),
592 NONE(X_RESERVED28),
593 NONE(X_RESERVED29),
594 NONE(X_RESERVED30),
595 NONE(X_RESERVED31),
596
597 /* Y: 192 (192 - 223) */
598 NONE(Y_RESERVED0),
599 PERIPHC_SDMMC_LEGACY_TM,
600 PERIPHC_NVDEC,
601 PERIPHC_NVJPG,
602 NONE(Y_RESERVED4),
603 PERIPHC_DMIC3, /* 197 */
604 PERIPHC_APE, /* 198 */
605 NONE(Y_RESERVED7),
606
607 /* 200 */
608 NONE(Y_RESERVED8),
609 NONE(Y_RESERVED9),
610 NONE(Y_RESERVED10),
611 NONE(Y_RESERVED11),
612 NONE(Y_RESERVED12),
613 NONE(Y_RESERVED13),
614 NONE(Y_RESERVED14),
615 NONE(Y_RESERVED15),
616
617 /* 208 */
618 PERIPHC_VI_I2C, /* 208 */
619 NONE(Y_RESERVED17),
620 NONE(Y_RESERVED18),
621 PERIPHC_QSPI, /* 211 */
622 NONE(Y_RESERVED20),
623 NONE(Y_RESERVED21),
624 NONE(Y_RESERVED22),
625 NONE(Y_RESERVED23),
626
627 /* 216 */
628 NONE(Y_RESERVED24),
629 NONE(Y_RESERVED25),
630 NONE(Y_RESERVED26),
631 PERIPHC_NVENC, /* 219 */
632 NONE(Y_RESERVED28),
633 NONE(Y_RESERVED29),
634 NONE(Y_RESERVED30),
635 NONE(Y_RESERVED31),
636};
637
638/*
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]639 * PLL divider shift/mask tables for all PLL IDs.
640 */
641struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
642 /*
643 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.)
644 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.)
645 */
646 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
647 .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */
648 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
649 .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
650 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
651 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */
652 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
653 .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */
654 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
655 .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */
656 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
657 .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */
658 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
659 .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */
660 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
661 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
662 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
663 .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]664 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
665 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]666};
667
668/*
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]669 * Get the oscillator frequency, from the corresponding hardware configuration
670 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
671 * to the old T20 freqs. Support for the higher oscillators is TBD.
672 */
673enum clock_osc_freq clock_get_osc_freq(void)
674{
675 struct clk_rst_ctlr *clkrst =
676 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
677 u32 reg;
678
679 reg = readl(&clkrst->crc_osc_ctrl);
680 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
681 /*
682 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
683 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
684 */
685 if (reg == 5) {
686 debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
Tom Warren27bce712015-06-22 13:03:44 -0700[diff] [blame]687 /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
688 return 4;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]689 }
690
691 /*
692 * Map to most common (T20) freqs (except 38.4, handled above):
693 * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
694 */
695 return reg >> 2;
696}
697
698/* Returns a pointer to the clock source register for a peripheral */
699u32 *get_periph_source_reg(enum periph_id periph_id)
700{
701 struct clk_rst_ctlr *clkrst =
702 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
703 enum periphc_internal_id internal_id;
704
705 /* Coresight is a special case */
706 if (periph_id == PERIPH_ID_CSI)
707 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
708
709 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
710 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
711 assert(internal_id != -1);
712
713 if (internal_id < PERIPHC_VW_FIRST)
714 /* L, H, U */
715 return &clkrst->crc_clk_src[internal_id];
716
717 if (internal_id < PERIPHC_X_FIRST) {
718 /* VW */
719 internal_id -= PERIPHC_VW_FIRST;
720 return &clkrst->crc_clk_src_vw[internal_id];
721 }
722
723 if (internal_id < PERIPHC_Y_FIRST) {
724 /* X */
725 internal_id -= PERIPHC_X_FIRST;
726 return &clkrst->crc_clk_src_x[internal_id];
727 }
728
729 /* Y */
730 internal_id -= PERIPHC_Y_FIRST;
731 return &clkrst->crc_clk_src_y[internal_id];
732}
733
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]734int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
735 int *divider_bits, int *type)
736{
737 enum periphc_internal_id internal_id;
738
739 if (!clock_periph_id_isvalid(periph_id))
740 return -1;
741
742 internal_id = periph_id_to_internal_id[periph_id];
743 if (!periphc_internal_id_isvalid(internal_id))
744 return -1;
745
746 *type = clock_periph_type[internal_id];
747 if (!clock_type_id_isvalid(*type))
748 return -1;
749
750 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
751
752 if (*type == CLOCK_TYPE_PC2CC3M_T16)
753 *divider_bits = 16;
754 else
755 *divider_bits = 8;
756
757 return 0;
758}
759
760enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
761{
762 enum periphc_internal_id internal_id;
763 int type;
764
765 if (!clock_periph_id_isvalid(periph_id))
766 return CLOCK_ID_NONE;
767
768 internal_id = periph_id_to_internal_id[periph_id];
769 if (!periphc_internal_id_isvalid(internal_id))
770 return CLOCK_ID_NONE;
771
772 type = clock_periph_type[internal_id];
773 if (!clock_type_id_isvalid(type))
774 return CLOCK_ID_NONE;
775
776 return clock_source[type][source];
777}
778
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]779/**
780 * Given a peripheral ID and the required source clock, this returns which
781 * value should be programmed into the source mux for that peripheral.
782 *
783 * There is special code here to handle the one source type with 5 sources.
784 *
785 * @param periph_id peripheral to start
786 * @param source PLL id of required parent clock
787 * @param mux_bits Set to number of bits in mux register: 2 or 4
788 * @param divider_bits Set to number of divider bits (8 or 16)
789 * @return mux value (0-4, or -1 if not found)
790 */
791int get_periph_clock_source(enum periph_id periph_id,
792 enum clock_id parent, int *mux_bits, int *divider_bits)
793{
794 enum clock_type_id type;
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]795 int mux, err;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]796
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]797 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
798 assert(!err);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]799
800 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
801 if (clock_source[type][mux] == parent)
802 return mux;
803
804 /* if we get here, either us or the caller has made a mistake */
805 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
806 parent);
807 return -1;
808}
809
810void clock_set_enable(enum periph_id periph_id, int enable)
811{
812 struct clk_rst_ctlr *clkrst =
813 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
814 u32 *clk;
815 u32 reg;
816
817 /* Enable/disable the clock to this peripheral */
818 assert(clock_periph_id_isvalid(periph_id));
819 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
820 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
821 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
822 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
823 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
824 clk = &clkrst->crc_clk_out_enb_x;
825 else
826 clk = &clkrst->crc_clk_out_enb_y;
827
828 reg = readl(clk);
829 if (enable)
830 reg |= PERIPH_MASK(periph_id);
831 else
832 reg &= ~PERIPH_MASK(periph_id);
833 writel(reg, clk);
834}
835
836void reset_set_enable(enum periph_id periph_id, int enable)
837{
838 struct clk_rst_ctlr *clkrst =
839 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
840 u32 *reset;
841 u32 reg;
842
843 /* Enable/disable reset to the peripheral */
844 assert(clock_periph_id_isvalid(periph_id));
845 if (periph_id < PERIPH_ID_VW_FIRST)
846 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
847 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
848 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
849 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
850 reset = &clkrst->crc_rst_devices_x;
851 else
852 reset = &clkrst->crc_rst_devices_y;
853
854 reg = readl(reset);
855 if (enable)
856 reg |= PERIPH_MASK(periph_id);
857 else
858 reg &= ~PERIPH_MASK(periph_id);
859 writel(reg, reset);
860}
861
862#ifdef CONFIG_OF_CONTROL
863/*
864 * Convert a device tree clock ID to our peripheral ID. They are mostly
865 * the same but we are very cautious so we check that a valid clock ID is
866 * provided.
867 *
868 * @param clk_id Clock ID according to tegra210 device tree binding
869 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
870 */
871enum periph_id clk_id_to_periph_id(int clk_id)
872{
873 if (clk_id > PERIPH_ID_COUNT)
874 return PERIPH_ID_NONE;
875
876 switch (clk_id) {
877 case PERIPH_ID_RESERVED4:
878 case PERIPH_ID_RESERVED25:
879 case PERIPH_ID_RESERVED35:
880 case PERIPH_ID_RESERVED36:
881 case PERIPH_ID_RESERVED38:
882 case PERIPH_ID_RESERVED43:
883 case PERIPH_ID_RESERVED49:
884 case PERIPH_ID_RESERVED53:
885 case PERIPH_ID_RESERVED64:
886 case PERIPH_ID_RESERVED84:
887 case PERIPH_ID_RESERVED85:
888 case PERIPH_ID_RESERVED86:
889 case PERIPH_ID_RESERVED88:
890 case PERIPH_ID_RESERVED90:
891 case PERIPH_ID_RESERVED92:
892 case PERIPH_ID_RESERVED93:
893 case PERIPH_ID_RESERVED94:
894 case PERIPH_ID_V_RESERVED2:
895 case PERIPH_ID_V_RESERVED4:
896 case PERIPH_ID_V_RESERVED17:
897 case PERIPH_ID_V_RESERVED18:
898 case PERIPH_ID_V_RESERVED19:
899 case PERIPH_ID_V_RESERVED20:
900 case PERIPH_ID_V_RESERVED21:
901 case PERIPH_ID_V_RESERVED22:
902 case PERIPH_ID_W_RESERVED2:
903 case PERIPH_ID_W_RESERVED3:
904 case PERIPH_ID_W_RESERVED4:
905 case PERIPH_ID_W_RESERVED5:
906 case PERIPH_ID_W_RESERVED6:
907 case PERIPH_ID_W_RESERVED7:
908 case PERIPH_ID_W_RESERVED9:
909 case PERIPH_ID_W_RESERVED10:
910 case PERIPH_ID_W_RESERVED11:
911 case PERIPH_ID_W_RESERVED12:
912 case PERIPH_ID_W_RESERVED13:
913 case PERIPH_ID_W_RESERVED15:
914 case PERIPH_ID_W_RESERVED16:
915 case PERIPH_ID_W_RESERVED17:
916 case PERIPH_ID_W_RESERVED18:
917 case PERIPH_ID_W_RESERVED19:
918 case PERIPH_ID_W_RESERVED20:
919 case PERIPH_ID_W_RESERVED23:
920 case PERIPH_ID_W_RESERVED29:
921 case PERIPH_ID_W_RESERVED30:
922 case PERIPH_ID_W_RESERVED31:
923 return PERIPH_ID_NONE;
924 default:
925 return clk_id;
926 }
927}
928#endif /* CONFIG_OF_CONTROL */
929
930/*
931 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
932 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
933 */
934void tegra210_setup_pllp(void)
935{
936 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
937 u32 reg;
938
939 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
940
941 /* OUT1 */
942 /* Assert RSTN before enable */
943 reg = PLLP_OUT1_RSTN_EN;
944 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
945 /* Set divisor and reenable */
946 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
947 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
948 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
949
950 /* OUT3, 4 */
951 /* Assert RSTN before enable */
952 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
953 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
954 /* Set divisor and reenable */
955 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
956 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
957 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
958 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
959 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
960
961 /*
962 * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
963 * you can change PLLP_BASE DIVP here. Currently defaults
964 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
965 * See Table 13 in section 5.1.4 in T210 TRM for more info.
966 */
967}
968
969void clock_early_init(void)
970{
971 struct clk_rst_ctlr *clkrst =
972 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]973 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]974 u32 data;
975
976 tegra210_setup_pllp();
977
978 /*
979 * PLLC output frequency set to 600Mhz
980 * PLLD output frequency set to 925Mhz
981 */
982 switch (clock_get_osc_freq()) {
983 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
984 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
985 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
986 break;
987
988 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
989 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
990 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
991 break;
992
993 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
994 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
995 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
996 break;
997 case CLOCK_OSC_FREQ_19_2:
998 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
999 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
1000 break;
Tom Warren27bce712015-06-22 13:03:44 -0700[diff] [blame]1001 case CLOCK_OSC_FREQ_38_4:
1002 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
1003 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
1004 break;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1005 default:
1006 /*
1007 * These are not supported. It is too early to print a
1008 * message and the UART likely won't work anyway due to the
1009 * oscillator being wrong.
1010 */
1011 break;
1012 }
1013
1014 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
1015 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
1016 (1 << PLLC_IDDQ));
1017 udelay(2);
1018
1019 /*
1020 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
1021 * to pll_out[1]
1022 */
1023 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],
1024 (1 << PLLC_RESET));
1025 udelay(2);
1026
1027 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]1028 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1029 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
1030 udelay(2);
1031}
1032
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200[diff] [blame]1033unsigned int clk_m_get_rate(unsigned parent_rate)
1034{
1035 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1036 u32 value, div;
1037
1038 value = readl(&clkrst->crc_spare_reg0);
1039 div = ((value >> 2) & 0x3) + 1;
1040
1041 return parent_rate / div;
1042}
1043
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1044void arch_timer_init(void)
1045{
1046 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
1047 u32 freq, val;
1048
Thierry Reding4c3aaa72015-08-20 11:42:20 +0200[diff] [blame]1049 freq = clock_get_rate(CLOCK_ID_CLK_M);
1050 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1051
Thierry Reding4c3aaa72015-08-20 11:42:20 +0200[diff] [blame]1052 if (current_el() == 3)
1053 asm("msr cntfrq_el0, %0\n" : : "r" (freq));
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1054
1055 /* Only Tegra114+ has the System Counter regs */
1056 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
1057 writel(freq, &sysctr->cntfid0);
1058
1059 val = readl(&sysctr->cntcr);
1060 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
1061 writel(val, &sysctr->cntcr);
1062 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
1063}
1064
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1065#define PLLREFE_MISC 0x4c8
1066#define PLLREFE_MISC_LOCK BIT(27)
1067#define PLLREFE_MISC_IDDQ BIT(24)
1068
1069#define PLLREFE_BASE 0x4c4
1070#define PLLREFE_BASE_BYPASS BIT(31)
1071#define PLLREFE_BASE_ENABLE BIT(30)
1072#define PLLREFE_BASE_REF_DIS BIT(29)
1073#define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27)
1074#define PLLREFE_BASE_KVCO BIT(26)
1075#define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16)
1076#define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8)
1077#define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0)
1078
1079static int tegra_pllref_enable(void)
1080{
1081 u32 value;
1082 unsigned long start;
1083
1084 /*
1085 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1086 * Recovery Mode or Boot from USB", sub-section "PLLREFE".
1087 */
1088
1089 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1090 value &= ~PLLREFE_MISC_IDDQ;
1091 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1092
1093 udelay(5);
1094
1095 value = PLLREFE_BASE_ENABLE |
1096 PLLREFE_BASE_KCP(0) |
1097 PLLREFE_BASE_DIVP(0) |
1098 PLLREFE_BASE_DIVN(0x41) |
1099 PLLREFE_BASE_DIVM(4);
1100 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE);
1101
1102 debug("waiting for pllrefe lock\n");
1103 start = get_timer(0);
1104 while (get_timer(start) < 250) {
1105 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1106 if (value & PLLREFE_MISC_LOCK)
1107 break;
1108 }
1109 if (!(value & PLLREFE_MISC_LOCK)) {
1110 debug(" timeout\n");
1111 return -ETIMEDOUT;
1112 }
1113 debug(" done\n");
1114
1115 return 0;
1116}
1117
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1118#define PLLE_SS_CNTL 0x68
1119#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
1120#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
1121#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
1122#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
1123#define PLLE_SS_CNTL_SSCBYP (1 << 12)
1124#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
1125#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
1126#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
1127
1128#define PLLE_BASE 0x0e8
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1129#define PLLE_BASE_ENABLE (1 << 31)
1130#define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1131#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
1132#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
1133
1134#define PLLE_MISC 0x0ec
1135#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1136#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
1137#define PLLE_MISC_LOCK (1 << 11)
Stephen Warrenb6409f22016-03-22 09:45:36 -0600[diff] [blame]1138#define PLLE_PTS (1 << 8)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1139#define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1140#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1141#define PLLE_MISC_KVCO (1 << 0)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1142
1143#define PLLE_AUX 0x48c
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1144#define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
1145#define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1146#define PLLE_AUX_SEQ_ENABLE (1 << 24)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1147#define PLLE_AUX_SS_SWCTL (1 << 6)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1148#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1149#define PLLE_AUX_USE_LOCKDET (1 << 3)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1150
1151int tegra_plle_enable(void)
1152{
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1153 u32 value;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1154 unsigned long start;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1155
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1156 /* PLLREF feeds PLLE */
1157 tegra_pllref_enable();
1158
1159 /*
1160 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1161 * Recovery Mode or Boot from USB", sub-section "PLLEs".
1162 */
1163
1164 /* 1. Select XTAL as the source */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1165
1166 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1167 value &= ~PLLE_AUX_REF_SEL_PLLREFE;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1168 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
1169
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1170 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1171 value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1172 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
1173
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1174 /* 2. Wait 5 us */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1175 udelay(5);
1176
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1177 /*
1178 * 3. Program the following registers to generate a low jitter 100MHz
1179 * clock.
1180 */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1181
1182 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1183 value &= ~PLLE_BASE_PLDIV_CML(0x1f);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1184 value &= ~PLLE_BASE_NDIV(0xff);
1185 value &= ~PLLE_BASE_MDIV(0xff);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1186 value |= PLLE_BASE_PLDIV_CML(0xe);
1187 value |= PLLE_BASE_NDIV(0x7d);
1188 value |= PLLE_BASE_MDIV(2);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1189 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1190
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1191 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
Stephen Warrenb6409f22016-03-22 09:45:36 -0600[diff] [blame]1192 value |= PLLE_PTS;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1193 value &= ~PLLE_MISC_KCP(3);
1194 value &= ~PLLE_MISC_VREG_CTRL(3);
1195 value &= ~PLLE_MISC_KVCO;
1196 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1197
1198 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1199 value |= PLLE_BASE_ENABLE;
1200 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1201
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1202 /* 4. Wait for LOCK */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1203
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1204 debug("waiting for plle lock\n");
1205 start = get_timer(0);
1206 while (get_timer(start) < 250) {
1207 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1208 if (value & PLLE_MISC_LOCK)
1209 break;
1210 }
1211 if (!(value & PLLE_MISC_LOCK)) {
1212 debug(" timeout\n");
1213 return -ETIMEDOUT;
1214 }
1215 debug(" done\n");
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1216
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1217 /* 5. Enable SSA */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1218
1219 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1220 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1221 value |= PLLE_SS_CNTL_SSCINC(1);
1222 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1223 value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
1224 value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
1225 value |= PLLE_SS_CNTL_SSCMAX(0x21);
1226 value &= ~PLLE_SS_CNTL_SSCINVERT;
1227 value &= ~PLLE_SS_CNTL_SSCCENTER;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1228 value &= ~PLLE_SS_CNTL_BYPASS_SS;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1229 value &= ~PLLE_SS_CNTL_SSCBYP;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1230 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1231
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1232 /* 6. Wait 300 ns */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1233
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1234 udelay(1);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1235 value &= ~PLLE_SS_CNTL_INTERP_RESET;
1236 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1237
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1238 /* 7. Enable HW power sequencer for PLLE */
1239
1240 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1241 value &= ~PLLE_MISC_IDDQ_SWCTL;
1242 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
1243
1244 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
1245 value &= ~PLLE_AUX_SS_SWCTL;
1246 value &= ~PLLE_AUX_ENABLE_SWCTL;
1247 value |= PLLE_AUX_SS_SEQ_INCLUDE;
1248 value |= PLLE_AUX_USE_LOCKDET;
1249 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
1250
1251 /* 8. Wait 1 us */
1252
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1253 udelay(1);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1254 value |= PLLE_AUX_SEQ_ENABLE;
1255 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1256
1257 return 0;
1258}
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1259
1260struct periph_clk_init periph_clk_init_table[] = {
1261 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
1262 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
1263 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
1264 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
1265 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
1266 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
1267 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1268 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
1269 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
1270 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
1271 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
1272 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
1273 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
1274 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
1275 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
1276 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
1277 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
1278 { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
1279 { -1, },
1280};