Log - ef64c0b4a2bbc877c6a671cb25ef8fec55c53c8e - filogic/uboot

58970ae ARM: tegra: Remove disp1 clock initialization on Tegra210 by Thierry Reding · Mon Apr 15 11:32:16 2019 +0200
317a47c ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210 by Thierry Reding · Mon Apr 15 11:32:15 2019 +0200
10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
532543c ARM: tegra: add APIs the clock uclass driver will need by Stephen Warren · Tue Sep 13 10:45:56 2016 -0600
1453d10 ARM: tegra: add peripheral clock init table by Stephen Warren · Tue Sep 13 10:45:55 2016 -0600
b6409f2 ARM: tegra210: set PLLE_PTS bit when enabling PLLE by Stephen Warren · Tue Mar 22 09:45:36 2016 -0600
553b61e ARM: tegra210: implement PLLE init procedure from TRM by Stephen Warren · Mon Oct 05 16:58:52 2015 -0600
4c3aaa7 ARM: tegra: clk_m is the architected timer source clock by Thierry Reding · Thu Aug 20 11:42:20 2015 +0200
fa6e24d ARM: tegra: Implement clk_m by Thierry Reding · Thu Aug 20 11:42:19 2015 +0200
b6ba3fb tegra: Correct logic for reading pll_misc in clock_start_pll() by Simon Glass · Mon Aug 10 07:14:36 2015 -0600
a8480ef Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. by Tom Warren · Thu Jun 25 09:50:44 2015 -0700
27bce71 Tegra: clocks: Add 38.4MHz OSC support for T210 use by Tom Warren · Mon Jun 22 13:03:44 2015 -0700
f80dd82 ARM: Tegra210: Add SoC code/include files for T210 by Tom Warren · Mon Feb 02 13:22:29 2015 -0700