| commit | b6ba3fb8b69733eb772b8c4f843b2c0086017fa9 | [log] [tgz] |
|---|---|---|
| author | Simon Glass <sjg@chromium.org> | Mon Aug 10 07:14:36 2015 -0600 |
| committer | Tom Warren <twarren@nvidia.com> | Thu Aug 13 13:06:04 2015 -0700 |
| tree | c0cf4cf1f57b09c09be1dfd12a543b991a82ce0d | |
| parent | debf298542042921f15e4caee29a79af560af970 [diff] |
tegra: Correct logic for reading pll_misc in clock_start_pll() The logic for simple PLLs on T124 was broken by this commit: 722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Correct it by reading from the same pll_misc register that it writes to and adding an entry for the DP PLL in the pllinfo table. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>