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Gabor Juhos02c754a2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 *
Tom Rinifba23012013-07-24 09:34:30 -04004 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos02c754a2013-05-22 03:57:37 +00005 */
6
Paul Burton10a74b52013-11-09 10:22:08 +00007#ifndef _MALTA_CONFIG_H
8#define _MALTA_CONFIG_H
Gabor Juhos02c754a2013-05-22 03:57:37 +00009
Gabor Juhos02c754a2013-05-22 03:57:37 +000010/*
11 * System configuration
12 */
Paul Burton10a74b52013-11-09 10:22:08 +000013#define CONFIG_MALTA
Paul Burtonc2150342014-04-07 10:11:23 +010014#define CONFIG_BOARD_EARLY_INIT_F
15#define CONFIG_DISPLAY_BOARDINFO
Gabor Juhos02c754a2013-05-22 03:57:37 +000016
Gabor Juhos5e195152013-10-24 14:32:00 +020017#define CONFIG_MEMSIZE_IN_BYTES
18
Gabor Juhos652ccee2013-05-22 03:57:42 +000019#define CONFIG_PCI
20#define CONFIG_PCI_GT64120
Paul Burton234882c2013-11-08 11:18:50 +000021#define CONFIG_PCI_MSC01
Gabor Juhos652ccee2013-05-22 03:57:42 +000022#define CONFIG_PCI_PNP
Gabor Juhos439c50c2013-05-22 03:57:44 +000023#define CONFIG_PCNET
Paul Burtonf38eea62013-11-08 11:18:52 +000024#define CONFIG_PCNET_79C973
25#define PCNET_HAS_PROM
Gabor Juhos652ccee2013-05-22 03:57:42 +000026
Paul Burtonc028f9b2013-11-08 11:18:55 +000027#define CONFIG_MISC_INIT_R
28#define CONFIG_RTC_MC146818
29#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
30
Gabor Juhos02c754a2013-05-22 03:57:37 +000031/*
32 * CPU Configuration
33 */
34#define CONFIG_SYS_MHZ 250 /* arbitrary value */
35#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Gabor Juhos02c754a2013-05-22 03:57:37 +000036
Gabor Juhos02c754a2013-05-22 03:57:37 +000037/*
38 * Memory map
39 */
Gabor Juhosc1df3702013-11-12 16:47:32 +010040#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Gabor Juhos02c754a2013-05-22 03:57:37 +000042
43#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
44#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
45
46#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
47
48#define CONFIG_SYS_LOAD_ADDR 0x81000000
49#define CONFIG_SYS_MEMTEST_START 0x80100000
50#define CONFIG_SYS_MEMTEST_END 0x80800000
51
52#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
53#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
Paul Burton657b9352013-11-26 17:45:28 +000054#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
Gabor Juhos02c754a2013-05-22 03:57:37 +000055
Gabor Juhos02c754a2013-05-22 03:57:37 +000056#define CONFIG_SYS_CBSIZE 256
57#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
58 sizeof(CONFIG_SYS_PROMPT) + 16)
59#define CONFIG_SYS_MAXARGS 16
60
61#define CONFIG_AUTO_COMPLETE
62#define CONFIG_CMDLINE_EDITING
63
64/*
65 * Serial driver
66 */
67#define CONFIG_BAUDRATE 115200
68
Gabor Juhos02c754a2013-05-22 03:57:37 +000069#define CONFIG_SYS_NS16550_SERIAL
70#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Burton6d891b72013-11-26 17:45:26 +000071#define CONFIG_SYS_NS16550_CLK (115200 * 16)
Daniel Schwierzeck535e08e2016-01-09 17:32:44 +010072#define CONFIG_SYS_NS16550_COM1 0xb80003f8
73#define CONFIG_SYS_NS16550_COM2 0xbb0003f8
Gabor Juhos02c754a2013-05-22 03:57:37 +000074#define CONFIG_CONS_INDEX 1
75
76/*
Gabor Juhos02c754a2013-05-22 03:57:37 +000077 * Flash configuration
78 */
Daniel Schwierzeck535e08e2016-01-09 17:32:44 +010079#define CONFIG_SYS_FLASH_BASE 0xbe000000
Gabor Juhos2c434772013-05-22 03:57:39 +000080#define CONFIG_SYS_MAX_FLASH_BANKS 1
81#define CONFIG_SYS_MAX_FLASH_SECT 128
82#define CONFIG_SYS_FLASH_CFI
83#define CONFIG_FLASH_CFI_DRIVER
84#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Gabor Juhos02c754a2013-05-22 03:57:37 +000085
86/*
Paul Burton60465222013-11-08 11:18:56 +000087 * Environment
88 */
89#define CONFIG_ENV_IS_IN_FLASH
90#define CONFIG_ENV_SECT_SIZE 0x20000
91#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
92#define CONFIG_ENV_ADDR \
93 (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
94
95/*
Paul Burtonc6c38532015-01-29 10:38:20 +000096 * IDE/ATA
97 */
98#define CONFIG_SYS_IDE_MAXBUS 1
99#define CONFIG_SYS_IDE_MAXDEVICE 2
100#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
101#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
102#define CONFIG_SYS_ATA_DATA_OFFSET 0
103#define CONFIG_SYS_ATA_REG_OFFSET 0
104
105/*
Gabor Juhos02c754a2013-05-22 03:57:37 +0000106 * Commands
107 */
Paul Burtonc028f9b2013-11-08 11:18:55 +0000108#define CONFIG_CMD_DATE
Paul Burtonc6c38532015-01-29 10:38:20 +0000109#define CONFIG_CMD_IDE
Gabor Juhos652ccee2013-05-22 03:57:42 +0000110#define CONFIG_CMD_PCI
111
Gabor Juhos02c754a2013-05-22 03:57:37 +0000112#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
113
Paul Burton10a74b52013-11-09 10:22:08 +0000114#endif /* _MALTA_CONFIG_H */