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Bin Meng055700e2018-09-26 06:55:14 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <common.h>
Bin Meng7a3bbfb2018-12-12 06:12:34 -08007#include <cpu.h>
Bin Mengedfe9a92018-12-12 06:12:38 -08008#include <dm.h>
Heinrich Schuchardtcc382ff2021-09-12 21:11:46 +02009#include <dm/lists.h>
Simon Glassfc557362022-03-04 08:43:05 -070010#include <event.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Bin Meng7a3bbfb2018-12-12 06:12:34 -080012#include <log.h>
Bin Menga7544ed2018-12-12 06:12:40 -080013#include <asm/encoding.h>
Simon Glassfc557362022-03-04 08:43:05 -070014#include <asm/system.h>
Bin Mengedfe9a92018-12-12 06:12:38 -080015#include <dm/uclass-internal.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Bin Meng055700e2018-09-26 06:55:14 -070017
Lukas Auer39a652b2018-11-22 11:26:29 +010018/*
Lukas Auera3596652019-03-17 19:28:37 +010019 * The variables here must be stored in the data section since they are used
Lukas Auer39a652b2018-11-22 11:26:29 +010020 * before the bss section is available.
21 */
Nikita Shubin7e5e0292022-09-02 11:47:39 +030022#if !CONFIG_IS_ENABLED(XIP)
Marek BehĂșn4bebdd32021-05-20 13:23:52 +020023u32 hart_lottery __section(".data") = 0;
Lukas Auera3596652019-03-17 19:28:37 +010024
Rick Chen9c4d5c12022-09-21 14:34:54 +080025#ifdef CONFIG_AVAILABLE_HARTS
Lukas Auera3596652019-03-17 19:28:37 +010026/*
27 * The main hart running U-Boot has acquired available_harts_lock until it has
28 * finished initialization of global data.
29 */
30u32 available_harts_lock = 1;
Rick Chene5e6c362019-04-30 13:49:33 +080031#endif
Rick Chen9c4d5c12022-09-21 14:34:54 +080032#endif
Lukas Auer39a652b2018-11-22 11:26:29 +010033
Bin Meng055700e2018-09-26 06:55:14 -070034static inline bool supports_extension(char ext)
35{
Nikita Shubinc9382b12022-12-14 08:58:43 +030036#if CONFIG_IS_ENABLED(RISCV_MMODE)
37 return csr_read(CSR_MISA) & (1 << (ext - 'a'));
38#elif CONFIG_CPU
Bin Mengedfe9a92018-12-12 06:12:38 -080039 struct udevice *dev;
40 char desc[32];
Yu Chien Peter Lina35afb82022-11-05 14:02:14 +080041 int i;
Bin Mengedfe9a92018-12-12 06:12:38 -080042
43 uclass_find_first_device(UCLASS_CPU, &dev);
44 if (!dev) {
45 debug("unable to find the RISC-V cpu device\n");
46 return false;
47 }
48 if (!cpu_get_desc(dev, desc, sizeof(desc))) {
Yu Chien Peter Lina35afb82022-11-05 14:02:14 +080049 /*
50 * skip the first 4 characters (rv32|rv64) and
51 * check until underscore
52 */
53 for (i = 4; i < sizeof(desc); i++) {
54 if (desc[i] == '_' || desc[i] == '\0')
55 break;
56 if (desc[i] == ext)
57 return true;
58 }
Bin Mengedfe9a92018-12-12 06:12:38 -080059 }
60
61 return false;
62#else /* !CONFIG_CPU */
Bin Mengedfe9a92018-12-12 06:12:38 -080063#warning "There is no way to determine the available extensions in S-mode."
64#warning "Please convert your board to use the RISC-V CPU driver."
65 return false;
Bin Mengedfe9a92018-12-12 06:12:38 -080066#endif /* CONFIG_CPU */
Bin Meng055700e2018-09-26 06:55:14 -070067}
68
Bin Meng7a3bbfb2018-12-12 06:12:34 -080069static int riscv_cpu_probe(void)
70{
71#ifdef CONFIG_CPU
72 int ret;
73
74 /* probe cpus so that RISC-V timer can be bound */
75 ret = cpu_probe_all();
76 if (ret)
77 return log_msg_ret("RISC-V cpus probe failed\n", ret);
78#endif
79
80 return 0;
81}
82
Sean Andersondd1cd702020-09-21 07:51:38 -040083/*
84 * This is called on secondary harts just after the IPI is init'd. Currently
85 * there's nothing to do, since we just need to clear any existing IPIs, and
86 * that is handled by the sending of an ipi itself.
87 */
88#if CONFIG_IS_ENABLED(SMP)
89static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
90{
91}
92#endif
93
Simon Glassfc557362022-03-04 08:43:05 -070094int riscv_cpu_setup(void *ctx, struct event *event)
Bin Meng7a3bbfb2018-12-12 06:12:34 -080095{
Bin Menga7544ed2018-12-12 06:12:40 -080096 int ret;
97
98 ret = riscv_cpu_probe();
99 if (ret)
100 return ret;
101
102 /* Enable FPU */
103 if (supports_extension('d') || supports_extension('f')) {
104 csr_set(MODE_PREFIX(status), MSTATUS_FS);
Bin Mengf9426362019-07-10 23:43:13 -0700105 csr_write(CSR_FCSR, 0);
Bin Menga7544ed2018-12-12 06:12:40 -0800106 }
107
108 if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
109 /*
110 * Enable perf counters for cycle, time,
111 * and instret counters only
112 */
Nikita Shubinc9382b12022-12-14 08:58:43 +0300113 if (supports_extension('u')) {
Sean Anderson7f4b6662020-06-24 06:41:19 -0400114#ifdef CONFIG_RISCV_PRIV_1_9
Nikita Shubinc9382b12022-12-14 08:58:43 +0300115 csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
116 csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
Sean Anderson7f4b6662020-06-24 06:41:19 -0400117#else
Nikita Shubinc9382b12022-12-14 08:58:43 +0300118 csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
Sean Anderson7f4b6662020-06-24 06:41:19 -0400119#endif
Nikita Shubinc9382b12022-12-14 08:58:43 +0300120 }
Bin Menga7544ed2018-12-12 06:12:40 -0800121
122 /* Disable paging */
123 if (supports_extension('s'))
Sean Anderson7f4b6662020-06-24 06:41:19 -0400124#ifdef CONFIG_RISCV_PRIV_1_9
125 csr_read_clear(CSR_MSTATUS, SR_VM);
126#else
Bin Mengf9426362019-07-10 23:43:13 -0700127 csr_write(CSR_SATP, 0);
Sean Anderson7f4b6662020-06-24 06:41:19 -0400128#endif
Bin Menga7544ed2018-12-12 06:12:40 -0800129 }
130
Bin Meng257875d2020-07-19 23:17:07 -0700131#if CONFIG_IS_ENABLED(SMP)
Sean Andersonb1d0cb32020-06-24 06:41:18 -0400132 ret = riscv_init_ipi();
133 if (ret)
134 return ret;
Sean Andersondd1cd702020-09-21 07:51:38 -0400135
136 /*
137 * Clear all pending IPIs on secondary harts. We don't do anything on
138 * the boot hart, since we never send an IPI to ourselves, and no
139 * interrupts are enabled
140 */
141 ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0);
142 if (ret)
143 return ret;
Sean Andersonb1d0cb32020-06-24 06:41:18 -0400144#endif
145
Bin Menga7544ed2018-12-12 06:12:40 -0800146 return 0;
Bin Meng7a3bbfb2018-12-12 06:12:34 -0800147}
Simon Glass93074012023-05-04 16:50:45 -0600148EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
Bin Meng7a3bbfb2018-12-12 06:12:34 -0800149
150int arch_early_init_r(void)
151{
Heinrich Schuchardtcc382ff2021-09-12 21:11:46 +0200152 int ret;
153
154 ret = riscv_cpu_probe();
155 if (ret)
156 return ret;
157
158 if (IS_ENABLED(CONFIG_SYSRESET_SBI))
159 device_bind_driver(gd->dm_root, "sbi-sysreset",
160 "sbi-sysreset", NULL);
161
162 return 0;
Bin Meng7a3bbfb2018-12-12 06:12:34 -0800163}
Green Wan26120802021-05-02 23:23:04 -0700164
165/**
166 * harts_early_init() - A callback function called by start.S to configure
167 * feature settings of each hart.
168 *
169 * In a multi-core system, memory access shall be careful here, it shall
170 * take care of race conditions.
171 */
172__weak void harts_early_init(void)
173{
174}