riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs. Using the new CSR on an old processor causes an illegal
instruction exception. This patch adds an option to use the old CSRs
instead of the new one.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d75a3f0..bbd6c15 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -91,11 +91,20 @@
* Enable perf counters for cycle, time,
* and instret counters only
*/
+#ifdef CONFIG_RISCV_PRIV_1_9
+ csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+ csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
/* Disable paging */
if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9
+ csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
csr_write(CSR_SATP, 0);
+#endif
}
#ifdef CONFIG_SMP