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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangaa827752017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangaa827752017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübneref6db5e2017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020031 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020032 select SPL_REGMAP
33 select SPL_SYSCON
34 select SPL_RAM
35 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020036 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020037 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010038 select ROCKCHIP_BROM_HELPER
39 help
40 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
41 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
42 video interfaces, several memory options and video codec support.
43 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
44 UART, SPI, I2C and PWMs.
45
Kever Yang57d4dbf2017-06-23 17:17:52 +080046config ROCKCHIP_RK322X
47 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053048 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080049 select SUPPORT_SPL
50 select SPL
51 select ROCKCHIP_BROM_HELPER
Kever Yang57d4dbf2017-06-23 17:17:52 +080052 help
53 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
54 including NEON and GPU, Mali-400 graphics, several DDR3 options
55 and video codec support. Peripherals include Gigabit Ethernet,
56 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
57
Simon Glass2cffe662015-08-30 16:55:38 -060058config ROCKCHIP_RK3288
59 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053060 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080061 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080062 select SUPPORT_SPL
63 select SPL
Eddie Caib3501fe2017-12-15 08:17:13 +080064 imply USB_FUNCTION_ROCKUSB
65 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -060066 help
67 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
68 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
69 video interfaces supporting HDMI and eDP, several DDR3 options
70 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +010071 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -060072
Jagan Tekie5df8342018-02-23 13:13:10 +053073if ROCKCHIP_RK3288
74
Jagan Teki843ac352018-02-23 13:13:11 +053075config TPL_TEXT_BASE
76 default 0xff704000
77
Tom Rinie34a2f32019-01-22 17:09:25 -050078config TPL_MAX_SIZE
79 default 32768
80
Jagan Tekie5df8342018-02-23 13:13:10 +053081endif
82
Kever Yangec02b3c2017-02-23 15:37:51 +080083config ROCKCHIP_RK3328
84 bool "Support Rockchip RK3328"
85 select ARM64
86 help
87 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
88 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
89 video interfaces supporting HDMI and eDP, several DDR3 options
90 and video codec support. Peripherals include Gigabit Ethernet,
91 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
92
Andreas Färber9e3ad682017-05-15 17:51:18 +080093config ROCKCHIP_RK3368
94 bool "Support Rockchip RK3368"
95 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +020096 select SUPPORT_SPL
97 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +020098 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
99 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200100 imply SPL_SEPARATE_BSS
101 imply SPL_SERIAL_SUPPORT
102 imply TPL_SERIAL_SUPPORT
Andreas Färber9e3ad682017-05-15 17:51:18 +0800103 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200104 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
105 into a big and little cluster with 4 cores each) Cortex-A53 including
106 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
107 (for the little cluster), PowerVR G6110 based graphics, one video
108 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
109 video codec support.
110
111 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
112 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800113
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200114if ROCKCHIP_RK3368
115
Philipp Tomsich7d1319b2017-07-28 20:20:41 +0200116config TPL_TEXT_BASE
117 default 0xff8c1000
118
119config TPL_MAX_SIZE
120 default 28672
121
122config TPL_STACK
123 default 0xff8cffff
124
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200125endif
126
Kever Yang0d3d7832016-07-19 21:16:59 +0800127config ROCKCHIP_RK3399
128 bool "Support Rockchip RK3399"
129 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800130 select SUPPORT_SPL
131 select SPL
132 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200133 select SPL_SERIAL_SUPPORT
134 select SPL_DRIVERS_MISC_SUPPORT
Andy Yan70378cb2017-10-11 15:00:16 +0800135 select BOARD_LATE_INIT
Andy Yand2349d92017-10-11 15:00:49 +0800136 select ROCKCHIP_BROM_HELPER
Kever Yang0d3d7832016-07-19 21:16:59 +0800137 help
138 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
139 and quad-core Cortex-A53.
140 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
141 video interfaces supporting HDMI and eDP, several DDR3 options
142 and video codec support. Peripherals include Gigabit Ethernet,
143 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
144
Andy Yan2d982da2017-06-01 18:00:55 +0800145config ROCKCHIP_RV1108
146 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530147 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800148 help
149 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
150 and a DSP.
151
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200152config ROCKCHIP_USB_UART
153 bool "Route uart output to usb pins"
154 help
155 Rockchip SoCs have the ability to route the signals of the debug
156 uart through the d+ and d- pins of a specific usb phy to enable
157 some form of closed-case debugging. With this option supported
158 SoCs will enable this routing as a debug measure.
159
Philipp Tomsich798370f2017-06-29 11:21:15 +0200160config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800161 bool "SPL returns to bootrom"
162 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100163 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200164 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800165 help
166 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
167 SPL will return to the boot rom, which will then load the U-Boot
168 binary to keep going on.
169
Philipp Tomsich798370f2017-06-29 11:21:15 +0200170config TPL_ROCKCHIP_BACK_TO_BROM
171 bool "TPL returns to bootrom"
172 default y if ROCKCHIP_RK3368
173 select ROCKCHIP_BROM_HELPER
174 depends on TPL
175 help
176 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
177 SPL will return to the boot rom, which will then load the U-Boot
178 binary to keep going on.
179
Andy Yan70378cb2017-10-11 15:00:16 +0800180config ROCKCHIP_BOOT_MODE_REG
181 hex "Rockchip boot mode flag register address"
182 default 0x200081c8 if ROCKCHIP_RK3036
183 default 0x20004040 if ROCKCHIP_RK3188
184 default 0x110005c8 if ROCKCHIP_RK322X
185 default 0xff730094 if ROCKCHIP_RK3288
186 default 0xff738200 if ROCKCHIP_RK3368
187 default 0xff320300 if ROCKCHIP_RK3399
188 default 0x10300580 if ROCKCHIP_RV1108
189 default 0
190 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800191 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800192 according to the value from this register.
193
Kever Yange484f772017-04-20 17:03:46 +0800194config ROCKCHIP_SPL_RESERVE_IRAM
195 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800196 default 0
Kever Yange484f772017-04-20 17:03:46 +0800197 help
198 SPL may need reserve memory for firmware loaded by SPL, whose load
199 address is in IRAM and may overlay with SPL text area if not
200 reserved.
201
Heiko Stübner355a8802017-02-18 19:46:25 +0100202config ROCKCHIP_BROM_HELPER
203 bool
204
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200205config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
206 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
207 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
208 help
209 Some Rockchip BROM variants (e.g. on the RK3188) load the
210 first stage in segments and enter multiple times. E.g. on
211 the RK3188, the first 1KB of the first stage are loaded
212 first and entered; after returning to the BROM, the
213 remainder of the first stage is loaded, but the BROM
214 re-enters at the same address/to the same code as previously.
215
216 This enables support code in the BOOT0 hook for the SPL stage
217 to allow multiple entries.
218
219config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
220 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
221 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
222 help
223 Some Rockchip BROM variants (e.g. on the RK3188) load the
224 first stage in segments and enter multiple times. E.g. on
225 the RK3188, the first 1KB of the first stage are loaded
226 first and entered; after returning to the BROM, the
227 remainder of the first stage is loaded, but the BROM
228 re-enters at the same address/to the same code as previously.
229
230 This enables support code in the BOOT0 hook for the TPL stage
231 to allow multiple entries.
232
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400233config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200234 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400235
huang lin1115b642015-11-17 14:20:27 +0800236source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800237source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100238source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800239source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200240source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800241source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800242source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800243source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800244source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600245endif