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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass246c1192011-06-13 16:13:09 -07002/*
Simon Glass68c41972015-07-07 20:53:42 -06003 * Copyright (c) 2015 Google, Inc
Simon Glass246c1192011-06-13 16:13:09 -07004 * Copyright (c) 2011 The Chromium OS Authors.
5 * Copyright (C) 2009 NVIDIA, Corporation
Simon Glass00be89c2014-09-08 13:44:14 -06006 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
Simon Glass246c1192011-06-13 16:13:09 -07007 */
8
Simon Glass68c41972015-07-07 20:53:42 -06009#include <dm.h>
Simon Glassce48e502015-07-07 20:53:38 -060010#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glassce48e502015-07-07 20:53:38 -060012#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060013#include <memalign.h>
Simon Glass274e0b02020-05-10 11:39:56 -060014#include <net.h>
Simon Glass246c1192011-06-13 16:13:09 -070015#include <usb.h>
Simon Glassce48e502015-07-07 20:53:38 -060016#include <asm/unaligned.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Simon Glass246c1192011-06-13 16:13:09 -070018#include <linux/mii.h>
19#include "usb_ether.h"
20
21/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
22
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -070023/* LED defines */
24#define LED_GPIO_CFG (0x24)
25#define LED_GPIO_CFG_SPD_LED (0x01000000)
26#define LED_GPIO_CFG_LNK_LED (0x00100000)
27#define LED_GPIO_CFG_FDX_LED (0x00010000)
28
Simon Glass246c1192011-06-13 16:13:09 -070029/* Tx command words */
30#define TX_CMD_A_FIRST_SEG_ 0x00002000
31#define TX_CMD_A_LAST_SEG_ 0x00001000
32
33/* Rx status word */
34#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
35#define RX_STS_ES_ 0x00008000 /* Error Summary */
36
37/* SCSRs */
38#define ID_REV 0x00
39
40#define INT_STS 0x08
41
42#define TX_CFG 0x10
43#define TX_CFG_ON_ 0x00000004
44
45#define HW_CFG 0x14
46#define HW_CFG_BIR_ 0x00001000
47#define HW_CFG_RXDOFF_ 0x00000600
48#define HW_CFG_MEF_ 0x00000020
49#define HW_CFG_BCE_ 0x00000002
50#define HW_CFG_LRST_ 0x00000008
51
52#define PM_CTRL 0x20
53#define PM_CTL_PHY_RST_ 0x00000010
54
55#define AFC_CFG 0x2C
56
57/*
58 * Hi watermark = 15.5Kb (~10 mtu pkts)
59 * low watermark = 3k (~2 mtu pkts)
60 * backpressure duration = ~ 350us
61 * Apply FC on any frame.
62 */
63#define AFC_CFG_DEFAULT 0x00F830A1
64
65#define E2P_CMD 0x30
66#define E2P_CMD_BUSY_ 0x80000000
67#define E2P_CMD_READ_ 0x00000000
68#define E2P_CMD_TIMEOUT_ 0x00000400
69#define E2P_CMD_LOADED_ 0x00000200
70#define E2P_CMD_ADDR_ 0x000001FF
71
72#define E2P_DATA 0x34
73
74#define BURST_CAP 0x38
75
76#define INT_EP_CTL 0x68
77#define INT_EP_CTL_PHY_INT_ 0x00008000
78
79#define BULK_IN_DLY 0x6C
80
81/* MAC CSRs */
82#define MAC_CR 0x100
83#define MAC_CR_MCPAS_ 0x00080000
84#define MAC_CR_PRMS_ 0x00040000
85#define MAC_CR_HPFILT_ 0x00002000
86#define MAC_CR_TXEN_ 0x00000008
87#define MAC_CR_RXEN_ 0x00000004
88
89#define ADDRH 0x104
90
91#define ADDRL 0x108
92
93#define MII_ADDR 0x114
94#define MII_WRITE_ 0x02
95#define MII_BUSY_ 0x01
96#define MII_READ_ 0x00 /* ~of MII Write bit */
97
98#define MII_DATA 0x118
99
100#define FLOW 0x11C
101
102#define VLAN1 0x120
103
104#define COE_CR 0x130
105#define Tx_COE_EN_ 0x00010000
106#define Rx_COE_EN_ 0x00000001
107
108/* Vendor-specific PHY Definitions */
109#define PHY_INT_SRC 29
110
111#define PHY_INT_MASK 30
112#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
113#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
114#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
115 PHY_INT_MASK_LINK_DOWN_)
116
117/* USB Vendor Requests */
118#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
119#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
120
121/* Some extra defines */
122#define HS_USB_PKT_SIZE 512
123#define FS_USB_PKT_SIZE 64
Stefan Brünsd3095fe2015-08-30 17:59:45 +0200124/* 5/33 is lower limit for BURST_CAP to work */
125#define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
126#define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
Simon Glass246c1192011-06-13 16:13:09 -0700127#define DEFAULT_BULK_IN_DELAY 0x00002000
128#define MAX_SINGLE_PACKET_SIZE 2048
129#define EEPROM_MAC_OFFSET 0x01
130#define SMSC95XX_INTERNAL_PHY_ID 1
131#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
132
133/* local defines */
134#define SMSC95XX_BASE_NAME "sms"
135#define USB_CTRL_SET_TIMEOUT 5000
136#define USB_CTRL_GET_TIMEOUT 5000
137#define USB_BULK_SEND_TIMEOUT 5000
138#define USB_BULK_RECV_TIMEOUT 5000
139
Stefan Brünsd3095fe2015-08-30 17:59:45 +0200140#define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
Simon Glass246c1192011-06-13 16:13:09 -0700141#define PHY_CONNECT_TIMEOUT 5000
142
143#define TURBO_MODE
144
Lucas Stach36267c42012-08-22 11:04:57 +0000145/* driver private */
146struct smsc95xx_private {
Simon Glass68c41972015-07-07 20:53:42 -0600147 struct ueth_data ueth;
Lucas Stach36267c42012-08-22 11:04:57 +0000148 size_t rx_urb_size; /* maximum USB URB size */
149 u32 mac_cr; /* MAC control register value */
150 int have_hwaddr; /* 1 if we have a hardware MAC address */
151};
Simon Glass246c1192011-06-13 16:13:09 -0700152
153/*
154 * Smsc95xx infrastructure commands
155 */
Simon Glass3faecae2015-07-07 20:53:41 -0600156static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
Simon Glass246c1192011-06-13 16:13:09 -0700157{
158 int len;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000159 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass246c1192011-06-13 16:13:09 -0700160
161 cpu_to_le32s(&data);
Ilya Yanok43b56c22012-07-15 04:43:53 +0000162 tmpbuf[0] = data;
Simon Glass246c1192011-06-13 16:13:09 -0700163
Simon Glass3faecae2015-07-07 20:53:41 -0600164 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
165 USB_VENDOR_REQUEST_WRITE_REGISTER,
166 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
167 0, index, tmpbuf, sizeof(data),
168 USB_CTRL_SET_TIMEOUT);
Simon Glass246c1192011-06-13 16:13:09 -0700169 if (len != sizeof(data)) {
170 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
171 index, data, len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600172 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700173 }
174 return 0;
175}
176
Simon Glass3faecae2015-07-07 20:53:41 -0600177static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
Simon Glass246c1192011-06-13 16:13:09 -0700178{
179 int len;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000180 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass246c1192011-06-13 16:13:09 -0700181
Simon Glass3faecae2015-07-07 20:53:41 -0600182 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
183 USB_VENDOR_REQUEST_READ_REGISTER,
184 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
Stephen Warrenb0e5b492016-03-22 22:28:16 -0600185 0, index, tmpbuf, sizeof(*data),
Simon Glass3faecae2015-07-07 20:53:41 -0600186 USB_CTRL_GET_TIMEOUT);
Ilya Yanok43b56c22012-07-15 04:43:53 +0000187 *data = tmpbuf[0];
Stephen Warrenb0e5b492016-03-22 22:28:16 -0600188 if (len != sizeof(*data)) {
Simon Glass246c1192011-06-13 16:13:09 -0700189 debug("smsc95xx_read_reg failed: index=%d, len=%d",
190 index, len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600191 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700192 }
193
194 le32_to_cpus(data);
195 return 0;
196}
197
198/* Loop until the read is completed with timeout */
Simon Glass3faecae2015-07-07 20:53:41 -0600199static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700200{
201 unsigned long start_time = get_timer(0);
202 u32 val;
203
204 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600205 smsc95xx_read_reg(udev, MII_ADDR, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700206 if (!(val & MII_BUSY_))
207 return 0;
Simon Glass3faecae2015-07-07 20:53:41 -0600208 } while (get_timer(start_time) < 1000);
Simon Glass246c1192011-06-13 16:13:09 -0700209
Simon Glassebe0e5a2015-07-07 20:53:40 -0600210 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700211}
212
Simon Glass3faecae2015-07-07 20:53:41 -0600213static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
Simon Glass246c1192011-06-13 16:13:09 -0700214{
215 u32 val, addr;
216
217 /* confirm MII not busy */
Simon Glass3faecae2015-07-07 20:53:41 -0600218 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700219 debug("MII is busy in smsc95xx_mdio_read\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600220 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700221 }
222
223 /* set the address, index & direction (read from PHY) */
224 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
Simon Glass3faecae2015-07-07 20:53:41 -0600225 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass246c1192011-06-13 16:13:09 -0700226
Simon Glass3faecae2015-07-07 20:53:41 -0600227 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700228 debug("Timed out reading MII reg %02X\n", idx);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600229 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700230 }
231
Simon Glass3faecae2015-07-07 20:53:41 -0600232 smsc95xx_read_reg(udev, MII_DATA, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700233
234 return (u16)(val & 0xFFFF);
235}
236
Simon Glass3faecae2015-07-07 20:53:41 -0600237static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
Simon Glass246c1192011-06-13 16:13:09 -0700238 int regval)
239{
240 u32 val, addr;
241
242 /* confirm MII not busy */
Simon Glass3faecae2015-07-07 20:53:41 -0600243 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700244 debug("MII is busy in smsc95xx_mdio_write\n");
245 return;
246 }
247
248 val = regval;
Simon Glass3faecae2015-07-07 20:53:41 -0600249 smsc95xx_write_reg(udev, MII_DATA, val);
Simon Glass246c1192011-06-13 16:13:09 -0700250
251 /* set the address, index & direction (write to PHY) */
252 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
Simon Glass3faecae2015-07-07 20:53:41 -0600253 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass246c1192011-06-13 16:13:09 -0700254
Simon Glass3faecae2015-07-07 20:53:41 -0600255 if (smsc95xx_phy_wait_not_busy(udev))
Simon Glass246c1192011-06-13 16:13:09 -0700256 debug("Timed out writing MII reg %02X\n", idx);
257}
258
Simon Glass3faecae2015-07-07 20:53:41 -0600259static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700260{
261 unsigned long start_time = get_timer(0);
262 u32 val;
263
264 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600265 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700266 if (!(val & E2P_CMD_BUSY_))
267 return 0;
268 udelay(40);
269 } while (get_timer(start_time) < 1 * 1000 * 1000);
270
271 debug("EEPROM is busy\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600272 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700273}
274
Simon Glass3faecae2015-07-07 20:53:41 -0600275static int smsc95xx_wait_eeprom(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700276{
277 unsigned long start_time = get_timer(0);
278 u32 val;
279
280 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600281 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700282 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
283 break;
284 udelay(40);
285 } while (get_timer(start_time) < 1 * 1000 * 1000);
286
287 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
288 debug("EEPROM read operation timeout\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600289 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700290 }
291 return 0;
292}
293
Simon Glass3faecae2015-07-07 20:53:41 -0600294static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
Simon Glass246c1192011-06-13 16:13:09 -0700295 u8 *data)
296{
297 u32 val;
298 int i, ret;
299
Simon Glass3faecae2015-07-07 20:53:41 -0600300 ret = smsc95xx_eeprom_confirm_not_busy(udev);
Simon Glass246c1192011-06-13 16:13:09 -0700301 if (ret)
302 return ret;
303
304 for (i = 0; i < length; i++) {
305 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
Simon Glass3faecae2015-07-07 20:53:41 -0600306 smsc95xx_write_reg(udev, E2P_CMD, val);
Simon Glass246c1192011-06-13 16:13:09 -0700307
Simon Glass3faecae2015-07-07 20:53:41 -0600308 ret = smsc95xx_wait_eeprom(udev);
Simon Glass246c1192011-06-13 16:13:09 -0700309 if (ret < 0)
310 return ret;
311
Simon Glass3faecae2015-07-07 20:53:41 -0600312 smsc95xx_read_reg(udev, E2P_DATA, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700313 data[i] = val & 0xFF;
314 offset++;
315 }
316 return 0;
317}
318
319/*
320 * mii_nway_restart - restart NWay (autonegotiation) for this interface
321 *
322 * Returns 0 on success, negative on error.
323 */
Simon Glass3faecae2015-07-07 20:53:41 -0600324static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
Simon Glass246c1192011-06-13 16:13:09 -0700325{
326 int bmcr;
327 int r = -1;
328
329 /* if autoneg is off, it's an error */
Simon Glass3faecae2015-07-07 20:53:41 -0600330 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
Simon Glass246c1192011-06-13 16:13:09 -0700331
332 if (bmcr & BMCR_ANENABLE) {
333 bmcr |= BMCR_ANRESTART;
Simon Glass3faecae2015-07-07 20:53:41 -0600334 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
Simon Glass246c1192011-06-13 16:13:09 -0700335 r = 0;
336 }
337 return r;
338}
339
Simon Glass3faecae2015-07-07 20:53:41 -0600340static int smsc95xx_phy_initialize(struct usb_device *udev,
341 struct ueth_data *dev)
Simon Glass246c1192011-06-13 16:13:09 -0700342{
Simon Glass3faecae2015-07-07 20:53:41 -0600343 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
344 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
345 ADVERTISE_ALL | ADVERTISE_CSMA |
346 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Simon Glass246c1192011-06-13 16:13:09 -0700347
348 /* read to clear */
Simon Glass3faecae2015-07-07 20:53:41 -0600349 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
Simon Glass246c1192011-06-13 16:13:09 -0700350
Simon Glass3faecae2015-07-07 20:53:41 -0600351 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
352 PHY_INT_MASK_DEFAULT_);
353 mii_nway_restart(udev, dev);
Simon Glass246c1192011-06-13 16:13:09 -0700354
355 debug("phy initialised succesfully\n");
356 return 0;
357}
358
Simon Glass3faecae2015-07-07 20:53:41 -0600359static int smsc95xx_init_mac_address(unsigned char *enetaddr,
360 struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700361{
Simon Glass3faecae2015-07-07 20:53:41 -0600362 int ret;
363
Simon Glass246c1192011-06-13 16:13:09 -0700364 /* try reading mac address from EEPROM */
Simon Glass3faecae2015-07-07 20:53:41 -0600365 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
366 if (ret)
367 return ret;
368
369 if (is_valid_ethaddr(enetaddr)) {
370 /* eeprom values are valid so use them */
371 debug("MAC address read from EEPROM\n");
372 return 0;
Simon Glass246c1192011-06-13 16:13:09 -0700373 }
374
375 /*
376 * No eeprom, or eeprom values are invalid. Generating a random MAC
377 * address is not safe. Just return an error.
378 */
Simon Glassebe0e5a2015-07-07 20:53:40 -0600379 debug("Invalid MAC address read from EEPROM\n");
380
381 return -ENXIO;
Simon Glass246c1192011-06-13 16:13:09 -0700382}
383
Simon Glass3faecae2015-07-07 20:53:41 -0600384static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
385 struct smsc95xx_private *priv,
386 unsigned char *enetaddr)
Simon Glass246c1192011-06-13 16:13:09 -0700387{
Chris Packhamfd3224b2016-07-13 09:52:36 +1200388 u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
389 u32 addr_hi = get_unaligned_le16(&enetaddr[4]);
Simon Glass246c1192011-06-13 16:13:09 -0700390 int ret;
391
392 /* set hardware address */
393 debug("** %s()\n", __func__);
Simon Glass3faecae2015-07-07 20:53:41 -0600394 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
Wolfgang Grandeggerf9af1f82011-11-14 23:19:15 +0000395 if (ret < 0)
Simon Glass246c1192011-06-13 16:13:09 -0700396 return ret;
Simon Glass246c1192011-06-13 16:13:09 -0700397
Simon Glass3faecae2015-07-07 20:53:41 -0600398 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
Simon Glass246c1192011-06-13 16:13:09 -0700399 if (ret < 0)
400 return ret;
Wolfgang Grandeggerf9af1f82011-11-14 23:19:15 +0000401
Simon Glass3faecae2015-07-07 20:53:41 -0600402 debug("MAC %pM\n", enetaddr);
Lucas Stach36267c42012-08-22 11:04:57 +0000403 priv->have_hwaddr = 1;
Simon Glass3faecae2015-07-07 20:53:41 -0600404
Simon Glass246c1192011-06-13 16:13:09 -0700405 return 0;
406}
407
408/* Enable or disable Tx & Rx checksum offload engines */
Simon Glass3faecae2015-07-07 20:53:41 -0600409static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
410 int use_rx_csum)
Simon Glass246c1192011-06-13 16:13:09 -0700411{
412 u32 read_buf;
Simon Glass3faecae2015-07-07 20:53:41 -0600413 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700414 if (ret < 0)
415 return ret;
416
417 if (use_tx_csum)
418 read_buf |= Tx_COE_EN_;
419 else
420 read_buf &= ~Tx_COE_EN_;
421
422 if (use_rx_csum)
423 read_buf |= Rx_COE_EN_;
424 else
425 read_buf &= ~Rx_COE_EN_;
426
Simon Glass3faecae2015-07-07 20:53:41 -0600427 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700428 if (ret < 0)
429 return ret;
430
431 debug("COE_CR = 0x%08x\n", read_buf);
432 return 0;
433}
434
Simon Glass3faecae2015-07-07 20:53:41 -0600435static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700436{
437 /* No multicast in u-boot */
Lucas Stach36267c42012-08-22 11:04:57 +0000438 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
Simon Glass246c1192011-06-13 16:13:09 -0700439}
440
441/* starts the TX path */
Simon Glass3faecae2015-07-07 20:53:41 -0600442static void smsc95xx_start_tx_path(struct usb_device *udev,
443 struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700444{
445 u32 reg_val;
446
447 /* Enable Tx at MAC */
Lucas Stach36267c42012-08-22 11:04:57 +0000448 priv->mac_cr |= MAC_CR_TXEN_;
Simon Glass246c1192011-06-13 16:13:09 -0700449
Simon Glass3faecae2015-07-07 20:53:41 -0600450 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700451
452 /* Enable Tx at SCSRs */
453 reg_val = TX_CFG_ON_;
Simon Glass3faecae2015-07-07 20:53:41 -0600454 smsc95xx_write_reg(udev, TX_CFG, reg_val);
Simon Glass246c1192011-06-13 16:13:09 -0700455}
456
457/* Starts the Receive path */
Simon Glass3faecae2015-07-07 20:53:41 -0600458static void smsc95xx_start_rx_path(struct usb_device *udev,
459 struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700460{
Lucas Stach36267c42012-08-22 11:04:57 +0000461 priv->mac_cr |= MAC_CR_RXEN_;
Simon Glass3faecae2015-07-07 20:53:41 -0600462 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700463}
464
Simon Glass3faecae2015-07-07 20:53:41 -0600465static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
466 struct smsc95xx_private *priv,
467 unsigned char *enetaddr)
Simon Glass246c1192011-06-13 16:13:09 -0700468{
469 int ret;
470 u32 write_buf;
471 u32 read_buf;
472 u32 burst_cap;
473 int timeout;
Simon Glass246c1192011-06-13 16:13:09 -0700474#define TIMEOUT_RESOLUTION 50 /* ms */
475 int link_detected;
476
477 debug("** %s()\n", __func__);
478 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
479
480 write_buf = HW_CFG_LRST_;
Simon Glass3faecae2015-07-07 20:53:41 -0600481 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700482 if (ret < 0)
483 return ret;
484
485 timeout = 0;
486 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600487 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700488 if (ret < 0)
489 return ret;
490 udelay(10 * 1000);
491 timeout++;
492 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
493
494 if (timeout >= 100) {
495 debug("timeout waiting for completion of Lite Reset\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600496 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700497 }
498
499 write_buf = PM_CTL_PHY_RST_;
Simon Glass3faecae2015-07-07 20:53:41 -0600500 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700501 if (ret < 0)
502 return ret;
503
504 timeout = 0;
505 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600506 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700507 if (ret < 0)
508 return ret;
509 udelay(10 * 1000);
510 timeout++;
511 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
512 if (timeout >= 100) {
513 debug("timeout waiting for PHY Reset\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600514 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700515 }
Lucas Stach36267c42012-08-22 11:04:57 +0000516 if (!priv->have_hwaddr) {
Simon Glass246c1192011-06-13 16:13:09 -0700517 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600518 return -EADDRNOTAVAIL;
Simon Glass246c1192011-06-13 16:13:09 -0700519 }
Simon Glass3faecae2015-07-07 20:53:41 -0600520 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600521 if (ret < 0)
522 return ret;
Simon Glass246c1192011-06-13 16:13:09 -0700523
Simon Glass246c1192011-06-13 16:13:09 -0700524#ifdef TURBO_MODE
525 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
526 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
Lucas Stach36267c42012-08-22 11:04:57 +0000527 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700528 } else {
529 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
Lucas Stach36267c42012-08-22 11:04:57 +0000530 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700531 }
532#else
533 burst_cap = 0;
Lucas Stach36267c42012-08-22 11:04:57 +0000534 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700535#endif
Lucas Stach36267c42012-08-22 11:04:57 +0000536 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
Simon Glass246c1192011-06-13 16:13:09 -0700537
Simon Glass3faecae2015-07-07 20:53:41 -0600538 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
Simon Glass246c1192011-06-13 16:13:09 -0700539 if (ret < 0)
540 return ret;
541
Simon Glass3faecae2015-07-07 20:53:41 -0600542 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700543 if (ret < 0)
544 return ret;
545 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
546
547 read_buf = DEFAULT_BULK_IN_DELAY;
Simon Glass3faecae2015-07-07 20:53:41 -0600548 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700549 if (ret < 0)
550 return ret;
551
Simon Glass3faecae2015-07-07 20:53:41 -0600552 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700553 if (ret < 0)
554 return ret;
555 debug("Read Value from BULK_IN_DLY after writing: "
556 "0x%08x\n", read_buf);
557
Simon Glass3faecae2015-07-07 20:53:41 -0600558 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700559 if (ret < 0)
560 return ret;
561 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
562
563#ifdef TURBO_MODE
564 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
565#endif
566 read_buf &= ~HW_CFG_RXDOFF_;
567
568#define NET_IP_ALIGN 0
569 read_buf |= NET_IP_ALIGN << 9;
570
Simon Glass3faecae2015-07-07 20:53:41 -0600571 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700572 if (ret < 0)
573 return ret;
574
Simon Glass3faecae2015-07-07 20:53:41 -0600575 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700576 if (ret < 0)
577 return ret;
578 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
579
580 write_buf = 0xFFFFFFFF;
Simon Glass3faecae2015-07-07 20:53:41 -0600581 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700582 if (ret < 0)
583 return ret;
584
Simon Glass3faecae2015-07-07 20:53:41 -0600585 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700586 if (ret < 0)
587 return ret;
588 debug("ID_REV = 0x%08x\n", read_buf);
589
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -0700590 /* Configure GPIO pins as LED outputs */
591 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
592 LED_GPIO_CFG_FDX_LED;
Simon Glass3faecae2015-07-07 20:53:41 -0600593 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -0700594 if (ret < 0)
595 return ret;
596 debug("LED_GPIO_CFG set\n");
597
Simon Glass246c1192011-06-13 16:13:09 -0700598 /* Init Tx */
599 write_buf = 0;
Simon Glass3faecae2015-07-07 20:53:41 -0600600 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700601 if (ret < 0)
602 return ret;
603
604 read_buf = AFC_CFG_DEFAULT;
Simon Glass3faecae2015-07-07 20:53:41 -0600605 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700606 if (ret < 0)
607 return ret;
608
Simon Glass3faecae2015-07-07 20:53:41 -0600609 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700610 if (ret < 0)
611 return ret;
612
613 /* Init Rx. Set Vlan */
614 write_buf = (u32)ETH_P_8021Q;
Simon Glass3faecae2015-07-07 20:53:41 -0600615 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700616 if (ret < 0)
617 return ret;
618
619 /* Disable checksum offload engines */
Simon Glass3faecae2015-07-07 20:53:41 -0600620 ret = smsc95xx_set_csums(udev, 0, 0);
Simon Glass246c1192011-06-13 16:13:09 -0700621 if (ret < 0) {
622 debug("Failed to set csum offload: %d\n", ret);
623 return ret;
624 }
Simon Glass3faecae2015-07-07 20:53:41 -0600625 smsc95xx_set_multicast(priv);
Simon Glass246c1192011-06-13 16:13:09 -0700626
Simon Glass3faecae2015-07-07 20:53:41 -0600627 ret = smsc95xx_phy_initialize(udev, dev);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600628 if (ret < 0)
629 return ret;
Simon Glass3faecae2015-07-07 20:53:41 -0600630 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700631 if (ret < 0)
632 return ret;
633
634 /* enable PHY interrupts */
635 read_buf |= INT_EP_CTL_PHY_INT_;
636
Simon Glass3faecae2015-07-07 20:53:41 -0600637 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700638 if (ret < 0)
639 return ret;
640
Simon Glass3faecae2015-07-07 20:53:41 -0600641 smsc95xx_start_tx_path(udev, priv);
642 smsc95xx_start_rx_path(udev, priv);
Simon Glass246c1192011-06-13 16:13:09 -0700643
644 timeout = 0;
645 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600646 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
Simon Glass246c1192011-06-13 16:13:09 -0700647 & BMSR_LSTATUS;
648 if (!link_detected) {
649 if (timeout == 0)
650 printf("Waiting for Ethernet connection... ");
651 udelay(TIMEOUT_RESOLUTION * 1000);
652 timeout += TIMEOUT_RESOLUTION;
653 }
654 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
655 if (link_detected) {
656 if (timeout != 0)
657 printf("done.\n");
658 } else {
659 printf("unable to connect.\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600660 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700661 }
662 return 0;
663}
664
Simon Glass3faecae2015-07-07 20:53:41 -0600665static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
Simon Glass246c1192011-06-13 16:13:09 -0700666{
Simon Glass246c1192011-06-13 16:13:09 -0700667 int err;
668 int actual_len;
669 u32 tx_cmd_a;
670 u32 tx_cmd_b;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000671 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
672 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
Simon Glass246c1192011-06-13 16:13:09 -0700673
Prabhakar Kushwaha91d52542015-10-25 13:18:41 +0530674 debug("** %s(), len %d, buf %#x\n", __func__, length,
675 (unsigned int)(ulong)msg);
Simon Glass246c1192011-06-13 16:13:09 -0700676 if (length > PKTSIZE)
Simon Glassebe0e5a2015-07-07 20:53:40 -0600677 return -ENOSPC;
Simon Glass246c1192011-06-13 16:13:09 -0700678
679 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
680 tx_cmd_b = (u32)length;
681 cpu_to_le32s(&tx_cmd_a);
682 cpu_to_le32s(&tx_cmd_b);
683
684 /* prepend cmd_a and cmd_b */
685 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
686 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
687 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
688 length);
689 err = usb_bulk_msg(dev->pusb_dev,
690 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
691 (void *)msg,
692 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
693 &actual_len,
694 USB_BULK_SEND_TIMEOUT);
695 debug("Tx: len = %u, actual = %u, err = %d\n",
Prabhakar Kushwaha91d52542015-10-25 13:18:41 +0530696 (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
697 (unsigned int)actual_len, err);
Simon Glass3faecae2015-07-07 20:53:41 -0600698
Simon Glass246c1192011-06-13 16:13:09 -0700699 return err;
700}
701
Simon Glass68c41972015-07-07 20:53:42 -0600702static int smsc95xx_eth_start(struct udevice *dev)
703{
Simon Glassde44acf2015-09-28 23:32:01 -0600704 struct usb_device *udev = dev_get_parent_priv(dev);
Simon Glass68c41972015-07-07 20:53:42 -0600705 struct smsc95xx_private *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700706 struct eth_pdata *pdata = dev_get_plat(dev);
Simon Glass68c41972015-07-07 20:53:42 -0600707
708 /* Driver-model Ethernet ensures we have this */
709 priv->have_hwaddr = 1;
710
711 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
712}
713
714void smsc95xx_eth_stop(struct udevice *dev)
715{
716 debug("** %s()\n", __func__);
717}
718
719int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
720{
721 struct smsc95xx_private *priv = dev_get_priv(dev);
722
723 return smsc95xx_send_common(&priv->ueth, packet, length);
724}
725
726int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
727{
728 struct smsc95xx_private *priv = dev_get_priv(dev);
729 struct ueth_data *ueth = &priv->ueth;
730 uint8_t *ptr;
731 int ret, len;
732 u32 packet_len;
733
734 len = usb_ether_get_rx_bytes(ueth, &ptr);
735 debug("%s: first try, len=%d\n", __func__, len);
736 if (!len) {
737 if (!(flags & ETH_RECV_CHECK_DEVICE))
738 return -EAGAIN;
739 ret = usb_ether_receive(ueth, RX_URB_SIZE);
740 if (ret == -EAGAIN)
741 return ret;
742
743 len = usb_ether_get_rx_bytes(ueth, &ptr);
744 debug("%s: second try, len=%d\n", __func__, len);
745 }
746
747 /*
748 * 1st 4 bytes contain the length of the actual data plus error info.
749 * Extract data length.
750 */
751 if (len < sizeof(packet_len)) {
752 debug("Rx: incomplete packet length\n");
753 goto err;
754 }
755 memcpy(&packet_len, ptr, sizeof(packet_len));
756 le32_to_cpus(&packet_len);
757 if (packet_len & RX_STS_ES_) {
758 debug("Rx: Error header=%#x", packet_len);
759 goto err;
760 }
761 packet_len = ((packet_len & RX_STS_FL_) >> 16);
762
763 if (packet_len > len - sizeof(packet_len)) {
764 debug("Rx: too large packet: %d\n", packet_len);
765 goto err;
766 }
767
768 *packetp = ptr + sizeof(packet_len);
Simon Glassb8fa8362017-04-05 16:23:28 -0600769 return packet_len - 4;
Simon Glass68c41972015-07-07 20:53:42 -0600770
771err:
772 usb_ether_advance_rxbuf(ueth, -1);
773 return -EINVAL;
774}
775
776static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
777{
778 struct smsc95xx_private *priv = dev_get_priv(dev);
779
Simon Glassb8fa8362017-04-05 16:23:28 -0600780 packet_len = ALIGN(packet_len + sizeof(u32), 4);
Simon Glass68c41972015-07-07 20:53:42 -0600781 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
782
783 return 0;
784}
785
786int smsc95xx_write_hwaddr(struct udevice *dev)
787{
Simon Glassde44acf2015-09-28 23:32:01 -0600788 struct usb_device *udev = dev_get_parent_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700789 struct eth_pdata *pdata = dev_get_plat(dev);
Simon Glass68c41972015-07-07 20:53:42 -0600790 struct smsc95xx_private *priv = dev_get_priv(dev);
791
792 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
793}
794
Stephen Warrenc8bff832016-09-15 12:53:22 -0600795int smsc95xx_read_rom_hwaddr(struct udevice *dev)
796{
797 struct usb_device *udev = dev_get_parent_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700798 struct eth_pdata *pdata = dev_get_plat(dev);
Stephen Warrenc8bff832016-09-15 12:53:22 -0600799 int ret;
800
801 ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
802 if (ret)
803 memset(pdata->enetaddr, 0, 6);
804
805 return 0;
806}
807
Simon Glass68c41972015-07-07 20:53:42 -0600808static int smsc95xx_eth_probe(struct udevice *dev)
809{
810 struct smsc95xx_private *priv = dev_get_priv(dev);
811 struct ueth_data *ueth = &priv->ueth;
812
813 return usb_ether_register(dev, ueth, RX_URB_SIZE);
814}
815
816static const struct eth_ops smsc95xx_eth_ops = {
817 .start = smsc95xx_eth_start,
818 .send = smsc95xx_eth_send,
819 .recv = smsc95xx_eth_recv,
820 .free_pkt = smsc95xx_free_pkt,
821 .stop = smsc95xx_eth_stop,
822 .write_hwaddr = smsc95xx_write_hwaddr,
Stephen Warrenc8bff832016-09-15 12:53:22 -0600823 .read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
Simon Glass68c41972015-07-07 20:53:42 -0600824};
825
826U_BOOT_DRIVER(smsc95xx_eth) = {
827 .name = "smsc95xx_eth",
828 .id = UCLASS_ETH,
829 .probe = smsc95xx_eth_probe,
830 .ops = &smsc95xx_eth_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700831 .priv_auto = sizeof(struct smsc95xx_private),
Simon Glass71fa5b42020-12-03 16:55:18 -0700832 .plat_auto = sizeof(struct eth_pdata),
Simon Glass68c41972015-07-07 20:53:42 -0600833};
834
835static const struct usb_device_id smsc95xx_eth_id_table[] = {
836 { USB_DEVICE(0x05ac, 0x1402) },
837 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
838 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
839 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
840 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
841 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
842 { } /* Terminating entry */
843};
844
845U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);