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Simon Glass246c1192011-06-13 16:13:09 -07001/*
Simon Glass68c41972015-07-07 20:53:42 -06002 * Copyright (c) 2015 Google, Inc
Simon Glass246c1192011-06-13 16:13:09 -07003 * Copyright (c) 2011 The Chromium OS Authors.
4 * Copyright (C) 2009 NVIDIA, Corporation
Simon Glass00be89c2014-09-08 13:44:14 -06005 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
Simon Glass246c1192011-06-13 16:13:09 -07006 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Simon Glass246c1192011-06-13 16:13:09 -07008 */
9
10#include <common.h>
Simon Glass68c41972015-07-07 20:53:42 -060011#include <dm.h>
Simon Glassce48e502015-07-07 20:53:38 -060012#include <errno.h>
13#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060014#include <memalign.h>
Simon Glass246c1192011-06-13 16:13:09 -070015#include <usb.h>
Simon Glassce48e502015-07-07 20:53:38 -060016#include <asm/unaligned.h>
Simon Glass246c1192011-06-13 16:13:09 -070017#include <linux/mii.h>
18#include "usb_ether.h"
19
20/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
21
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -070022/* LED defines */
23#define LED_GPIO_CFG (0x24)
24#define LED_GPIO_CFG_SPD_LED (0x01000000)
25#define LED_GPIO_CFG_LNK_LED (0x00100000)
26#define LED_GPIO_CFG_FDX_LED (0x00010000)
27
Simon Glass246c1192011-06-13 16:13:09 -070028/* Tx command words */
29#define TX_CMD_A_FIRST_SEG_ 0x00002000
30#define TX_CMD_A_LAST_SEG_ 0x00001000
31
32/* Rx status word */
33#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
34#define RX_STS_ES_ 0x00008000 /* Error Summary */
35
36/* SCSRs */
37#define ID_REV 0x00
38
39#define INT_STS 0x08
40
41#define TX_CFG 0x10
42#define TX_CFG_ON_ 0x00000004
43
44#define HW_CFG 0x14
45#define HW_CFG_BIR_ 0x00001000
46#define HW_CFG_RXDOFF_ 0x00000600
47#define HW_CFG_MEF_ 0x00000020
48#define HW_CFG_BCE_ 0x00000002
49#define HW_CFG_LRST_ 0x00000008
50
51#define PM_CTRL 0x20
52#define PM_CTL_PHY_RST_ 0x00000010
53
54#define AFC_CFG 0x2C
55
56/*
57 * Hi watermark = 15.5Kb (~10 mtu pkts)
58 * low watermark = 3k (~2 mtu pkts)
59 * backpressure duration = ~ 350us
60 * Apply FC on any frame.
61 */
62#define AFC_CFG_DEFAULT 0x00F830A1
63
64#define E2P_CMD 0x30
65#define E2P_CMD_BUSY_ 0x80000000
66#define E2P_CMD_READ_ 0x00000000
67#define E2P_CMD_TIMEOUT_ 0x00000400
68#define E2P_CMD_LOADED_ 0x00000200
69#define E2P_CMD_ADDR_ 0x000001FF
70
71#define E2P_DATA 0x34
72
73#define BURST_CAP 0x38
74
75#define INT_EP_CTL 0x68
76#define INT_EP_CTL_PHY_INT_ 0x00008000
77
78#define BULK_IN_DLY 0x6C
79
80/* MAC CSRs */
81#define MAC_CR 0x100
82#define MAC_CR_MCPAS_ 0x00080000
83#define MAC_CR_PRMS_ 0x00040000
84#define MAC_CR_HPFILT_ 0x00002000
85#define MAC_CR_TXEN_ 0x00000008
86#define MAC_CR_RXEN_ 0x00000004
87
88#define ADDRH 0x104
89
90#define ADDRL 0x108
91
92#define MII_ADDR 0x114
93#define MII_WRITE_ 0x02
94#define MII_BUSY_ 0x01
95#define MII_READ_ 0x00 /* ~of MII Write bit */
96
97#define MII_DATA 0x118
98
99#define FLOW 0x11C
100
101#define VLAN1 0x120
102
103#define COE_CR 0x130
104#define Tx_COE_EN_ 0x00010000
105#define Rx_COE_EN_ 0x00000001
106
107/* Vendor-specific PHY Definitions */
108#define PHY_INT_SRC 29
109
110#define PHY_INT_MASK 30
111#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
112#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
113#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
114 PHY_INT_MASK_LINK_DOWN_)
115
116/* USB Vendor Requests */
117#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
118#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
119
120/* Some extra defines */
121#define HS_USB_PKT_SIZE 512
122#define FS_USB_PKT_SIZE 64
Stefan Brünsd3095fe2015-08-30 17:59:45 +0200123/* 5/33 is lower limit for BURST_CAP to work */
124#define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
125#define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
Simon Glass246c1192011-06-13 16:13:09 -0700126#define DEFAULT_BULK_IN_DELAY 0x00002000
127#define MAX_SINGLE_PACKET_SIZE 2048
128#define EEPROM_MAC_OFFSET 0x01
129#define SMSC95XX_INTERNAL_PHY_ID 1
130#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
131
132/* local defines */
133#define SMSC95XX_BASE_NAME "sms"
134#define USB_CTRL_SET_TIMEOUT 5000
135#define USB_CTRL_GET_TIMEOUT 5000
136#define USB_BULK_SEND_TIMEOUT 5000
137#define USB_BULK_RECV_TIMEOUT 5000
138
Stefan Brünsd3095fe2015-08-30 17:59:45 +0200139#define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
Simon Glass246c1192011-06-13 16:13:09 -0700140#define PHY_CONNECT_TIMEOUT 5000
141
142#define TURBO_MODE
143
Simon Glass68c41972015-07-07 20:53:42 -0600144#ifndef CONFIG_DM_ETH
Simon Glass246c1192011-06-13 16:13:09 -0700145/* local vars */
146static int curr_eth_dev; /* index for name of next device detected */
Simon Glass68c41972015-07-07 20:53:42 -0600147#endif
Simon Glass246c1192011-06-13 16:13:09 -0700148
Lucas Stach36267c42012-08-22 11:04:57 +0000149/* driver private */
150struct smsc95xx_private {
Simon Glass68c41972015-07-07 20:53:42 -0600151#ifdef CONFIG_DM_ETH
152 struct ueth_data ueth;
153#endif
Lucas Stach36267c42012-08-22 11:04:57 +0000154 size_t rx_urb_size; /* maximum USB URB size */
155 u32 mac_cr; /* MAC control register value */
156 int have_hwaddr; /* 1 if we have a hardware MAC address */
157};
Simon Glass246c1192011-06-13 16:13:09 -0700158
159/*
160 * Smsc95xx infrastructure commands
161 */
Simon Glass3faecae2015-07-07 20:53:41 -0600162static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
Simon Glass246c1192011-06-13 16:13:09 -0700163{
164 int len;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000165 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass246c1192011-06-13 16:13:09 -0700166
167 cpu_to_le32s(&data);
Ilya Yanok43b56c22012-07-15 04:43:53 +0000168 tmpbuf[0] = data;
Simon Glass246c1192011-06-13 16:13:09 -0700169
Simon Glass3faecae2015-07-07 20:53:41 -0600170 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
171 USB_VENDOR_REQUEST_WRITE_REGISTER,
172 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
173 0, index, tmpbuf, sizeof(data),
174 USB_CTRL_SET_TIMEOUT);
Simon Glass246c1192011-06-13 16:13:09 -0700175 if (len != sizeof(data)) {
176 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
177 index, data, len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600178 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700179 }
180 return 0;
181}
182
Simon Glass3faecae2015-07-07 20:53:41 -0600183static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
Simon Glass246c1192011-06-13 16:13:09 -0700184{
185 int len;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000186 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass246c1192011-06-13 16:13:09 -0700187
Simon Glass3faecae2015-07-07 20:53:41 -0600188 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
189 USB_VENDOR_REQUEST_READ_REGISTER,
190 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
Stephen Warrenb0e5b492016-03-22 22:28:16 -0600191 0, index, tmpbuf, sizeof(*data),
Simon Glass3faecae2015-07-07 20:53:41 -0600192 USB_CTRL_GET_TIMEOUT);
Ilya Yanok43b56c22012-07-15 04:43:53 +0000193 *data = tmpbuf[0];
Stephen Warrenb0e5b492016-03-22 22:28:16 -0600194 if (len != sizeof(*data)) {
Simon Glass246c1192011-06-13 16:13:09 -0700195 debug("smsc95xx_read_reg failed: index=%d, len=%d",
196 index, len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600197 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700198 }
199
200 le32_to_cpus(data);
201 return 0;
202}
203
204/* Loop until the read is completed with timeout */
Simon Glass3faecae2015-07-07 20:53:41 -0600205static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700206{
207 unsigned long start_time = get_timer(0);
208 u32 val;
209
210 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600211 smsc95xx_read_reg(udev, MII_ADDR, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700212 if (!(val & MII_BUSY_))
213 return 0;
Simon Glass3faecae2015-07-07 20:53:41 -0600214 } while (get_timer(start_time) < 1000);
Simon Glass246c1192011-06-13 16:13:09 -0700215
Simon Glassebe0e5a2015-07-07 20:53:40 -0600216 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700217}
218
Simon Glass3faecae2015-07-07 20:53:41 -0600219static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
Simon Glass246c1192011-06-13 16:13:09 -0700220{
221 u32 val, addr;
222
223 /* confirm MII not busy */
Simon Glass3faecae2015-07-07 20:53:41 -0600224 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700225 debug("MII is busy in smsc95xx_mdio_read\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600226 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700227 }
228
229 /* set the address, index & direction (read from PHY) */
230 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
Simon Glass3faecae2015-07-07 20:53:41 -0600231 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass246c1192011-06-13 16:13:09 -0700232
Simon Glass3faecae2015-07-07 20:53:41 -0600233 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700234 debug("Timed out reading MII reg %02X\n", idx);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600235 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700236 }
237
Simon Glass3faecae2015-07-07 20:53:41 -0600238 smsc95xx_read_reg(udev, MII_DATA, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700239
240 return (u16)(val & 0xFFFF);
241}
242
Simon Glass3faecae2015-07-07 20:53:41 -0600243static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
Simon Glass246c1192011-06-13 16:13:09 -0700244 int regval)
245{
246 u32 val, addr;
247
248 /* confirm MII not busy */
Simon Glass3faecae2015-07-07 20:53:41 -0600249 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700250 debug("MII is busy in smsc95xx_mdio_write\n");
251 return;
252 }
253
254 val = regval;
Simon Glass3faecae2015-07-07 20:53:41 -0600255 smsc95xx_write_reg(udev, MII_DATA, val);
Simon Glass246c1192011-06-13 16:13:09 -0700256
257 /* set the address, index & direction (write to PHY) */
258 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
Simon Glass3faecae2015-07-07 20:53:41 -0600259 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass246c1192011-06-13 16:13:09 -0700260
Simon Glass3faecae2015-07-07 20:53:41 -0600261 if (smsc95xx_phy_wait_not_busy(udev))
Simon Glass246c1192011-06-13 16:13:09 -0700262 debug("Timed out writing MII reg %02X\n", idx);
263}
264
Simon Glass3faecae2015-07-07 20:53:41 -0600265static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700266{
267 unsigned long start_time = get_timer(0);
268 u32 val;
269
270 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600271 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700272 if (!(val & E2P_CMD_BUSY_))
273 return 0;
274 udelay(40);
275 } while (get_timer(start_time) < 1 * 1000 * 1000);
276
277 debug("EEPROM is busy\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600278 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700279}
280
Simon Glass3faecae2015-07-07 20:53:41 -0600281static int smsc95xx_wait_eeprom(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700282{
283 unsigned long start_time = get_timer(0);
284 u32 val;
285
286 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600287 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700288 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
289 break;
290 udelay(40);
291 } while (get_timer(start_time) < 1 * 1000 * 1000);
292
293 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
294 debug("EEPROM read operation timeout\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600295 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700296 }
297 return 0;
298}
299
Simon Glass3faecae2015-07-07 20:53:41 -0600300static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
Simon Glass246c1192011-06-13 16:13:09 -0700301 u8 *data)
302{
303 u32 val;
304 int i, ret;
305
Simon Glass3faecae2015-07-07 20:53:41 -0600306 ret = smsc95xx_eeprom_confirm_not_busy(udev);
Simon Glass246c1192011-06-13 16:13:09 -0700307 if (ret)
308 return ret;
309
310 for (i = 0; i < length; i++) {
311 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
Simon Glass3faecae2015-07-07 20:53:41 -0600312 smsc95xx_write_reg(udev, E2P_CMD, val);
Simon Glass246c1192011-06-13 16:13:09 -0700313
Simon Glass3faecae2015-07-07 20:53:41 -0600314 ret = smsc95xx_wait_eeprom(udev);
Simon Glass246c1192011-06-13 16:13:09 -0700315 if (ret < 0)
316 return ret;
317
Simon Glass3faecae2015-07-07 20:53:41 -0600318 smsc95xx_read_reg(udev, E2P_DATA, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700319 data[i] = val & 0xFF;
320 offset++;
321 }
322 return 0;
323}
324
325/*
326 * mii_nway_restart - restart NWay (autonegotiation) for this interface
327 *
328 * Returns 0 on success, negative on error.
329 */
Simon Glass3faecae2015-07-07 20:53:41 -0600330static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
Simon Glass246c1192011-06-13 16:13:09 -0700331{
332 int bmcr;
333 int r = -1;
334
335 /* if autoneg is off, it's an error */
Simon Glass3faecae2015-07-07 20:53:41 -0600336 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
Simon Glass246c1192011-06-13 16:13:09 -0700337
338 if (bmcr & BMCR_ANENABLE) {
339 bmcr |= BMCR_ANRESTART;
Simon Glass3faecae2015-07-07 20:53:41 -0600340 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
Simon Glass246c1192011-06-13 16:13:09 -0700341 r = 0;
342 }
343 return r;
344}
345
Simon Glass3faecae2015-07-07 20:53:41 -0600346static int smsc95xx_phy_initialize(struct usb_device *udev,
347 struct ueth_data *dev)
Simon Glass246c1192011-06-13 16:13:09 -0700348{
Simon Glass3faecae2015-07-07 20:53:41 -0600349 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
350 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
351 ADVERTISE_ALL | ADVERTISE_CSMA |
352 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Simon Glass246c1192011-06-13 16:13:09 -0700353
354 /* read to clear */
Simon Glass3faecae2015-07-07 20:53:41 -0600355 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
Simon Glass246c1192011-06-13 16:13:09 -0700356
Simon Glass3faecae2015-07-07 20:53:41 -0600357 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
358 PHY_INT_MASK_DEFAULT_);
359 mii_nway_restart(udev, dev);
Simon Glass246c1192011-06-13 16:13:09 -0700360
361 debug("phy initialised succesfully\n");
362 return 0;
363}
364
Simon Glass3faecae2015-07-07 20:53:41 -0600365static int smsc95xx_init_mac_address(unsigned char *enetaddr,
366 struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700367{
Simon Glass3faecae2015-07-07 20:53:41 -0600368 int ret;
369
Simon Glass246c1192011-06-13 16:13:09 -0700370 /* try reading mac address from EEPROM */
Simon Glass3faecae2015-07-07 20:53:41 -0600371 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
372 if (ret)
373 return ret;
374
375 if (is_valid_ethaddr(enetaddr)) {
376 /* eeprom values are valid so use them */
377 debug("MAC address read from EEPROM\n");
378 return 0;
Simon Glass246c1192011-06-13 16:13:09 -0700379 }
380
381 /*
382 * No eeprom, or eeprom values are invalid. Generating a random MAC
383 * address is not safe. Just return an error.
384 */
Simon Glassebe0e5a2015-07-07 20:53:40 -0600385 debug("Invalid MAC address read from EEPROM\n");
386
387 return -ENXIO;
Simon Glass246c1192011-06-13 16:13:09 -0700388}
389
Simon Glass3faecae2015-07-07 20:53:41 -0600390static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
391 struct smsc95xx_private *priv,
392 unsigned char *enetaddr)
Simon Glass246c1192011-06-13 16:13:09 -0700393{
Simon Glass3faecae2015-07-07 20:53:41 -0600394 u32 addr_lo = __get_unaligned_le32(&enetaddr[0]);
395 u32 addr_hi = __get_unaligned_le16(&enetaddr[4]);
Simon Glass246c1192011-06-13 16:13:09 -0700396 int ret;
397
398 /* set hardware address */
399 debug("** %s()\n", __func__);
Simon Glass3faecae2015-07-07 20:53:41 -0600400 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
Wolfgang Grandeggerf9af1f82011-11-14 23:19:15 +0000401 if (ret < 0)
Simon Glass246c1192011-06-13 16:13:09 -0700402 return ret;
Simon Glass246c1192011-06-13 16:13:09 -0700403
Simon Glass3faecae2015-07-07 20:53:41 -0600404 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
Simon Glass246c1192011-06-13 16:13:09 -0700405 if (ret < 0)
406 return ret;
Wolfgang Grandeggerf9af1f82011-11-14 23:19:15 +0000407
Simon Glass3faecae2015-07-07 20:53:41 -0600408 debug("MAC %pM\n", enetaddr);
Lucas Stach36267c42012-08-22 11:04:57 +0000409 priv->have_hwaddr = 1;
Simon Glass3faecae2015-07-07 20:53:41 -0600410
Simon Glass246c1192011-06-13 16:13:09 -0700411 return 0;
412}
413
414/* Enable or disable Tx & Rx checksum offload engines */
Simon Glass3faecae2015-07-07 20:53:41 -0600415static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
416 int use_rx_csum)
Simon Glass246c1192011-06-13 16:13:09 -0700417{
418 u32 read_buf;
Simon Glass3faecae2015-07-07 20:53:41 -0600419 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700420 if (ret < 0)
421 return ret;
422
423 if (use_tx_csum)
424 read_buf |= Tx_COE_EN_;
425 else
426 read_buf &= ~Tx_COE_EN_;
427
428 if (use_rx_csum)
429 read_buf |= Rx_COE_EN_;
430 else
431 read_buf &= ~Rx_COE_EN_;
432
Simon Glass3faecae2015-07-07 20:53:41 -0600433 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700434 if (ret < 0)
435 return ret;
436
437 debug("COE_CR = 0x%08x\n", read_buf);
438 return 0;
439}
440
Simon Glass3faecae2015-07-07 20:53:41 -0600441static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700442{
443 /* No multicast in u-boot */
Lucas Stach36267c42012-08-22 11:04:57 +0000444 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
Simon Glass246c1192011-06-13 16:13:09 -0700445}
446
447/* starts the TX path */
Simon Glass3faecae2015-07-07 20:53:41 -0600448static void smsc95xx_start_tx_path(struct usb_device *udev,
449 struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700450{
451 u32 reg_val;
452
453 /* Enable Tx at MAC */
Lucas Stach36267c42012-08-22 11:04:57 +0000454 priv->mac_cr |= MAC_CR_TXEN_;
Simon Glass246c1192011-06-13 16:13:09 -0700455
Simon Glass3faecae2015-07-07 20:53:41 -0600456 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700457
458 /* Enable Tx at SCSRs */
459 reg_val = TX_CFG_ON_;
Simon Glass3faecae2015-07-07 20:53:41 -0600460 smsc95xx_write_reg(udev, TX_CFG, reg_val);
Simon Glass246c1192011-06-13 16:13:09 -0700461}
462
463/* Starts the Receive path */
Simon Glass3faecae2015-07-07 20:53:41 -0600464static void smsc95xx_start_rx_path(struct usb_device *udev,
465 struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700466{
Lucas Stach36267c42012-08-22 11:04:57 +0000467 priv->mac_cr |= MAC_CR_RXEN_;
Simon Glass3faecae2015-07-07 20:53:41 -0600468 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700469}
470
Simon Glass3faecae2015-07-07 20:53:41 -0600471static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
472 struct smsc95xx_private *priv,
473 unsigned char *enetaddr)
Simon Glass246c1192011-06-13 16:13:09 -0700474{
475 int ret;
476 u32 write_buf;
477 u32 read_buf;
478 u32 burst_cap;
479 int timeout;
Simon Glass246c1192011-06-13 16:13:09 -0700480#define TIMEOUT_RESOLUTION 50 /* ms */
481 int link_detected;
482
483 debug("** %s()\n", __func__);
484 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
485
486 write_buf = HW_CFG_LRST_;
Simon Glass3faecae2015-07-07 20:53:41 -0600487 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700488 if (ret < 0)
489 return ret;
490
491 timeout = 0;
492 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600493 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700494 if (ret < 0)
495 return ret;
496 udelay(10 * 1000);
497 timeout++;
498 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
499
500 if (timeout >= 100) {
501 debug("timeout waiting for completion of Lite Reset\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600502 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700503 }
504
505 write_buf = PM_CTL_PHY_RST_;
Simon Glass3faecae2015-07-07 20:53:41 -0600506 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700507 if (ret < 0)
508 return ret;
509
510 timeout = 0;
511 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600512 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700513 if (ret < 0)
514 return ret;
515 udelay(10 * 1000);
516 timeout++;
517 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
518 if (timeout >= 100) {
519 debug("timeout waiting for PHY Reset\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600520 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700521 }
Simon Glass3faecae2015-07-07 20:53:41 -0600522 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
523 0)
Lucas Stach36267c42012-08-22 11:04:57 +0000524 priv->have_hwaddr = 1;
525 if (!priv->have_hwaddr) {
Simon Glass246c1192011-06-13 16:13:09 -0700526 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600527 return -EADDRNOTAVAIL;
Simon Glass246c1192011-06-13 16:13:09 -0700528 }
Simon Glass3faecae2015-07-07 20:53:41 -0600529 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600530 if (ret < 0)
531 return ret;
Simon Glass246c1192011-06-13 16:13:09 -0700532
Simon Glass246c1192011-06-13 16:13:09 -0700533#ifdef TURBO_MODE
534 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
535 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
Lucas Stach36267c42012-08-22 11:04:57 +0000536 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700537 } else {
538 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
Lucas Stach36267c42012-08-22 11:04:57 +0000539 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700540 }
541#else
542 burst_cap = 0;
Lucas Stach36267c42012-08-22 11:04:57 +0000543 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700544#endif
Lucas Stach36267c42012-08-22 11:04:57 +0000545 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
Simon Glass246c1192011-06-13 16:13:09 -0700546
Simon Glass3faecae2015-07-07 20:53:41 -0600547 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
Simon Glass246c1192011-06-13 16:13:09 -0700548 if (ret < 0)
549 return ret;
550
Simon Glass3faecae2015-07-07 20:53:41 -0600551 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700552 if (ret < 0)
553 return ret;
554 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
555
556 read_buf = DEFAULT_BULK_IN_DELAY;
Simon Glass3faecae2015-07-07 20:53:41 -0600557 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700558 if (ret < 0)
559 return ret;
560
Simon Glass3faecae2015-07-07 20:53:41 -0600561 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700562 if (ret < 0)
563 return ret;
564 debug("Read Value from BULK_IN_DLY after writing: "
565 "0x%08x\n", read_buf);
566
Simon Glass3faecae2015-07-07 20:53:41 -0600567 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700568 if (ret < 0)
569 return ret;
570 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
571
572#ifdef TURBO_MODE
573 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
574#endif
575 read_buf &= ~HW_CFG_RXDOFF_;
576
577#define NET_IP_ALIGN 0
578 read_buf |= NET_IP_ALIGN << 9;
579
Simon Glass3faecae2015-07-07 20:53:41 -0600580 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700581 if (ret < 0)
582 return ret;
583
Simon Glass3faecae2015-07-07 20:53:41 -0600584 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700585 if (ret < 0)
586 return ret;
587 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
588
589 write_buf = 0xFFFFFFFF;
Simon Glass3faecae2015-07-07 20:53:41 -0600590 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700591 if (ret < 0)
592 return ret;
593
Simon Glass3faecae2015-07-07 20:53:41 -0600594 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700595 if (ret < 0)
596 return ret;
597 debug("ID_REV = 0x%08x\n", read_buf);
598
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -0700599 /* Configure GPIO pins as LED outputs */
600 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
601 LED_GPIO_CFG_FDX_LED;
Simon Glass3faecae2015-07-07 20:53:41 -0600602 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -0700603 if (ret < 0)
604 return ret;
605 debug("LED_GPIO_CFG set\n");
606
Simon Glass246c1192011-06-13 16:13:09 -0700607 /* Init Tx */
608 write_buf = 0;
Simon Glass3faecae2015-07-07 20:53:41 -0600609 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700610 if (ret < 0)
611 return ret;
612
613 read_buf = AFC_CFG_DEFAULT;
Simon Glass3faecae2015-07-07 20:53:41 -0600614 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700615 if (ret < 0)
616 return ret;
617
Simon Glass3faecae2015-07-07 20:53:41 -0600618 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700619 if (ret < 0)
620 return ret;
621
622 /* Init Rx. Set Vlan */
623 write_buf = (u32)ETH_P_8021Q;
Simon Glass3faecae2015-07-07 20:53:41 -0600624 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700625 if (ret < 0)
626 return ret;
627
628 /* Disable checksum offload engines */
Simon Glass3faecae2015-07-07 20:53:41 -0600629 ret = smsc95xx_set_csums(udev, 0, 0);
Simon Glass246c1192011-06-13 16:13:09 -0700630 if (ret < 0) {
631 debug("Failed to set csum offload: %d\n", ret);
632 return ret;
633 }
Simon Glass3faecae2015-07-07 20:53:41 -0600634 smsc95xx_set_multicast(priv);
Simon Glass246c1192011-06-13 16:13:09 -0700635
Simon Glass3faecae2015-07-07 20:53:41 -0600636 ret = smsc95xx_phy_initialize(udev, dev);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600637 if (ret < 0)
638 return ret;
Simon Glass3faecae2015-07-07 20:53:41 -0600639 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700640 if (ret < 0)
641 return ret;
642
643 /* enable PHY interrupts */
644 read_buf |= INT_EP_CTL_PHY_INT_;
645
Simon Glass3faecae2015-07-07 20:53:41 -0600646 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700647 if (ret < 0)
648 return ret;
649
Simon Glass3faecae2015-07-07 20:53:41 -0600650 smsc95xx_start_tx_path(udev, priv);
651 smsc95xx_start_rx_path(udev, priv);
Simon Glass246c1192011-06-13 16:13:09 -0700652
653 timeout = 0;
654 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600655 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
Simon Glass246c1192011-06-13 16:13:09 -0700656 & BMSR_LSTATUS;
657 if (!link_detected) {
658 if (timeout == 0)
659 printf("Waiting for Ethernet connection... ");
660 udelay(TIMEOUT_RESOLUTION * 1000);
661 timeout += TIMEOUT_RESOLUTION;
662 }
663 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
664 if (link_detected) {
665 if (timeout != 0)
666 printf("done.\n");
667 } else {
668 printf("unable to connect.\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600669 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700670 }
671 return 0;
672}
673
Simon Glass3faecae2015-07-07 20:53:41 -0600674static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
Simon Glass246c1192011-06-13 16:13:09 -0700675{
Simon Glass246c1192011-06-13 16:13:09 -0700676 int err;
677 int actual_len;
678 u32 tx_cmd_a;
679 u32 tx_cmd_b;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000680 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
681 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
Simon Glass246c1192011-06-13 16:13:09 -0700682
Prabhakar Kushwaha91d52542015-10-25 13:18:41 +0530683 debug("** %s(), len %d, buf %#x\n", __func__, length,
684 (unsigned int)(ulong)msg);
Simon Glass246c1192011-06-13 16:13:09 -0700685 if (length > PKTSIZE)
Simon Glassebe0e5a2015-07-07 20:53:40 -0600686 return -ENOSPC;
Simon Glass246c1192011-06-13 16:13:09 -0700687
688 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
689 tx_cmd_b = (u32)length;
690 cpu_to_le32s(&tx_cmd_a);
691 cpu_to_le32s(&tx_cmd_b);
692
693 /* prepend cmd_a and cmd_b */
694 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
695 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
696 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
697 length);
698 err = usb_bulk_msg(dev->pusb_dev,
699 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
700 (void *)msg,
701 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
702 &actual_len,
703 USB_BULK_SEND_TIMEOUT);
704 debug("Tx: len = %u, actual = %u, err = %d\n",
Prabhakar Kushwaha91d52542015-10-25 13:18:41 +0530705 (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
706 (unsigned int)actual_len, err);
Simon Glass3faecae2015-07-07 20:53:41 -0600707
Simon Glass246c1192011-06-13 16:13:09 -0700708 return err;
709}
710
Simon Glass68c41972015-07-07 20:53:42 -0600711#ifndef CONFIG_DM_ETH
Simon Glass3faecae2015-07-07 20:53:41 -0600712/*
713 * Smsc95xx callbacks
714 */
715static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
716{
717 struct ueth_data *dev = (struct ueth_data *)eth->priv;
718 struct usb_device *udev = dev->pusb_dev;
719 struct smsc95xx_private *priv =
720 (struct smsc95xx_private *)dev->dev_priv;
721
722 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
723}
724
725static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
726{
727 struct ueth_data *dev = (struct ueth_data *)eth->priv;
728
729 return smsc95xx_send_common(dev, packet, length);
730}
731
Simon Glass246c1192011-06-13 16:13:09 -0700732static int smsc95xx_recv(struct eth_device *eth)
733{
734 struct ueth_data *dev = (struct ueth_data *)eth->priv;
Simon Glass4d89e5b2015-07-07 20:53:39 -0600735 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
Simon Glass246c1192011-06-13 16:13:09 -0700736 unsigned char *buf_ptr;
737 int err;
738 int actual_len;
739 u32 packet_len;
740 int cur_buf_align;
741
742 debug("** %s()\n", __func__);
743 err = usb_bulk_msg(dev->pusb_dev,
Simon Glass3faecae2015-07-07 20:53:41 -0600744 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
745 (void *)recv_buf, RX_URB_SIZE, &actual_len,
746 USB_BULK_RECV_TIMEOUT);
Simon Glass4d89e5b2015-07-07 20:53:39 -0600747 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
Simon Glass246c1192011-06-13 16:13:09 -0700748 actual_len, err);
749 if (err != 0) {
750 debug("Rx: failed to receive\n");
Simon Glass3faecae2015-07-07 20:53:41 -0600751 return -err;
Simon Glass246c1192011-06-13 16:13:09 -0700752 }
Simon Glass4d89e5b2015-07-07 20:53:39 -0600753 if (actual_len > RX_URB_SIZE) {
Simon Glass246c1192011-06-13 16:13:09 -0700754 debug("Rx: received too many bytes %d\n", actual_len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600755 return -ENOSPC;
Simon Glass246c1192011-06-13 16:13:09 -0700756 }
757
758 buf_ptr = recv_buf;
759 while (actual_len > 0) {
760 /*
761 * 1st 4 bytes contain the length of the actual data plus error
762 * info. Extract data length.
763 */
764 if (actual_len < sizeof(packet_len)) {
765 debug("Rx: incomplete packet length\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600766 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700767 }
768 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
769 le32_to_cpus(&packet_len);
770 if (packet_len & RX_STS_ES_) {
771 debug("Rx: Error header=%#x", packet_len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600772 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700773 }
774 packet_len = ((packet_len & RX_STS_FL_) >> 16);
775
776 if (packet_len > actual_len - sizeof(packet_len)) {
777 debug("Rx: too large packet: %d\n", packet_len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600778 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700779 }
780
781 /* Notify net stack */
Joe Hershberger9f09a362015-04-08 01:41:06 -0500782 net_process_received_packet(buf_ptr + sizeof(packet_len),
783 packet_len - 4);
Simon Glass246c1192011-06-13 16:13:09 -0700784
785 /* Adjust for next iteration */
786 actual_len -= sizeof(packet_len) + packet_len;
787 buf_ptr += sizeof(packet_len) + packet_len;
Prabhakar Kushwaha91d52542015-10-25 13:18:41 +0530788 cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
Simon Glass246c1192011-06-13 16:13:09 -0700789
790 if (cur_buf_align & 0x03) {
791 int align = 4 - (cur_buf_align & 0x03);
792
793 actual_len -= align;
794 buf_ptr += align;
795 }
796 }
797 return err;
798}
799
800static void smsc95xx_halt(struct eth_device *eth)
801{
802 debug("** %s()\n", __func__);
803}
804
Simon Glass3faecae2015-07-07 20:53:41 -0600805static int smsc95xx_write_hwaddr(struct eth_device *eth)
806{
807 struct ueth_data *dev = eth->priv;
808 struct usb_device *udev = dev->pusb_dev;
809 struct smsc95xx_private *priv = dev->dev_priv;
810
811 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
812}
813
Simon Glass246c1192011-06-13 16:13:09 -0700814/*
815 * SMSC probing functions
816 */
817void smsc95xx_eth_before_probe(void)
818{
819 curr_eth_dev = 0;
820}
821
822struct smsc95xx_dongle {
823 unsigned short vendor;
824 unsigned short product;
825};
826
827static const struct smsc95xx_dongle smsc95xx_dongles[] = {
828 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
829 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
Lubomir Popov7ca25b62013-04-01 04:50:55 +0000830 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
Stefan Roese8aa7b042013-07-03 18:34:54 +0200831 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
Ilya Ledvich180bb6a2014-03-12 10:36:31 +0200832 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
Simon Glass246c1192011-06-13 16:13:09 -0700833 { 0x0000, 0x0000 } /* END - Do not remove */
834};
835
836/* Probe to see if a new device is actually an SMSC device */
837int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
838 struct ueth_data *ss)
839{
840 struct usb_interface *iface;
841 struct usb_interface_descriptor *iface_desc;
842 int i;
843
844 /* let's examine the device now */
845 iface = &dev->config.if_desc[ifnum];
846 iface_desc = &dev->config.if_desc[ifnum].desc;
847
848 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
849 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
850 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
851 /* Found a supported dongle */
852 break;
853 }
854 if (smsc95xx_dongles[i].vendor == 0)
855 return 0;
856
857 /* At this point, we know we've got a live one */
858 debug("\n\nUSB Ethernet device detected\n");
859 memset(ss, '\0', sizeof(struct ueth_data));
860
861 /* Initialize the ueth_data structure with some useful info */
862 ss->ifnum = ifnum;
863 ss->pusb_dev = dev;
864 ss->subclass = iface_desc->bInterfaceSubClass;
865 ss->protocol = iface_desc->bInterfaceProtocol;
866
867 /*
868 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
869 * We will ignore any others.
870 */
871 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
872 /* is it an BULK endpoint? */
873 if ((iface->ep_desc[i].bmAttributes &
874 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
875 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
876 ss->ep_in =
877 iface->ep_desc[i].bEndpointAddress &
878 USB_ENDPOINT_NUMBER_MASK;
879 else
880 ss->ep_out =
881 iface->ep_desc[i].bEndpointAddress &
882 USB_ENDPOINT_NUMBER_MASK;
883 }
884
885 /* is it an interrupt endpoint? */
886 if ((iface->ep_desc[i].bmAttributes &
887 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
888 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
889 USB_ENDPOINT_NUMBER_MASK;
890 ss->irqinterval = iface->ep_desc[i].bInterval;
891 }
892 }
893 debug("Endpoints In %d Out %d Int %d\n",
894 ss->ep_in, ss->ep_out, ss->ep_int);
895
896 /* Do some basic sanity checks, and bail if we find a problem */
897 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
898 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
899 debug("Problems with device\n");
900 return 0;
901 }
902 dev->privptr = (void *)ss;
Lucas Stach36267c42012-08-22 11:04:57 +0000903
904 /* alloc driver private */
905 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
906 if (!ss->dev_priv)
907 return 0;
908
Simon Glass246c1192011-06-13 16:13:09 -0700909 return 1;
910}
911
912int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
913 struct eth_device *eth)
914{
915 debug("** %s()\n", __func__);
916 if (!eth) {
917 debug("%s: missing parameter.\n", __func__);
918 return 0;
919 }
920 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
921 eth->init = smsc95xx_init;
922 eth->send = smsc95xx_send;
923 eth->recv = smsc95xx_recv;
924 eth->halt = smsc95xx_halt;
925 eth->write_hwaddr = smsc95xx_write_hwaddr;
926 eth->priv = ss;
927 return 1;
928}
Simon Glass68c41972015-07-07 20:53:42 -0600929#endif /* !CONFIG_DM_ETH */
930
931#ifdef CONFIG_DM_ETH
932static int smsc95xx_eth_start(struct udevice *dev)
933{
Simon Glassde44acf2015-09-28 23:32:01 -0600934 struct usb_device *udev = dev_get_parent_priv(dev);
Simon Glass68c41972015-07-07 20:53:42 -0600935 struct smsc95xx_private *priv = dev_get_priv(dev);
936 struct eth_pdata *pdata = dev_get_platdata(dev);
937
938 /* Driver-model Ethernet ensures we have this */
939 priv->have_hwaddr = 1;
940
941 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
942}
943
944void smsc95xx_eth_stop(struct udevice *dev)
945{
946 debug("** %s()\n", __func__);
947}
948
949int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
950{
951 struct smsc95xx_private *priv = dev_get_priv(dev);
952
953 return smsc95xx_send_common(&priv->ueth, packet, length);
954}
955
956int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
957{
958 struct smsc95xx_private *priv = dev_get_priv(dev);
959 struct ueth_data *ueth = &priv->ueth;
960 uint8_t *ptr;
961 int ret, len;
962 u32 packet_len;
963
964 len = usb_ether_get_rx_bytes(ueth, &ptr);
965 debug("%s: first try, len=%d\n", __func__, len);
966 if (!len) {
967 if (!(flags & ETH_RECV_CHECK_DEVICE))
968 return -EAGAIN;
969 ret = usb_ether_receive(ueth, RX_URB_SIZE);
970 if (ret == -EAGAIN)
971 return ret;
972
973 len = usb_ether_get_rx_bytes(ueth, &ptr);
974 debug("%s: second try, len=%d\n", __func__, len);
975 }
976
977 /*
978 * 1st 4 bytes contain the length of the actual data plus error info.
979 * Extract data length.
980 */
981 if (len < sizeof(packet_len)) {
982 debug("Rx: incomplete packet length\n");
983 goto err;
984 }
985 memcpy(&packet_len, ptr, sizeof(packet_len));
986 le32_to_cpus(&packet_len);
987 if (packet_len & RX_STS_ES_) {
988 debug("Rx: Error header=%#x", packet_len);
989 goto err;
990 }
991 packet_len = ((packet_len & RX_STS_FL_) >> 16);
992
993 if (packet_len > len - sizeof(packet_len)) {
994 debug("Rx: too large packet: %d\n", packet_len);
995 goto err;
996 }
997
998 *packetp = ptr + sizeof(packet_len);
999 return packet_len;
1000
1001err:
1002 usb_ether_advance_rxbuf(ueth, -1);
1003 return -EINVAL;
1004}
1005
1006static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1007{
1008 struct smsc95xx_private *priv = dev_get_priv(dev);
1009
1010 packet_len = ALIGN(packet_len, 4);
1011 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
1012
1013 return 0;
1014}
1015
1016int smsc95xx_write_hwaddr(struct udevice *dev)
1017{
Simon Glassde44acf2015-09-28 23:32:01 -06001018 struct usb_device *udev = dev_get_parent_priv(dev);
Simon Glass68c41972015-07-07 20:53:42 -06001019 struct eth_pdata *pdata = dev_get_platdata(dev);
1020 struct smsc95xx_private *priv = dev_get_priv(dev);
1021
1022 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
1023}
1024
1025static int smsc95xx_eth_probe(struct udevice *dev)
1026{
1027 struct smsc95xx_private *priv = dev_get_priv(dev);
1028 struct ueth_data *ueth = &priv->ueth;
1029
1030 return usb_ether_register(dev, ueth, RX_URB_SIZE);
1031}
1032
1033static const struct eth_ops smsc95xx_eth_ops = {
1034 .start = smsc95xx_eth_start,
1035 .send = smsc95xx_eth_send,
1036 .recv = smsc95xx_eth_recv,
1037 .free_pkt = smsc95xx_free_pkt,
1038 .stop = smsc95xx_eth_stop,
1039 .write_hwaddr = smsc95xx_write_hwaddr,
1040};
1041
1042U_BOOT_DRIVER(smsc95xx_eth) = {
1043 .name = "smsc95xx_eth",
1044 .id = UCLASS_ETH,
1045 .probe = smsc95xx_eth_probe,
1046 .ops = &smsc95xx_eth_ops,
1047 .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
1048 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1049};
1050
1051static const struct usb_device_id smsc95xx_eth_id_table[] = {
1052 { USB_DEVICE(0x05ac, 0x1402) },
1053 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
1054 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
1055 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
1056 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
1057 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
1058 { } /* Terminating entry */
1059};
1060
1061U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
1062#endif